mirror of
https://github.com/zeldaret/ss
synced 2026-05-25 23:35:13 -04:00
Elijah Thomas
26af4db82d
* update from dtk-template and start work towards using clangd * include <a> -> "a" * Update build.yml * remove/add non-trivial class in union warning
75 lines
2.2 KiB
C
75 lines
2.2 KiB
C
#ifndef RVL_SDK_DSP_HARDWARE_H
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#define RVL_SDK_DSP_HARDWARE_H
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#include "common.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* DSP Hardware Registers
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* https://www.gc-forever.com/yagcd/chap5.html#sec5.6
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*/
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volatile u16 DSP_HW_REGS[] : 0xCC005000;
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/**
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* Hardware register indexes
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*/
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typedef enum {
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DSP_DSPMBOX_H, //!< 0xCC005000
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DSP_DSPMBOX_L, //!< 0xCC005002
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DSP_CPUMBOX_H, //!< 0xCC005004
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DSP_CPUMBOX_L, //!< 0xCC005006
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DSP_REG_0x8, //!< 0xCC005008
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DSP_CSR, //!< 0xCC00500A
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DSP_REG_0xC, //!< 0xCC00500C
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DSP_REG_0xE, //!< 0xCC00500E
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DSP_REG_0x10, //!< 0xCC005010
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DSP_AR_SIZE, //!< 0xCC005012
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DSP_REG_0x14, //!< 0xCC005014
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DSP_AR_MODE, //!< 0xCC005016
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DSP_REG_0x18, //!< 0xCC005018
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DSP_AR_REFRESH, //!< 0xCC00501A
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DSP_REG_0x1C, //!< 0xCC00501C
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DSP_REG_0x1E, //!< 0xCC00501E
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DSP_AR_DMA_MMADDR_H, //!< 0xCC005020
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DSP_AR_DMA_MMADDR_L, //!< 0xCC005022
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DSP_AR_DMA_ARADDR_H, //!< 0xCC005024
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DSP_AR_DMA_ARADDR_L, //!< 0xCC005026
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DSP_AR_DMA_CNT_H, //!< 0xCC005028
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DSP_AR_DMA_CNT_L, //!< 0xCC00502A
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DSP_REG_0x2C, //!< 0xCC00502C
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DSP_REG_0x2E, //!< 0xCC00502E
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DSP_AI_DMA_START_H, //!< 0xCC005030
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DSP_AI_DMA_START_L, //!< 0xCC005032
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DSP_REG_0x34, //!< 0xCC005034
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DSP_AI_DMA_CSR, //!< 0xCC005036
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DSP_REG_0x38, //!< 0xCC005038
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DSP_AI_DMA_BYTES_LEFT //!< 0xCC00503A
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} DSPHwReg;
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// DSPMBOX_H - DSP Mailbox High (to DSP)
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#define DSP_DSPMBOX_H_STATUS (1 << 15)
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// CPUMBOX_H - CPU Mailbox High (from DSP)
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#define DSP_CPUMBOX_H_STATUS (1 << 15)
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// CSR - Control Status Register
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#define DSP_CSR_RES (1 << 11)
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#define DSP_CSR_DMAINT (1 << 9)
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#define DSP_CSR_DSPINTMSK (1 << 8)
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#define DSP_CSR_DSPINT (1 << 7)
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#define DSP_CSR_ARINTMSK (1 << 6)
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#define DSP_CSR_ARINT (1 << 5)
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#define DSP_CSR_AIDINTMSK (1 << 4)
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#define DSP_CSR_AIDINT (1 << 3)
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#define DSP_CSR_HALT (1 << 2)
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#define DSP_CSR_PIINT (1 << 1)
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// AI_DMA_CSR - AI DMA Control Status Register
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#define DSP_AI_DMA_CSR_PLAY (1 << 15)
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#ifdef __cplusplus
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}
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#endif
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#endif
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