mirror of
https://github.com/zeldaret/ss
synced 2026-06-01 09:47:32 -04:00
Elijah Thomas
26af4db82d
* update from dtk-template and start work towards using clangd * include <a> -> "a" * Update build.yml * remove/add non-trivial class in union warning
104 lines
2.9 KiB
C
104 lines
2.9 KiB
C
#ifndef RVL_SDK_VI_HARDWARE_H
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#define RVL_SDK_VI_HARDWARE_H
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#include "common.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* VI Hardware Registers - arr size for typing
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* https://www.gc-forever.com/yagcd/chap5.html#sec5.3
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*/
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volatile u16 VI_HW_REGS[63] AT_ADDRESS(0xCC002000);
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/**
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* Hardware register indexes
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*/
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typedef enum {
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VI_REG_VTR, //!< 0xCC002000
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VI_REG_DCR, //!< 0xCC002002
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VI_REG_HTR0_H, //!< 0xCC002004
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VI_REG_HTR0_L, //!< 0xCC002006
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VI_REG_HTR1_H, //!< 0xCC002008
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VI_REG_HTR1_L, //!< 0xCC00200A
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VI_REG_VTO_H, //!< 0xCC00200C
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VI_REG_VTO_L, //!< 0xCC00200E
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VI_REG_VTE_H, //!< 0xCC002010
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VI_REG_VTE_L, //!< 0xCC002012
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VI_REG_BBEI_H, //!< 0xCC002014
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VI_REG_BBEI_L, //!< 0xCC002016
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VI_REG_BBOI_H, //!< 0xCC002018
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VI_REG_BBOI_L, //!< 0xCC00201A
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VI_REG_TFBL_H, //!< 0xCC00201C
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VI_REG_TFBL_L, //!< 0xCC00201E
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VI_REG_TFBR_H, //!< 0xCC002020
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VI_REG_TFBR_L, //!< 0xCC002022
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VI_REG_BFBL_H, //!< 0xCC002024
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VI_REG_BFBL_L, //!< 0xCC002026
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VI_REG_BFBR_H, //!< 0xCC002028
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VI_REG_BFBR_L, //!< 0xCC00202A
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VI_REG_DPV, //!< 0xCC00202C
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VI_REG_DPH, //!< 0xCC00202E
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VI_REG_DI0_H, //!< 0xCC002030
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VI_REG_DI0_L, //!< 0xCC002032
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VI_REG_DI1_H, //!< 0xCC002034
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VI_REG_DI1_L, //!< 0xCC002036
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VI_REG_DI2_H, //!< 0xCC002038
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VI_REG_DI2_L, //!< 0xCC00203A
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VI_REG_DI3_H, //!< 0xCC00203C
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VI_REG_DI3_L, //!< 0xCC00203E
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VI_REG_DL0_H, //!< 0xCC002040
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VI_REG_DL0_L, //!< 0xCC002042
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VI_REG_DL1_H, //!< 0xCC002044
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VI_REG_DL1_L, //!< 0xCC002046
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VI_REG_HSW, //!< 0xCC002048
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VI_REG_HSR, //!< 0xCC00204A
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VI_REG_FCT0_H, //!< 0xCC00204C
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VI_REG_FCT0_L, //!< 0xCC00204E
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VI_REG_FCT1_H, //!< 0xCC002050
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VI_REG_FCT1_L, //!< 0xCC002052
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VI_REG_FCT2_H, //!< 0xCC002054
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VI_REG_FCT2_L, //!< 0xCC002056
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VI_REG_FCT3_H, //!< 0xCC002058
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VI_REG_FCT3_L, //!< 0xCC00205A
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VI_REG_FCT4_H, //!< 0xCC00205C
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VI_REG_FCT4_L, //!< 0xCC00205E
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VI_REG_FCT5_H, //!< 0xCC002060
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VI_REG_FCT5_L, //!< 0xCC002062
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VI_REG_FCT6_H, //!< 0xCC002064
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VI_REG_FCT6_L, //!< 0xCC002066
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VI_REG_0x68, //!< 0xCC002068
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VI_REG_0x6A, //!< 0xCC00206A
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VI_REG_VICLK, //!< 0xCC00206C
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VI_REG_VISEL, //!< 0xCC00206E
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VI_REG_0x70, //!< 0xCC002070
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VI_REG_HBE, //!< 0xCC002072
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VI_REG_HBS, //!< 0xCC002074
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VI_REG_0x76, //!< 0xCC002076
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VI_REG_0x78, //!< 0xCC002078
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VI_REG_0x7A, //!< 0xCC00207A
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VI_REG_0x7C, //!< 0xCC00207C
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} VIHwReg;
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// DCR - Display Configuration Register
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#define VI_DCR_ENB (1 << 0)
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#define VI_DCR_RST (1 << 1)
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#define VI_DCR_NIN (1 << 2)
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#define VI_DCR_FMT_MASK (0b0000001100000000)
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// DI{n} - Display Interrupt Register N
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#define VI_DI_INT (1 << 15)
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#define VI_DI_ENB (1 << 12)
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// VICLK - VI Clock Select Register
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#define VI_VICLK_27MHZ 0
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#define VI_VICLK_54MHZ 1
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// HBE - Border HBE
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#define VI_HBE_BRDR_EN (1 << 15)
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#ifdef __cplusplus
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}
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#endif
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#endif
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