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Update dsd to v0.12.0; dsprot OK (#135)

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* `Actor::mType` field

* Remove fake symbol `data_027e0254`

* `dsd format`

* eur: Enable dsprot decomp

* jp: Enable dsprot decomp

* dsprot OK

* `dsd format`

* Use new `weak` attribute

* Add relocations for exception table link-time constants

* Add exception table symbols

* Bump dsd to v0.12.0

* `#define FALSE 1` ???
Why did I make it 1?

* Truncate `data_ov001_020c27a8`
That data belongs to dsprot
This commit is contained in:
Aetias
2026-08-15 01:07:14 +02:00
committed by GitHub
parent ce24ddfc4e
commit 521100caed
104 changed files with 4547 additions and 2014 deletions
Download Patch File Download Diff File Expand all files Collapse all files
libs/nitro/include/nitro.h
-1
View File
@@ -2,7 +2,6 @@
#include <stddef.h>
#include "nitro/card.h"
#include "nitro/dc.h"
#include "nitro/fs.h"
#include "nitro/fx.h"
#include "nitro/g2.h"
libs/nitro/include/nitro/card.h
+16
View File
@@ -29,6 +29,19 @@ extern "C" {
#define CARD_RESULT_NO_RESPONSE
#define CARD_RESULT_ERROR
#define CARD_ROM_PAGE_SIZE 0x200
#define CARD_DATA_READY 0x800000
#define CARD_CTL_CMD_MASK 0x7000000
#define CARD_CTL_CMD_PAGE 0x1000000
#define CARD_CTL_READ 0x20000000
#define CARD_CTL_START 0x80000000
#define CARD_CMD_ENCRYPTED_READ 0xb7
#define CARDMST_ENABLE 0x80
typedef u32 CARDBackupType;
typedef u32 CARDResult;
@@ -45,6 +58,9 @@ CARDResult CARD_GetResultCode(void);
BOOL CARD_func_0033();
void CARD_func_0034();
void CARD_func_0010(u32);
void CARD_func_0011(u32);
inline BOOL CARD_ReadEepromAsync(u32 offset, void *buf, u32 size, void *param4, void *param5) {
return CARD_ReadWriteBackupAsync(offset, buf, size, param4, param5, 1, 6, 1, 0);
}
libs/nitro/include/nitro/os.h
+18
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@@ -7,8 +7,10 @@ extern "C" {
#include <stdarg.h>
#include "nitro/os/cache.h"
#include "nitro/os/context.h"
#include "nitro/os/mutex.h"
#include "nitro/os/owner.h"
#include "nitro/os/thread.h"
#include "nitro/reg.h"
@@ -30,6 +32,12 @@ extern "C" {
#define OS_THREAD_LAUNCHER_PRIORITY 0x10
#define OS_EXMEM_CNT_NDS_SLOT_ACCESS_SHIFT 11
#define OS_EXMEM_CNT_NDS_SLOT_ACCESS (1 << OS_EXMEM_CNT_NDS_SLOT_ACCESS_SHIFT)
#define OS_CPU_ARM9 0
#define OS_CPU_ARM7 1
typedef struct OSLinkedList {
/* 00 */ void *head;
/* 04 */ void *tail;
@@ -166,6 +174,9 @@ s32 OS_func_0171(u32, u32, u32);
s32 OS_func_0174(void);
BOOL OS_func_0065(void);
void OS_func_0176(u8 *);
void OS_func_0178(u32);
inline void OS_SetIrqCheckFlag(void) {
REG_IRQ |= 1;
}
@@ -228,9 +239,16 @@ inline BOOL OS_IsRunOnTwl(void) {
return false;
#else
// Probably checks some reg here
#define REG_A9ROM_OFFSET 0x4000
#define REG_SCFG_A9ROM_SEC_MASK 1
#endif
}
inline void OS_SetNdsSlotAccess(u32 processor) {
REG_EXMEM_CNT = (REG_EXMEM_CNT & ~OS_EXMEM_CNT_NDS_SLOT_ACCESS) | (processor << OS_EXMEM_CNT_NDS_SLOT_ACCESS_SHIFT);
}
#ifdef __cplusplus
} // extern "C"
#endif
libs/nitro/include/nitro/dc.h → libs/nitro/include/nitro/os/cache.h
+8 -5
View File
@@ -1,12 +1,14 @@
#ifndef _NITRO_DC_H
#define _NITRO_DC_H
#include "nitro/types.h"
#ifndef _NITRO_OS_CACHE_H
#define _NITRO_OS_CACHE_H
#ifdef __cplusplus
extern "C" {
#endif
#include "nitro/types.h"
#define OS_CACHE_LINE_SIZE 0x20
void DC_StoreAll(void);
void DC_StoreRange(void *ptr, u32 size);
@@ -15,9 +17,10 @@ void DC_FlushRange(void *ptr, u32 size);
void DC_InvalidateRange(void *ptr, u32 size);
void DC_func_0004(void *, int);
void DC_func_0002();
void IC_InvalidateRange(void *ptr, u32 size);
#ifdef __cplusplus
} // extern "C"
#endif
libs/nitro/include/nitro/os/context.h
+1 -1
View File
@@ -1,7 +1,7 @@
#ifndef _NITRO_CONTEXT_H
#define _NITRO_CONTEXT_H
#include <types.h>
#include "nitro/types.h"
typedef struct OSContext {
/* 0x00 */ u32 cpsr;
libs/nitro/include/nitro/os/mutex.h
+2 -2
View File
@@ -1,8 +1,8 @@
#ifndef NITROSDK_OS_MUTEX_H
#define NITROSDK_OS_MUTEX_H
#include <nitro/os/thread.h>
#include <types.h>
#include "nitro/os/thread.h"
#include "nitro/types.h"
typedef struct OSMutex {
/* 0x00 */ OSThreadQueue queue;
libs/nitro/include/nitro/os/owner.h
+28
View File
@@ -0,0 +1,28 @@
#ifndef _NITRO_OS_OWNER_H
#define _NITRO_OS_OWNER_H
#ifdef __cplusplus
extern "C" {
#endif
#include "nitro/types.h"
typedef struct OSOwnerInfo {
/* 00 */ u8 unk_00[0x2];
struct {
/* 02 */ u8 month;
/* 03 */ u8 day;
} birthday;
/* 04 */ u8 unk_04[0x16];
/* 1a */ u16 nickNameLength;
/* 1c */ u8 unk_1c[0x38];
/* 54 */
} OSOwnerInfo;
void OS_func_0177(OSOwnerInfo *info);
#ifdef __cplusplus
} // extern "C"
#endif
#endif
libs/nitro/include/nitro/reg.h
+64 -47
View File
@@ -7,32 +7,37 @@ extern "C" {
#include "nitro/types.h"
#define REG_POWER_CNT (*(vu16 *) 0x04000304)
#define REG_IME (*(vu16 *) 0x04000208)
#define REG_BASE 0x4000000
#define REG_DISPSTAT (*(vu16 *) 0x4000004)
#define REG_VCOUNT (*(vu16 *) 0x04000006)
#define REG_DISP3DCNT (*(vu16 *) 0x04000060)
#define REG_DISPCAPCNT (*(vu32 *) 0x04000064)
#define REG_GFX_STATUS (*(vu32 *) 0x04000600)
#define REG_POWER_CNT (*(vu16 *) (REG_BASE | 0x304))
#define REG_IME (*(vu16 *) (REG_BASE | 0x208))
#define REG_DMA ((OSDma *) 0x040000B0)
#define REG_DMA0SAD (*(vu32 *) 0x040000B0)
#define REG_DMA0DAD (*(vu32 *) 0x040000B4)
#define REG_DMA0CNT (*(vu32 *) 0x040000B8)
#define REG_DISPSTAT (*(vu16 *) (REG_BASE | 0x4))
#define REG_VCOUNT (*(vu16 *) (REG_BASE | 0x6))
#define REG_DISP3DCNT (*(vu16 *) (REG_BASE | 0x60))
#define REG_DISPCAPCNT (*(vu32 *) (REG_BASE | 0x64))
#define REG_GFX_STATUS (*(vu32 *) (REG_BASE | 0x600))
#define REG_VRAM_CNT_ABCD (*(vu32 *) 0x04000240)
#define REG_VRAM_CNT_A (*(vu8 *) 0x04000240)
#define REG_VRAM_CNT_B (*(vu8 *) 0x04000241)
#define REG_VRAM_CNT_C (*(vu8 *) 0x04000242)
#define REG_VRAM_CNT_D (*(vu8 *) 0x04000243)
#define REG_VRAM_CNT_E (*(vu8 *) 0x04000244)
#define REG_VRAM_CNT_F (*(vu8 *) 0x04000245)
#define REG_VRAM_CNT_G (*(vu8 *) 0x04000246)
#define REG_WRAM_CNT (*(vu8 *) 0x04000247)
#define REG_VRAM_CNT_HI (*(vu16 *) 0x04000248)
#define REG_VRAM_CNT_H (*(vu8 *) 0x04000248)
#define REG_VRAM_CNT_I (*(vu8 *) 0x04000249)
#define REG_DMA ((OSDma *) (REG_BASE | 0xB0))
#define REG_DMA0SAD (*(vu32 *) (REG_BASE | 0xB0))
#define REG_DMA0DAD (*(vu32 *) (REG_BASE | 0xB4))
#define REG_DMA0CNT (*(vu32 *) (REG_BASE | 0xB8))
#define REG_VRAM_CNT_ABCD (*(vu32 *) (REG_BASE | 0x240))
#define REG_VRAM_CNT_A (*(vu8 *) (REG_BASE | 0x240))
#define REG_VRAM_CNT_B (*(vu8 *) (REG_BASE | 0x241))
#define REG_VRAM_CNT_C (*(vu8 *) (REG_BASE | 0x242))
#define REG_VRAM_CNT_D (*(vu8 *) (REG_BASE | 0x243))
#define REG_VRAM_CNT_E (*(vu8 *) (REG_BASE | 0x244))
#define REG_VRAM_CNT_F (*(vu8 *) (REG_BASE | 0x245))
#define REG_VRAM_CNT_G (*(vu8 *) (REG_BASE | 0x246))
#define REG_WRAM_CNT (*(vu8 *) (REG_BASE | 0x247))
#define REG_VRAM_CNT_HI (*(vu16 *) (REG_BASE | 0x248))
#define REG_VRAM_CNT_H (*(vu8 *) (REG_BASE | 0x248))
#define REG_VRAM_CNT_I (*(vu8 *) (REG_BASE | 0x249))
#define REG_EXMEM_CNT_OFFSET 0x204
#define REG_EXMEM_CNT (*(vu16 *) (REG_BASE | REG_EXMEM_CNT_OFFSET))
#if NITRO_VERSION >= 0x05057533
#define _BIOS_REG_BASE 0x02FFF000
@@ -41,7 +46,16 @@ extern "C" {
#endif
#define REG_PAD (*(u16 *) (_BIOS_REG_BASE | 0xFA8))
#define REG_KEYINPUT (*(u16 *) 0x04000130)
#define REG_KEYINPUT (*(u16 *) (REG_BASE | 0x130))
#define REG_CARD_AUX_SPI_CNT_OFFSET 0x1A0
#define REG_CARD_AUX_SPI_CNT (*(vu16 *) (REG_BASE | 0x1A0))
#define REG_CARD_CNT_OFFSET 0x1A4
#define REG_CARD_CNT (*(vu32 *) (REG_BASE | REG_CARD_CNT_OFFSET))
#define REG_CARD_CMD_OFFSET 0x1A8
#define REG_CARD_CMD (*(vu8 *) (REG_BASE | REG_CARD_CMD_OFFSET))
#define REG_CARD_DATA_OFFSET 0x100010
#define REG_CARD_DATA (*(vu32 *) (REG_BASE | REG_CARD_DATA_OFFSET))
#define REG_FRAME_COUNTER (*(u32 *) (_BIOS_REG_BASE | 0xC3C))
#define REG_027FFC40 (*(u16 *) (_BIOS_REG_BASE | 0xC40))
@@ -56,33 +70,33 @@ extern "C" {
#define REG_027FFF9C (*(u32 *) (_BIOS_REG_BASE | 0xF9C))
#define REG_027FFFA0 (*(u32 *) (_BIOS_REG_BASE | 0xFA0))
#define REG_GFX_FIFO (*(vu32 *) 0x04000400)
#define REG_GFX_FIFO_MATRIX_MODE (*(vu32 *) 0x04000440)
#define REG_GFX_FIFO_MATRIX_PUSH (*(vu32 *) 0x04000444)
#define REG_GFX_FIFO_MATRIX_POP (*(vu32 *) 0x04000448)
#define REG_GFX_FIFO_MATRIX_STORE (*(vu32 *) 0x0400044C)
#define REG_GFX_FIFO_MATRIX_RESTORE (*(vu32 *) 0x04000450)
#define REG_GFX_FIFO_MATRIX_IDENTITY (*(vu32 *) 0x04000454)
#define REG_GFX_FIFO_MATRIX_TRANSLATE (*(vu32 *) 0x04000470)
#define REG_GFX_FIFO_VERTEX_COLOR (*(vu32 *) 0x04000480)
#define REG_GFX_FIFO_VERTEX_TEXCOORD (*(vu32 *) 0x04000488)
#define REG_GFX_FIFO_VERTEX_16 (*(vu32 *) 0x0400048C)
#define REG_GFX_FIFO_VERTEX_XZ (*(vu32 *) 0x04000498)
#define REG_GFX_FIFO_POLYGON_ATTR (*(vu32 *) 0x040004A4)
#define REG_GFX_FIFO_TEXTURE_PARAM (*(vu32 *) 0x040004A8)
#define REG_GFX_FIFO_TEXTURE_PALETTE (*(vu32 *) 0x040004AC)
#define REG_GFX_FIFO_DIFFUSE_AMBIENT_REFLECT (*(vu32 *) 0x040004C0)
#define REG_GFX_FIFO_POLYGONS_BEGIN (*(vu32 *) 0x04000500)
#define REG_GFX_FIFO_POLYGONS_END (*(vu32 *) 0x04000504)
#define REG_GFX_FIFO_SWAP_BUFFERS (*(vu32 *) 0x04000540)
#define REG_GFX_FIFO_VIEWPORT (*(vu32 *) 0x04000580)
#define REG_GFX_FIFO (*(vu32 *) (REG_BASE | 0x400))
#define REG_GFX_FIFO_MATRIX_MODE (*(vu32 *) (REG_BASE | 0x440))
#define REG_GFX_FIFO_MATRIX_PUSH (*(vu32 *) (REG_BASE | 0x444))
#define REG_GFX_FIFO_MATRIX_POP (*(vu32 *) (REG_BASE | 0x448))
#define REG_GFX_FIFO_MATRIX_STORE (*(vu32 *) (REG_BASE | 0x44C))
#define REG_GFX_FIFO_MATRIX_RESTORE (*(vu32 *) (REG_BASE | 0x450))
#define REG_GFX_FIFO_MATRIX_IDENTITY (*(vu32 *) (REG_BASE | 0x454))
#define REG_GFX_FIFO_MATRIX_TRANSLATE (*(vu32 *) (REG_BASE | 0x470))
#define REG_GFX_FIFO_VERTEX_COLOR (*(vu32 *) (REG_BASE | 0x480))
#define REG_GFX_FIFO_VERTEX_TEXCOORD (*(vu32 *) (REG_BASE | 0x488))
#define REG_GFX_FIFO_VERTEX_16 (*(vu32 *) (REG_BASE | 0x48C))
#define REG_GFX_FIFO_VERTEX_XZ (*(vu32 *) (REG_BASE | 0x498))
#define REG_GFX_FIFO_POLYGON_ATTR (*(vu32 *) (REG_BASE | 0x4A4))
#define REG_GFX_FIFO_TEXTURE_PARAM (*(vu32 *) (REG_BASE | 0x4A8))
#define REG_GFX_FIFO_TEXTURE_PALETTE (*(vu32 *) (REG_BASE | 0x4AC))
#define REG_GFX_FIFO_DIFFUSE_AMBIENT_REFLECT (*(vu32 *) (REG_BASE | 0x4C0))
#define REG_GFX_FIFO_POLYGONS_BEGIN (*(vu32 *) (REG_BASE | 0x500))
#define REG_GFX_FIFO_POLYGONS_END (*(vu32 *) (REG_BASE | 0x504))
#define REG_GFX_FIFO_SWAP_BUFFERS (*(vu32 *) (REG_BASE | 0x540))
#define REG_GFX_FIFO_VIEWPORT (*(vu32 *) (REG_BASE | 0x580))
extern u32 __DTCM_LO;
#define DTCM_LO ((u8 *) &__DTCM_LO)
#define REG_IRQ (*(u32 *) (DTCM_LO + 0x3FF8))
#define _MAIN_REG_BASE 0x04000000
#define _SUB_REG_BASE 0x04001000
#define _MAIN_REG_BASE REG_BASE
#define _SUB_REG_BASE (REG_BASE | 0x1000)
#define _REG_DISPCNT(base) (*(u32 *) ((base) | 0x0))
#define _REG_BG0CNT(base) (*(vu16 *) ((base) | 0x8))
@@ -171,7 +185,10 @@ extern u32 __DTCM_LO;
#define REG_BLDALPHA_SUB _REG_BLDALPHA(_SUB_REG_BASE)
#define REG_MASTER_BRIGHT_SUB _REG_MASTER_BRIGHT(_SUB_REG_BASE)
#define REG_04FFF200 (*(vu32 *) 0x04FFF200)
#define REG_A9ROM_OFFSET 0x4000
#define REG_A9ROM (*(vu16 *) (REG_BASE | REG_A9ROM_OFFSET))
#define REG_04FFF200 (*(vu32 *) (REG_BASE | 0xFFF200))
#ifdef __cplusplus
} // extern "C"
libs/nitro/include/nitro/types.h
+6
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@@ -9,11 +9,13 @@ extern "C" {
#endif
typedef unsigned long long u64;
typedef unsigned long ulong;
typedef unsigned int u32;
typedef unsigned short u16;
typedef unsigned char u8;
typedef long long s64;
typedef long long slong;
typedef int s32;
typedef short s16;
typedef char s8;
@@ -22,11 +24,13 @@ typedef float f32;
typedef double f64;
typedef volatile u64 vu64;
typedef volatile u64 vulong;
typedef volatile u32 vu32;
typedef volatile u16 vu16;
typedef volatile u8 vu8;
typedef volatile s64 vs64;
typedef volatile s64 vslong;
typedef volatile s32 vs32;
typedef volatile s16 vs16;
typedef volatile s8 vs8;
@@ -35,6 +39,8 @@ typedef volatile f32 vf32;
typedef volatile f64 vf64;
typedef s32 BOOL;
#define TRUE 1
#define FALSE 0
#define ATTRIBUTE_ALIGN(x) __attribute__((aligned(x)))