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J3DSkinDeform work (#2896)

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* Match four inline asm functions with manual regalloc

* J3DSkinDeform::changeFastSkinDL: Clean up var names, slightly improve match

* Syntax

* More var names
This commit is contained in:
LagoLunatic
2025-11-30 16:39:56 -05:00
committed by GitHub
parent 20e9957356
commit 434415337d
3 changed files with 136 additions and 199 deletions
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include/JSystem/J3DGraphBase/J3DTransform.h
+88 -147
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@@ -111,177 +111,118 @@ inline void J3DPSMtx33CopyFrom34(register MtxP src, register Mtx3P dst) {
#endif
}
// regalloc issues
inline void J3DPSMulMtxVec(register MtxP mtx, register Vec* vec, register Vec* dst) {
register f32 fr12;
register f32 fr11;
register f32 fr10;
register f32 fr9;
register f32 fr8;
register f32 fr6;
register f32 fra6;
register f32 fr5;
register f32 fra5;
register f32 fra4;
register f32 fr4;
register f32 fr3;
register f32 fr2;
register f32 fra2;
register f32 fr01;
register f32 fr00;
#ifdef __MWERKS__
asm {
psq_l fr00, 0(vec), 0, 0
psq_l fr2, 0(mtx), 0, 0
psq_l fr01, 8(vec), 1, 0
ps_mul fr4, fr2, fr00
psq_l fr3, 8(mtx), 0, 0
ps_madd fr5, fr3, fr01, fr4
psq_l fr8, 16(mtx), 0, 0
ps_sum0 fr6, fr5, fr6, fr5
psq_l fr9, 24(mtx), 0, 0
ps_mul fr10, fr8, fr00
psq_st fr6, 0(dst), 1, 0
ps_madd fr11, fr9, fr01, fr10
psq_l fra2, 32(mtx), 0, 0
ps_sum0 fr12, fr11, fr12, fr11
psq_l fr3, 40(mtx), 0, 0
ps_mul fra4, fra2, fr00
psq_st fr12, 4(dst), 1, 0
ps_madd fra5, fr3, fr01, fra4
ps_sum0 fra6, fra5, fra6, fra5
psq_st fra6, 8(dst), 1, 0
psq_l f0, 0(vec), 0, 0
psq_l f2, 0(mtx), 0, 0
psq_l f1, 8(vec), 1, 0
ps_mul f4, f2, f0
psq_l f3, 8(mtx), 0, 0
ps_madd f5, f3, f1, f4
psq_l f8, 16(mtx), 0, 0
ps_sum0 f6, f5, f6, f5
psq_l f9, 24(mtx), 0, 0
ps_mul f10, f8, f0
psq_st f6, 0(dst), 1, 0
ps_madd f11, f9, f1, f10
psq_l f2, 32(mtx), 0, 0
ps_sum0 f12, f11, f12, f11
psq_l f3, 40(mtx), 0, 0
ps_mul f4, f2, f0
psq_st f12, 4(dst), 1, 0
ps_madd f5, f3, f1, f4
ps_sum0 f6, f5, f6, f5
psq_st f6, 8(dst), 1, 0
}
#endif
}
// regalloc issues
inline void J3DPSMulMtxVec(register MtxP mtx, register S16Vec* vec, register S16Vec* dst) {
register f32 fr12;
register f32 fr11;
register f32 fr10;
register f32 fr9;
register f32 fr8;
register f32 fr6;
register f32 fra6;
register f32 fr5;
register f32 fra5;
register f32 fra4;
register f32 fr4;
register f32 fr3;
register f32 fr2;
register f32 fra2;
register f32 fr01;
register f32 fr00;
#ifdef __MWERKS__
asm {
psq_l fr00, 0(vec), 0, 7
psq_l fr2, 0(mtx), 0, 0
psq_l fr01, 4(vec), 1, 7
ps_mul fr4, fr2, fr00
psq_l fr3, 8(mtx), 0, 0
ps_madd fr5, fr3, fr01, fr4
psq_l fr8, 16(mtx), 0, 0
ps_sum0 fr6, fr5, fr6, fr5
psq_l fr9, 24(mtx), 0, 0
ps_mul fr10, fr8, fr00
psq_st fr6, 0(dst), 1, 7
ps_madd fr11, fr9, fr01, fr10
psq_l fra2, 32(mtx), 0, 0
ps_sum0 fr12, fr11, fr12, fr11
psq_l fr3, 40(mtx), 0, 0
ps_mul fra4, fra2, fr00
psq_st fr12, 2(dst), 1, 7
ps_madd fra5, fr3, fr01, fra4
ps_sum0 fra6, fra5, fra6, fra5
psq_st fra6, 4(dst), 1, 7
psq_l f0, 0(vec), 0, 7
psq_l f2, 0(mtx), 0, 0
psq_l f1, 4(vec), 1, 7
ps_mul f4, f2, f0
psq_l f3, 8(mtx), 0, 0
ps_madd f5, f3, f1, f4
psq_l f8, 16(mtx), 0, 0
ps_sum0 f6, f5, f6, f5
psq_l f9, 24(mtx), 0, 0
ps_mul f10, f8, f0
psq_st f6, 0(dst), 1, 7
ps_madd f11, f9, f1, f10
psq_l f2, 32(mtx), 0, 0
ps_sum0 f12, f11, f12, f11
psq_l f3, 40(mtx), 0, 0
ps_mul f4, f2, f0
psq_st f12, 2(dst), 1, 7
ps_madd f5, f3, f1, f4
ps_sum0 f6, f5, f6, f5
psq_st f6, 4(dst), 1, 7
}
#endif
}
// regalloc issues
inline void J3DPSMulMtxVec(register Mtx3P mtx, register Vec* vec, register Vec* dst) {
register f32* punit;
register f32 unit;
register f32 fr12;
register f32 fr11;
register f32 fr10;
register f32 fr9;
register f32 fr8;
register f32 fr6;
register f32 fr5;
register f32 fr4;
register f32 fr3;
register f32 fr2;
register f32 fr01;
register f32 fr00;
#ifdef __MWERKS__
asm {
lis punit, PSMulUnit01@ha
psq_l fr00, 0(vec), 0, 0
addi punit, punit, PSMulUnit01@l
psq_l fr2, 0(mtx), 0, 0
psq_l unit, 0(punit), 0, 0
psq_l fr01, 8(vec), 1, 0
ps_add fr01, unit, fr01
psq_l fr3, 8(mtx), 1, 0
ps_mul fr4, fr2, fr00
psq_l fr8, 12(mtx), 0, 0
ps_madd fr5, fr3, fr01, fr4
ps_sum0 fr6, fr5, fr6, fr5
psq_l fr9, 20(mtx), 1, 0
ps_mul fr10, fr8, fr00
psq_st fr6, 0(dst), 1, 0
ps_madd fr11, fr9, fr01, fr10
psq_l fr2, 24(mtx), 0, 0
ps_sum0 fr12, fr11, fr12, fr11
psq_l fr3, 32(mtx), 1, 0
ps_mul fr4, fr2, fr00
psq_st fr12, 4(dst), 1, 0
ps_madd fr5, fr3, fr01, fr4
ps_sum0 fr6, fr5, fr6, fr5
psq_st fr6, 8(dst), 1, 0
lis r6, PSMulUnit01@ha
psq_l f0, 0(vec), 0, 0
addi r6, r6, PSMulUnit01@l
psq_l f2, 0(mtx), 0, 0
psq_l f13, 0(r6), 0, 0
psq_l f1, 8(vec), 1, 0
ps_add f1, f13, f1
psq_l f3, 8(mtx), 1, 0
ps_mul f4, f2, f0
psq_l f8, 12(mtx), 0, 0
ps_madd f5, f3, f1, f4
ps_sum0 f6, f5, f6, f5
psq_l f9, 20(mtx), 1, 0
ps_mul f10, f8, f0
psq_st f6, 0(dst), 1, 0
ps_madd f11, f9, f1, f10
psq_l f2, 24(mtx), 0, 0
ps_sum0 f12, f11, f12, f11
psq_l f3, 32(mtx), 1, 0
ps_mul f4, f2, f0
psq_st f12, 4(dst), 1, 0
ps_madd f5, f3, f1, f4
ps_sum0 f6, f5, f6, f5
psq_st f6, 8(dst), 1, 0
}
#endif
}
// regalloc issues
inline void J3DPSMulMtxVec(register Mtx3P mtx, register S16Vec* vec, register S16Vec* dst) {
register f32* punit;
register f32 unit;
register f32 fr6;
register f32 fr5;
register f32 fr4;
register f32 fr3;
register f32 fr2;
register f32 fr01;
register f32 fr00;
#ifdef __MWERKS__
asm {
lis punit, PSMulUnit01@ha
psq_l fr00, 0(vec), 0, 7
addi punit, punit, PSMulUnit01@l
psq_l fr2, 0(mtx), 0, 0
psq_l unit, 0(punit), 0, 0
psq_l fr01, 4(vec), 1, 7
ps_add fr01, unit, fr01
psq_l fr3, 8(mtx), 1, 0
ps_mul fr4, fr2, fr00
psq_l fr2, 12(mtx), 0, 0
ps_madd fr5, fr3, fr01, fr4
ps_sum0 fr6, fr5, fr6, fr5
psq_l fr3, 20(mtx), 1, 0
ps_mul fr4, fr2, fr00
psq_st fr6, 0(dst), 1, 7
ps_madd fr5, fr3, fr01, fr4
psq_l fr2, 24(mtx), 0, 0
ps_sum0 fr6, fr5, fr6, fr5
psq_l fr3, 32(mtx), 1, 0
ps_mul fr4, fr2, fr00
psq_st fr6, 2(dst), 1, 7
ps_madd fr5, fr3, fr01, fr4
ps_sum0 fr6, fr5, fr6, fr5
psq_st fr6, 4(dst), 1, 7
lis r6, PSMulUnit01@ha
psq_l f0, 0(vec), 0, 7
addi r6, r6, PSMulUnit01@l
psq_l f2, 0(mtx), 0, 0
psq_l f13, 0(r6), 0, 0
psq_l f1, 4(vec), 1, 7
ps_add f1, f13, f1
psq_l f3, 8(mtx), 1, 0
ps_mul f4, f2, f0
psq_l f8, 12(mtx), 0, 0
ps_madd f5, f3, f1, f4
ps_sum0 f6, f5, f6, f5
psq_l f9, 20(mtx), 1, 0
ps_mul f10, f8, f0
psq_st f6, 0(dst), 1, 7
ps_madd f11, f9, f1, f10
psq_l f2, 24(mtx), 0, 0
ps_sum0 f12, f11, f12, f11
psq_l f3, 32(mtx), 1, 0
ps_mul f4, f2, f0
psq_st f12, 2(dst), 1, 7
ps_madd f5, f3, f1, f4
ps_sum0 f6, f5, f6, f5
psq_st f6, 4(dst), 1, 7
}
#endif
}