mirror of
https://github.com/zeldaret/tp
synced 2026-07-09 06:53:23 -04:00
J3DPacket, J3DShape OK (#366)
This commit is contained in:
hatal175
@@ -1,137 +0,0 @@
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lbl_80312BD4:
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/* 80312BD4 94 21 FF E0 */ stwu r1, -0x20(r1)
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/* 80312BD8 7C 08 02 A6 */ mflr r0
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/* 80312BDC 90 01 00 24 */ stw r0, 0x24(r1)
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/* 80312BE0 39 61 00 20 */ addi r11, r1, 0x20
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/* 80312BE4 48 04 F5 F5 */ bl _savegpr_28
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/* 80312BE8 7C 7D 1B 78 */ mr r29, r3
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/* 80312BEC 7C 9E 23 78 */ mr r30, r4
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/* 80312BF0 3B E0 00 00 */ li r31, 0
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/* 80312BF4 38 60 00 00 */ li r3, 0
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/* 80312BF8 3C 80 80 3D */ lis r4, sDifferedRegister@ha /* 0x803CD900@ha */
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/* 80312BFC 38 A4 D9 00 */ addi r5, r4, sDifferedRegister@l /* 0x803CD900@l */
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/* 80312C00 3C 80 80 3D */ lis r4, sSizeOfDiffered@ha /* 0x803CD920@ha */
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/* 80312C04 38 84 D9 20 */ addi r4, r4, sSizeOfDiffered@l /* 0x803CD920@l */
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/* 80312C08 38 00 00 08 */ li r0, 8
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/* 80312C0C 7C 09 03 A6 */ mtctr r0
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lbl_80312C10:
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/* 80312C10 7C 05 18 2E */ lwzx r0, r5, r3
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/* 80312C14 7F C0 00 39 */ and. r0, r30, r0
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/* 80312C18 41 82 00 0C */ beq lbl_80312C24
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/* 80312C1C 7C 04 18 2E */ lwzx r0, r4, r3
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/* 80312C20 7F FF 02 14 */ add r31, r31, r0
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lbl_80312C24:
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/* 80312C24 38 63 00 04 */ addi r3, r3, 4
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/* 80312C28 42 00 FF E8 */ bdnz lbl_80312C10
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/* 80312C2C 57 C0 E7 3E */ rlwinm r0, r30, 0x1c, 0x1c, 0x1f
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/* 80312C30 1C 00 00 48 */ mulli r0, r0, 0x48
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/* 80312C34 7F FF 02 14 */ add r31, r31, r0
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/* 80312C38 57 DC C7 3F */ rlwinm. r28, r30, 0x18, 0x1c, 0x1f
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/* 80312C3C 41 82 00 4C */ beq lbl_80312C88
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/* 80312C40 80 7D 00 28 */ lwz r3, 0x28(r29)
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/* 80312C44 80 63 00 04 */ lwz r3, 4(r3)
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/* 80312C48 80 63 00 28 */ lwz r3, 0x28(r3)
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/* 80312C4C 81 83 00 00 */ lwz r12, 0(r3)
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/* 80312C50 81 8C 00 40 */ lwz r12, 0x40(r12)
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/* 80312C54 7D 89 03 A6 */ mtctr r12
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/* 80312C58 4E 80 04 21 */ bctrl
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/* 80312C5C 7C 1C 18 40 */ cmplw r28, r3
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/* 80312C60 40 81 00 08 */ ble lbl_80312C68
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/* 80312C64 7F 83 E3 78 */ mr r3, r28
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lbl_80312C68:
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/* 80312C68 57 C0 04 E7 */ rlwinm. r0, r30, 0, 0x13, 0x13
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/* 80312C6C 41 82 00 14 */ beq lbl_80312C80
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/* 80312C70 1C 03 00 3D */ mulli r0, r3, 0x3d
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/* 80312C74 7F E0 FA 14 */ add r31, r0, r31
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/* 80312C78 3B FF 00 0A */ addi r31, r31, 0xa
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/* 80312C7C 48 00 00 0C */ b lbl_80312C88
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lbl_80312C80:
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/* 80312C80 1C 03 00 35 */ mulli r0, r3, 0x35
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/* 80312C84 7F FF 02 14 */ add r31, r31, r0
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lbl_80312C88:
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/* 80312C88 57 DC 87 3F */ rlwinm. r28, r30, 0x10, 0x1c, 0x1f
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/* 80312C8C 41 82 00 90 */ beq lbl_80312D1C
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/* 80312C90 80 7D 00 28 */ lwz r3, 0x28(r29)
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/* 80312C94 80 63 00 04 */ lwz r3, 4(r3)
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/* 80312C98 80 63 00 2C */ lwz r3, 0x2c(r3)
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/* 80312C9C 81 83 00 00 */ lwz r12, 0(r3)
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/* 80312CA0 81 8C 00 98 */ lwz r12, 0x98(r12)
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/* 80312CA4 7D 89 03 A6 */ mtctr r12
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/* 80312CA8 4E 80 04 21 */ bctrl
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/* 80312CAC 54 60 06 3E */ clrlwi r0, r3, 0x18
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/* 80312CB0 28 00 00 08 */ cmplwi r0, 8
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/* 80312CB4 40 81 00 0C */ ble lbl_80312CC0
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/* 80312CB8 38 60 00 08 */ li r3, 8
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/* 80312CBC 48 00 00 20 */ b lbl_80312CDC
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lbl_80312CC0:
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/* 80312CC0 80 7D 00 28 */ lwz r3, 0x28(r29)
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/* 80312CC4 80 63 00 04 */ lwz r3, 4(r3)
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/* 80312CC8 80 63 00 2C */ lwz r3, 0x2c(r3)
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/* 80312CCC 81 83 00 00 */ lwz r12, 0(r3)
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/* 80312CD0 81 8C 00 98 */ lwz r12, 0x98(r12)
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/* 80312CD4 7D 89 03 A6 */ mtctr r12
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/* 80312CD8 4E 80 04 21 */ bctrl
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lbl_80312CDC:
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/* 80312CDC 54 60 06 3E */ clrlwi r0, r3, 0x18
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/* 80312CE0 7C 1C 00 40 */ cmplw r28, r0
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/* 80312CE4 7C 03 03 78 */ mr r3, r0
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/* 80312CE8 40 81 00 08 */ ble lbl_80312CF0
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/* 80312CEC 7F 83 E3 78 */ mr r3, r28
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lbl_80312CF0:
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/* 80312CF0 57 C0 01 4B */ rlwinm. r0, r30, 0, 5, 5
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/* 80312CF4 41 82 00 20 */ beq lbl_80312D14
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/* 80312CF8 1C 83 00 37 */ mulli r4, r3, 0x37
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/* 80312CFC 38 03 00 01 */ addi r0, r3, 1
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/* 80312D00 54 00 F8 7E */ srwi r0, r0, 1
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/* 80312D04 1C 00 00 37 */ mulli r0, r0, 0x37
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/* 80312D08 7C 84 02 14 */ add r4, r4, r0
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/* 80312D0C 7F FF 22 14 */ add r31, r31, r4
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/* 80312D10 48 00 00 0C */ b lbl_80312D1C
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lbl_80312D14:
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/* 80312D14 1C 03 00 37 */ mulli r0, r3, 0x37
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/* 80312D18 7F FF 02 14 */ add r31, r31, r0
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lbl_80312D1C:
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/* 80312D1C 57 DC 67 3F */ rlwinm. r28, r30, 0xc, 0x1c, 0x1f
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/* 80312D20 41 82 00 7C */ beq lbl_80312D9C
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/* 80312D24 80 7D 00 28 */ lwz r3, 0x28(r29)
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/* 80312D28 80 63 00 04 */ lwz r3, 4(r3)
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/* 80312D2C 80 63 00 2C */ lwz r3, 0x2c(r3)
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/* 80312D30 81 83 00 00 */ lwz r12, 0(r3)
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/* 80312D34 81 8C 00 98 */ lwz r12, 0x98(r12)
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/* 80312D38 7D 89 03 A6 */ mtctr r12
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/* 80312D3C 4E 80 04 21 */ bctrl
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/* 80312D40 54 60 06 3E */ clrlwi r0, r3, 0x18
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/* 80312D44 28 00 00 08 */ cmplwi r0, 8
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/* 80312D48 40 81 00 0C */ ble lbl_80312D54
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/* 80312D4C 38 60 00 08 */ li r3, 8
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/* 80312D50 48 00 00 20 */ b lbl_80312D70
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lbl_80312D54:
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/* 80312D54 80 7D 00 28 */ lwz r3, 0x28(r29)
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/* 80312D58 80 63 00 04 */ lwz r3, 4(r3)
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/* 80312D5C 80 63 00 2C */ lwz r3, 0x2c(r3)
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/* 80312D60 81 83 00 00 */ lwz r12, 0(r3)
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/* 80312D64 81 8C 00 98 */ lwz r12, 0x98(r12)
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/* 80312D68 7D 89 03 A6 */ mtctr r12
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/* 80312D6C 4E 80 04 21 */ bctrl
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lbl_80312D70:
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/* 80312D70 54 60 06 3E */ clrlwi r0, r3, 0x18
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/* 80312D74 7C 1C 00 40 */ cmplw r28, r0
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/* 80312D78 7C 03 03 78 */ mr r3, r0
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/* 80312D7C 40 81 00 08 */ ble lbl_80312D84
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/* 80312D80 7F 83 E3 78 */ mr r3, r28
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lbl_80312D84:
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/* 80312D84 1C 03 00 0A */ mulli r0, r3, 0xa
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/* 80312D88 7F FF 02 14 */ add r31, r31, r0
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/* 80312D8C 57 C0 01 09 */ rlwinm. r0, r30, 0, 4, 4
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/* 80312D90 41 82 00 0C */ beq lbl_80312D9C
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/* 80312D94 1C 03 00 05 */ mulli r0, r3, 5
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/* 80312D98 7F FF 02 14 */ add r31, r31, r0
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lbl_80312D9C:
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/* 80312D9C 38 1F 00 1F */ addi r0, r31, 0x1f
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/* 80312DA0 54 03 00 34 */ rlwinm r3, r0, 0, 0, 0x1a
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/* 80312DA4 39 61 00 20 */ addi r11, r1, 0x20
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/* 80312DA8 48 04 F4 7D */ bl _restgpr_28
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/* 80312DAC 80 01 00 24 */ lwz r0, 0x24(r1)
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/* 80312DB0 7C 08 03 A6 */ mtlr r0
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/* 80312DB4 38 21 00 20 */ addi r1, r1, 0x20
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/* 80312DB8 4E 80 00 20 */ blr
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@@ -1,78 +0,0 @@
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lbl_80312E08:
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/* 80312E08 94 21 FF F0 */ stwu r1, -0x10(r1)
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/* 80312E0C 7C 08 02 A6 */ mflr r0
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/* 80312E10 90 01 00 14 */ stw r0, 0x14(r1)
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/* 80312E14 93 E1 00 0C */ stw r31, 0xc(r1)
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/* 80312E18 7C 7F 1B 78 */ mr r31, r3
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/* 80312E1C 80 63 00 38 */ lwz r3, 0x38(r3)
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/* 80312E20 38 63 00 88 */ addi r3, r3, 0x88
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/* 80312E24 4B FF E2 49 */ bl setArray__15J3DVertexBufferCFv
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/* 80312E28 80 9F 00 38 */ lwz r4, 0x38(r31)
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/* 80312E2C 3C 60 80 43 */ lis r3, j3dSys@ha /* 0x80434AC8@ha */
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/* 80312E30 38 63 4A C8 */ addi r3, r3, j3dSys@l /* 0x80434AC8@l */
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/* 80312E34 90 83 00 38 */ stw r4, 0x38(r3)
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/* 80312E38 93 E3 00 40 */ stw r31, 0x40(r3)
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/* 80312E3C 80 04 00 08 */ lwz r0, 8(r4)
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/* 80312E40 54 00 E7 FE */ rlwinm r0, r0, 0x1c, 0x1f, 0x1f
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/* 80312E44 98 0D 90 31 */ stb r0, struct_804515B0+0x1(r13)
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/* 80312E48 80 04 00 08 */ lwz r0, 8(r4)
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/* 80312E4C 54 00 07 7B */ rlwinm. r0, r0, 0, 0x1d, 0x1d
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/* 80312E50 41 82 00 18 */ beq lbl_80312E68
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/* 80312E54 80 7F 00 28 */ lwz r3, 0x28(r31)
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/* 80312E58 80 03 00 0C */ lwz r0, 0xc(r3)
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/* 80312E5C 60 00 00 04 */ ori r0, r0, 4
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/* 80312E60 90 03 00 0C */ stw r0, 0xc(r3)
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/* 80312E64 48 00 00 14 */ b lbl_80312E78
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lbl_80312E68:
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/* 80312E68 80 7F 00 28 */ lwz r3, 0x28(r31)
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/* 80312E6C 80 03 00 0C */ lwz r0, 0xc(r3)
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/* 80312E70 54 00 07 B8 */ rlwinm r0, r0, 0, 0x1e, 0x1c
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/* 80312E74 90 03 00 0C */ stw r0, 0xc(r3)
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lbl_80312E78:
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/* 80312E78 80 7F 00 38 */ lwz r3, 0x38(r31)
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/* 80312E7C 80 03 00 08 */ lwz r0, 8(r3)
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/* 80312E80 54 00 07 39 */ rlwinm. r0, r0, 0, 0x1c, 0x1c
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/* 80312E84 41 82 00 24 */ beq lbl_80312EA8
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/* 80312E88 80 7F 00 28 */ lwz r3, 0x28(r31)
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/* 80312E8C 80 03 00 0C */ lwz r0, 0xc(r3)
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/* 80312E90 54 00 C7 FF */ rlwinm. r0, r0, 0x18, 0x1f, 0x1f
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/* 80312E94 40 82 00 14 */ bne lbl_80312EA8
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/* 80312E98 80 03 00 0C */ lwz r0, 0xc(r3)
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/* 80312E9C 60 00 00 08 */ ori r0, r0, 8
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/* 80312EA0 90 03 00 0C */ stw r0, 0xc(r3)
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/* 80312EA4 48 00 00 14 */ b lbl_80312EB8
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lbl_80312EA8:
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/* 80312EA8 80 7F 00 28 */ lwz r3, 0x28(r31)
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/* 80312EAC 80 03 00 0C */ lwz r0, 0xc(r3)
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/* 80312EB0 54 00 07 76 */ rlwinm r0, r0, 0, 0x1d, 0x1b
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/* 80312EB4 90 03 00 0C */ stw r0, 0xc(r3)
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lbl_80312EB8:
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/* 80312EB8 80 7F 00 2C */ lwz r3, 0x2c(r31)
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/* 80312EBC 38 03 00 30 */ addi r0, r3, 0x30
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/* 80312EC0 80 9F 00 28 */ lwz r4, 0x28(r31)
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/* 80312EC4 90 04 00 60 */ stw r0, 0x60(r4)
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/* 80312EC8 80 03 00 04 */ lwz r0, 4(r3)
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/* 80312ECC 90 04 00 54 */ stw r0, 0x54(r4)
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/* 80312ED0 80 03 00 18 */ lwz r0, 0x18(r3)
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/* 80312ED4 90 04 00 58 */ stw r0, 0x58(r4)
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/* 80312ED8 88 04 00 34 */ lbz r0, 0x34(r4)
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/* 80312EDC 28 00 00 00 */ cmplwi r0, 0
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/* 80312EE0 40 82 00 10 */ bne lbl_80312EF0
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/* 80312EE4 80 03 00 20 */ lwz r0, 0x20(r3)
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/* 80312EE8 90 04 00 5C */ stw r0, 0x5c(r4)
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/* 80312EEC 48 00 00 18 */ b lbl_80312F04
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lbl_80312EF0:
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/* 80312EF0 80 04 00 64 */ lwz r0, 0x64(r4)
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/* 80312EF4 80 63 00 28 */ lwz r3, 0x28(r3)
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/* 80312EF8 54 00 10 3A */ slwi r0, r0, 2
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/* 80312EFC 7C 03 00 2E */ lwzx r0, r3, r0
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/* 80312F00 90 04 00 5C */ stw r0, 0x5c(r4)
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lbl_80312F04:
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/* 80312F04 80 7F 00 38 */ lwz r3, 0x38(r31)
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/* 80312F08 80 63 00 04 */ lwz r3, 4(r3)
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/* 80312F0C 48 01 31 ED */ bl syncJ3DSysFlags__12J3DModelDataCFv
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/* 80312F10 83 E1 00 0C */ lwz r31, 0xc(r1)
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/* 80312F14 80 01 00 14 */ lwz r0, 0x14(r1)
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/* 80312F18 7C 08 03 A6 */ mtlr r0
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/* 80312F1C 38 21 00 10 */ addi r1, r1, 0x10
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/* 80312F20 4E 80 00 20 */ blr
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@@ -1,114 +0,0 @@
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lbl_8031544C:
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/* 8031544C 94 21 FF E0 */ stwu r1, -0x20(r1)
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/* 80315450 7C 08 02 A6 */ mflr r0
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/* 80315454 90 01 00 24 */ stw r0, 0x24(r1)
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/* 80315458 39 61 00 20 */ addi r11, r1, 0x20
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/* 8031545C 48 04 CD 79 */ bl _savegpr_27
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/* 80315460 7C 7F 1B 78 */ mr r31, r3
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/* 80315464 80 0D 90 50 */ lwz r0, sOldVcdVatCmd__8J3DShape(r13)
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/* 80315468 80 63 00 2C */ lwz r3, 0x2c(r3)
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/* 8031546C 7C 00 18 40 */ cmplw r0, r3
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/* 80315470 41 82 00 14 */ beq lbl_80315484
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/* 80315474 38 80 00 C0 */ li r4, 0xc0
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/* 80315478 48 04 AA 79 */ bl GXCallDisplayList
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/* 8031547C 80 1F 00 2C */ lwz r0, 0x2c(r31)
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/* 80315480 90 0D 90 50 */ stw r0, sOldVcdVatCmd__8J3DShape(r13)
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lbl_80315484:
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/* 80315484 88 0D 90 54 */ lbz r0, data_804515D4(r13)
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/* 80315488 28 00 00 00 */ cmplwi r0, 0
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/* 8031548C 41 82 00 60 */ beq lbl_803154EC
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/* 80315490 88 1F 00 48 */ lbz r0, 0x48(r31)
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/* 80315494 28 00 00 00 */ cmplwi r0, 0
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/* 80315498 40 82 00 54 */ bne lbl_803154EC
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/* 8031549C 80 BF 00 40 */ lwz r5, 0x40(r31)
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/* 803154A0 38 80 00 08 */ li r4, 8
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/* 803154A4 3C 60 CC 01 */ lis r3, 0xCC01 /* 0xCC008000@ha */
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/* 803154A8 98 83 80 00 */ stb r4, 0x8000(r3) /* 0xCC008000@l */
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/* 803154AC 38 00 00 30 */ li r0, 0x30
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/* 803154B0 98 03 80 00 */ stb r0, -0x8000(r3)
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/* 803154B4 90 A3 80 00 */ stw r5, -0x8000(r3)
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/* 803154B8 80 DF 00 44 */ lwz r6, 0x44(r31)
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/* 803154BC 98 83 80 00 */ stb r4, -0x8000(r3)
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/* 803154C0 38 00 00 40 */ li r0, 0x40
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/* 803154C4 98 03 80 00 */ stb r0, -0x8000(r3)
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/* 803154C8 90 C3 80 00 */ stw r6, -0x8000(r3)
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/* 803154CC 38 00 00 10 */ li r0, 0x10
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/* 803154D0 98 03 80 00 */ stb r0, -0x8000(r3)
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/* 803154D4 38 00 00 01 */ li r0, 1
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/* 803154D8 B0 03 80 00 */ sth r0, -0x8000(r3)
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/* 803154DC 38 00 10 18 */ li r0, 0x1018
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/* 803154E0 B0 03 80 00 */ sth r0, -0x8000(r3)
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/* 803154E4 90 A3 80 00 */ stw r5, -0x8000(r3)
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/* 803154E8 90 C3 80 00 */ stw r6, -0x8000(r3)
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lbl_803154EC:
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/* 803154EC 7F E3 FB 78 */ mr r3, r31
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/* 803154F0 4B FF FE A9 */ bl setArrayAndBindPipeline__8J3DShapeCFv
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/* 803154F4 80 1F 00 0C */ lwz r0, 0xc(r31)
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/* 803154F8 54 00 05 AD */ rlwinm. r0, r0, 0, 0x16, 0x16
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/* 803154FC 40 82 00 6C */ bne lbl_80315568
|
||||
/* 80315500 88 0D 90 31 */ lbz r0, struct_804515B0+0x1(r13)
|
||||
/* 80315504 28 00 00 00 */ cmplwi r0, 0
|
||||
/* 80315508 41 82 00 08 */ beq lbl_80315510
|
||||
/* 8031550C 4B FF DB 9D */ bl resetMtxLoadCache__11J3DShapeMtxFv
|
||||
lbl_80315510:
|
||||
/* 80315510 A3 DF 00 0A */ lhz r30, 0xa(r31)
|
||||
/* 80315514 3B 60 00 00 */ li r27, 0
|
||||
/* 80315518 83 BF 00 38 */ lwz r29, 0x38(r31)
|
||||
/* 8031551C 83 FF 00 3C */ lwz r31, 0x3c(r31)
|
||||
/* 80315520 48 00 00 38 */ b lbl_80315558
|
||||
lbl_80315524:
|
||||
/* 80315524 57 7C 13 BA */ rlwinm r28, r27, 2, 0xe, 0x1d
|
||||
/* 80315528 7C 7D E0 2E */ lwzx r3, r29, r28
|
||||
/* 8031552C 28 03 00 00 */ cmplwi r3, 0
|
||||
/* 80315530 41 82 00 14 */ beq lbl_80315544
|
||||
/* 80315534 81 83 00 00 */ lwz r12, 0(r3)
|
||||
/* 80315538 81 8C 00 18 */ lwz r12, 0x18(r12)
|
||||
/* 8031553C 7D 89 03 A6 */ mtctr r12
|
||||
/* 80315540 4E 80 04 21 */ bctrl
|
||||
lbl_80315544:
|
||||
/* 80315544 7C 7F E0 2E */ lwzx r3, r31, r28
|
||||
/* 80315548 28 03 00 00 */ cmplwi r3, 0
|
||||
/* 8031554C 41 82 00 08 */ beq lbl_80315554
|
||||
/* 80315550 4B FF F5 85 */ bl draw__12J3DShapeDrawCFv
|
||||
lbl_80315554:
|
||||
/* 80315554 3B 7B 00 01 */ addi r27, r27, 1
|
||||
lbl_80315558:
|
||||
/* 80315558 57 60 04 3E */ clrlwi r0, r27, 0x10
|
||||
/* 8031555C 7C 00 F0 40 */ cmplw r0, r30
|
||||
/* 80315560 41 80 FF C4 */ blt lbl_80315524
|
||||
/* 80315564 48 00 00 64 */ b lbl_803155C8
|
||||
lbl_80315568:
|
||||
/* 80315568 3C 60 80 43 */ lis r3, j3dSys@ha /* 0x80434AC8@ha */
|
||||
/* 8031556C 3B C3 4A C8 */ addi r30, r3, j3dSys@l /* 0x80434AC8@l */
|
||||
/* 80315570 80 7E 00 40 */ lwz r3, 0x40(r30)
|
||||
/* 80315574 80 63 00 30 */ lwz r3, 0x30(r3)
|
||||
/* 80315578 38 80 00 00 */ li r4, 0
|
||||
/* 8031557C 4B FF A5 65 */ bl J3DFifoLoadPosMtxImm__FPA4_fUl
|
||||
/* 80315580 80 7E 00 40 */ lwz r3, 0x40(r30)
|
||||
/* 80315584 80 63 00 30 */ lwz r3, 0x30(r3)
|
||||
/* 80315588 38 80 00 00 */ li r4, 0
|
||||
/* 8031558C 4B FF A5 D5 */ bl J3DFifoLoadNrmMtxImm__FPA4_fUl
|
||||
/* 80315590 A0 1F 00 0A */ lhz r0, 0xa(r31)
|
||||
/* 80315594 3B 60 00 00 */ li r27, 0
|
||||
/* 80315598 83 DF 00 3C */ lwz r30, 0x3c(r31)
|
||||
/* 8031559C 54 1F 04 3E */ clrlwi r31, r0, 0x10
|
||||
/* 803155A0 48 00 00 1C */ b lbl_803155BC
|
||||
lbl_803155A4:
|
||||
/* 803155A4 57 60 13 BA */ rlwinm r0, r27, 2, 0xe, 0x1d
|
||||
/* 803155A8 7C 7E 00 2E */ lwzx r3, r30, r0
|
||||
/* 803155AC 28 03 00 00 */ cmplwi r3, 0
|
||||
/* 803155B0 41 82 00 08 */ beq lbl_803155B8
|
||||
/* 803155B4 4B FF F5 21 */ bl draw__12J3DShapeDrawCFv
|
||||
lbl_803155B8:
|
||||
/* 803155B8 3B 7B 00 01 */ addi r27, r27, 1
|
||||
lbl_803155BC:
|
||||
/* 803155BC 57 60 04 3E */ clrlwi r0, r27, 0x10
|
||||
/* 803155C0 7C 00 F8 40 */ cmplw r0, r31
|
||||
/* 803155C4 41 80 FF E0 */ blt lbl_803155A4
|
||||
lbl_803155C8:
|
||||
/* 803155C8 39 61 00 20 */ addi r11, r1, 0x20
|
||||
/* 803155CC 48 04 CC 55 */ bl _restgpr_27
|
||||
/* 803155D0 80 01 00 24 */ lwz r0, 0x24(r1)
|
||||
/* 803155D4 7C 08 03 A6 */ mtlr r0
|
||||
/* 803155D8 38 21 00 20 */ addi r1, r1, 0x20
|
||||
/* 803155DC 4E 80 00 20 */ blr
|
||||
Reference in New Issue
Block a user