mirror of https://github.com/zeldaret/tp
187 lines
9.9 KiB
C
187 lines
9.9 KiB
C
#ifndef GXREGS_H
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#define GXREGS_H
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#include <revolution/gx.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <revolution/private/bp_reg.h>
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#include <revolution/private/cp_reg.h>
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#include <revolution/private/gen_reg.h>
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#include <revolution/private/pe_reg.h>
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#include <revolution/private/pi_reg.h>
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#include <revolution/private/ras_reg.h>
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#include <revolution/private/su_reg.h>
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#include <revolution/private/tev_reg.h>
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#include <revolution/private/tx_reg.h>
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#include <revolution/private/xf_mem.h>
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extern volatile void* __piReg;
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extern volatile void* __cpReg;
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extern volatile void* __peReg;
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extern volatile void* __memReg;
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#define MEM_PE_REQCOUNTH_IDX 0x27
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#define MEM_PE_REQCOUNTL_IDX 0x28
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/* GX fifo write helpers */
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#define GX_WRITE_U8(ub) \
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GXWGFifo.u8 = (u8)(ub)
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#define GX_WRITE_U16(us) \
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GXWGFifo.u16 = (u16)(us)
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#define GX_WRITE_U32(ui) \
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GXWGFifo.u32 = (u32)(ui)
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#define GX_WRITE_F32(f) \
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GXWGFifo.f32 = (f32)(f);
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#define GX_PI_REG_WRITE_U32(a, d) *(vu32*)((vu8*)__piReg + (a)) = (u32)(d)
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#define GX_PI_REG_READ_U32(a) *(vu32*)((vu8*)__piReg + (a))
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#define GX_CP_REG_WRITE_U16(a, d) *(vu16*)((vu16*)__cpReg + (a)) = (u16)(d)
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#define GX_CP_REG_READ_U16(a) *(vu16*)((vu16*)__cpReg + (a))
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#define GX_CP_REG_WRITE_U32(a, d) *(vu32*)((vu16*)__cpReg + (a)) = (u32)(d)
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#define GX_CP_REG_READ_U32(a) *(vu32*)((vu16*)__cpReg + (a))
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#define GX_MEM_REG_WRITE_U16(a, d) *(vu16*)((vu16*)__memReg + (a)) = (u16)(d)
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#define GX_MEM_REG_READ_U16(a) *(vu16*)((vu16*)__memReg + (a))
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#define GX_PE_REG_WRITE_U16(a, d) *(vu16*)((vu16*)__peReg + (a)) = (u16)(d)
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#define GX_PE_REG_READ_U16(a) *(vu16*)((vu16*)__peReg + (a))
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#define GX_CP_IDLE_REG_READ_U16(a) GX_CP_REG_READ_U16(a)
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#define GX_PI_REG_WRITE_U32(a, d) *(vu32*)((vu8*)__piReg + (a)) = (u32)(d)
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#define GX_PI_REG_READ_U32(a) *(vu32*)((vu8*)__piReg + (a))
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#define GX_CP_REG_WRITE_U16(a, d) *(vu16*)((vu16*)__cpReg + (a)) = (u16)(d)
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#define GX_CP_REG_READ_U16(a) *(vu16*)((vu16*)__cpReg + (a))
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#define GX_CP_REG_WRITE_U32(a, d) *(vu32*)((vu16*)__cpReg + (a)) = (u32)(d)
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#define GX_CP_REG_READ_U32(a) *(vu32*)((vu16*)__cpReg + (a))
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#define GX_MEM_REG_WRITE_U16(a, d) *(vu16*)((vu16*)__memReg + (a)) = (u16)(d)
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#define GX_MEM_REG_READ_U16(a) *(vu16*)((vu16*)__memReg + (a))
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#define GX_PE_REG_WRITE_U16(a, d) *(vu16*)((vu16*)__peReg + (a)) = (u16)(d)
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#define GX_PE_REG_READ_U16(a) *(vu16*)((vu16*)__peReg + (a))
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#define GX_CP_IDLE_REG_READ_U16(a) GX_CP_REG_READ_U16(a)
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#define GX_WRITE_CP_STRM_REG(addr, vtxfmt, data) \
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{ \
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GX_WRITE_U8(CP_OPCODE(0, 1)); \
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GX_WRITE_U8(CP_STREAM_REG((vtxfmt), (addr))); \
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GX_WRITE_U32((data)); \
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}
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// needed to match some places
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#define GX_WRITE_CP_STRM_REG_alt(addr, vtxfmt, data, rAddr) \
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{ \
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s32 regAddr; \
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GX_WRITE_U8(CP_OPCODE(0, 1)); \
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GX_WRITE_U8(CP_STREAM_REG((vtxfmt), (addr))); \
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GX_WRITE_U32((data)); \
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regAddr = rAddr; \
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}
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// needed to match some places
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#if DEBUG
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#define GX_WRITE_CP_STRM_REG_alt2(addr, vtxfmt, data, rAddr) \
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{ \
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s32 regAddr; \
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GX_WRITE_U8(CP_OPCODE(0, 1)); \
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GX_WRITE_U8(CP_STREAM_REG((vtxfmt), (addr))); \
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GX_WRITE_U32((data)); \
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regAddr = rAddr; \
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if (regAddr >= 0 && regAddr < 4) { \
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__GXData->indexBase[regAddr] = data; \
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} \
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}
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#else
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#define GX_WRITE_CP_STRM_REG_alt2(addr, vtxfmt, data, rAddr) GX_WRITE_CP_STRM_REG(addr, vtxfmt, data)
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#endif
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// needed to match some places
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#if DEBUG
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#define GX_WRITE_CP_STRM_REG_alt3(addr, vtxfmt, data, rAddr) \
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{ \
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s32 regAddr; \
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GX_WRITE_U8(CP_OPCODE(0, 1)); \
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GX_WRITE_U8(CP_STREAM_REG((vtxfmt), (addr))); \
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GX_WRITE_U32((data)); \
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regAddr = rAddr; \
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if (regAddr >= 0 && regAddr < 4) { \
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__GXData->indexStride[regAddr] = data; \
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} \
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}
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#else
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#define GX_WRITE_CP_STRM_REG_alt3(addr, vtxfmt, data, rAddr) GX_WRITE_CP_STRM_REG(addr, vtxfmt, data)
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#endif
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#define GX_WRITE_XF_REG(addr, data, cnt) \
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{ \
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GX_WRITE_U8(CP_OPCODE(0, 0x2)); \
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GX_WRITE_U32(CP_XF_LOADREGS((addr), (cnt))); \
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GX_WRITE_U32((data)); \
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VERIF_XF_REG(addr, data); \
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}
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#define GX_WRITE_XF_MEM_U32(addr, data) GX_WRITE_U32(data)
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#define GX_WRITE_XF_MEM_F32(addr, data) GX_WRITE_F32(data)
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#define GX_WRITE_RA_REG(reg) \
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{ \
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GX_WRITE_U8(CP_OPCODE(1, 0xC)); \
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GX_WRITE_U32((reg)); \
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VERIF_RAS_REG(reg); \
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}
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#ifdef __MWERKS__
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#define GX_DEFINE_GX_READ_COUNTER(unit) \
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inline u32 __GXRead##unit##CounterU32(u32 regAddrL, u32 regAddrH) { \
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u32 ctrH0, ctrH1, ctrL; \
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ctrH0 = GX_##unit##_REG_READ_U16(regAddrH); \
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do { \
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ctrH1 = ctrH0; \
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ctrL = GX_##unit##_REG_READ_U16(regAddrL); \
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ctrH0 = GX_##unit##_REG_READ_U16(regAddrH); \
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} while (ctrH0 != ctrH1); \
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return ((ctrH0 << 16) | ctrL); \
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}
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#else
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#define GX_DEFINE_GX_READ_COUNTER(unit)
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#endif
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#ifdef __MWERKS__
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#define FAST_FLAG_SET(regOrg, newFlag, shift, size) \
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do { \
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(regOrg) = (u32)__rlwimi((int)(regOrg), (int)(newFlag), (shift), (32 - (shift) - (size)), (31 - (shift))); \
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} while (0);
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#else
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#define FAST_FLAG_SET(regOrg, newFlag, shift, size)
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif // GXREGS_H
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