mirror of
https://github.com/zeldaret/tp
synced 2026-07-01 20:20:21 -04:00
Julgodis
101 lines
4.4 KiB
ArmAsm
101 lines
4.4 KiB
ArmAsm
lbl_80370618:
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/* 80370618 94 21 FF E0 */ stwu r1, -0x20(r1)
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/* 8037061C 7C 08 02 A6 */ mflr r0
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/* 80370620 28 04 00 60 */ cmplwi r4, 0x60
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/* 80370624 90 01 00 24 */ stw r0, 0x24(r1)
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/* 80370628 93 E1 00 1C */ stw r31, 0x1c(r1)
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/* 8037062C 93 C1 00 18 */ stw r30, 0x18(r1)
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/* 80370630 7C DE 33 78 */ mr r30, r6
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/* 80370634 40 81 00 0C */ ble lbl_80370640
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/* 80370638 38 60 07 01 */ li r3, 0x701
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/* 8037063C 48 00 01 34 */ b lbl_80370770
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lbl_80370640:
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/* 80370640 3C C0 80 3D */ lis r6, gTRKExceptionStatus@ha /* 0x803D3244@ha */
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/* 80370644 38 00 00 00 */ li r0, 0
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/* 80370648 3B E6 32 44 */ addi r31, r6, gTRKExceptionStatus@l /* 0x803D3244@l */
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/* 8037064C 7C 03 20 40 */ cmplw r3, r4
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/* 80370650 80 DF 00 0C */ lwz r6, 0xc(r31)
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/* 80370654 81 5F 00 00 */ lwz r10, 0(r31)
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/* 80370658 81 3F 00 04 */ lwz r9, 4(r31)
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/* 8037065C 81 1F 00 08 */ lwz r8, 8(r31)
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/* 80370660 98 1F 00 0D */ stb r0, 0xd(r31)
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/* 80370664 91 41 00 08 */ stw r10, 8(r1)
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/* 80370668 91 21 00 0C */ stw r9, 0xc(r1)
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/* 8037066C 91 01 00 10 */ stw r8, 0x10(r1)
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/* 80370670 90 C1 00 14 */ stw r6, 0x14(r1)
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/* 80370674 90 1E 00 00 */ stw r0, 0(r30)
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/* 80370678 41 81 00 B8 */ bgt lbl_80370730
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/* 8037067C 7C 83 20 50 */ subf r4, r3, r4
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/* 80370680 3D 00 80 45 */ lis r8, gTRKCPUState@ha /* 0x8044F338@ha */
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/* 80370684 38 04 00 01 */ addi r0, r4, 1
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/* 80370688 80 9E 00 00 */ lwz r4, 0(r30)
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/* 8037068C 54 06 10 3A */ slwi r6, r0, 2
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/* 80370690 2C 07 00 00 */ cmpwi r7, 0
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/* 80370694 7C 84 32 14 */ add r4, r4, r6
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/* 80370698 38 E8 F3 38 */ addi r7, r8, gTRKCPUState@l /* 0x8044F338@l */
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/* 8037069C 54 63 10 3A */ slwi r3, r3, 2
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/* 803706A0 90 9E 00 00 */ stw r4, 0(r30)
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/* 803706A4 7C 87 1A 14 */ add r4, r7, r3
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/* 803706A8 38 84 01 A8 */ addi r4, r4, 0x1a8
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/* 803706AC 41 82 00 14 */ beq lbl_803706C0
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/* 803706B0 7C A3 2B 78 */ mr r3, r5
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/* 803706B4 7C 05 03 78 */ mr r5, r0
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/* 803706B8 4B FF CB D5 */ bl TRKAppendBuffer_ui32
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/* 803706BC 48 00 00 74 */ b lbl_80370730
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lbl_803706C0:
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/* 803706C0 38 67 01 EC */ addi r3, r7, 0x1ec
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/* 803706C4 7C 04 18 40 */ cmplw r4, r3
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/* 803706C8 41 81 00 24 */ bgt lbl_803706EC
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/* 803706CC 38 C6 FF FC */ addi r6, r6, -4
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/* 803706D0 38 67 01 E8 */ addi r3, r7, 0x1e8
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/* 803706D4 7C C4 32 14 */ add r6, r4, r6
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/* 803706D8 7C 06 18 40 */ cmplw r6, r3
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/* 803706DC 41 80 00 10 */ blt lbl_803706EC
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/* 803706E0 3C 60 80 3D */ lis r3, gTRKRestoreFlags@ha /* 0x803D3238@ha */
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/* 803706E4 38 C0 00 01 */ li r6, 1
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/* 803706E8 98 C3 32 38 */ stb r6, gTRKRestoreFlags@l(r3) /* 0x803D3238@l */
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lbl_803706EC:
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/* 803706EC 3C 60 80 45 */ lis r3, gTRKCPUState@ha /* 0x8044F338@ha */
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/* 803706F0 38 63 F3 38 */ addi r3, r3, gTRKCPUState@l /* 0x8044F338@l */
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/* 803706F4 38 C3 02 78 */ addi r6, r3, 0x278
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/* 803706F8 7C 04 30 40 */ cmplw r4, r6
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/* 803706FC 41 81 00 28 */ bgt lbl_80370724
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/* 80370700 54 03 10 3A */ slwi r3, r0, 2
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/* 80370704 38 63 FF FC */ addi r3, r3, -4
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/* 80370708 7C 64 1A 14 */ add r3, r4, r3
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/* 8037070C 7C 03 30 40 */ cmplw r3, r6
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/* 80370710 41 80 00 14 */ blt lbl_80370724
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/* 80370714 3C 60 80 3D */ lis r3, gTRKRestoreFlags@ha /* 0x803D3238@ha */
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/* 80370718 38 C0 00 01 */ li r6, 1
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/* 8037071C 38 63 32 38 */ addi r3, r3, gTRKRestoreFlags@l /* 0x803D3238@l */
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/* 80370720 98 C3 00 01 */ stb r6, 1(r3)
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lbl_80370724:
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/* 80370724 7C A3 2B 78 */ mr r3, r5
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/* 80370728 7C 05 03 78 */ mr r5, r0
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/* 8037072C 4B FF C8 F1 */ bl TRKReadBuffer_ui32
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lbl_80370730:
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/* 80370730 88 1F 00 0D */ lbz r0, 0xd(r31)
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/* 80370734 28 00 00 00 */ cmplwi r0, 0
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/* 80370738 41 82 00 10 */ beq lbl_80370748
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/* 8037073C 38 00 00 00 */ li r0, 0
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/* 80370740 38 60 07 02 */ li r3, 0x702
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/* 80370744 90 1E 00 00 */ stw r0, 0(r30)
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lbl_80370748:
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/* 80370748 3C 80 80 3D */ lis r4, gTRKExceptionStatus@ha /* 0x803D3244@ha */
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/* 8037074C 80 C1 00 08 */ lwz r6, 8(r1)
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/* 80370750 38 E4 32 44 */ addi r7, r4, gTRKExceptionStatus@l /* 0x803D3244@l */
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/* 80370754 80 A1 00 0C */ lwz r5, 0xc(r1)
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/* 80370758 80 81 00 10 */ lwz r4, 0x10(r1)
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/* 8037075C 80 01 00 14 */ lwz r0, 0x14(r1)
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/* 80370760 90 C7 00 00 */ stw r6, 0(r7)
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/* 80370764 90 A7 00 04 */ stw r5, 4(r7)
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/* 80370768 90 87 00 08 */ stw r4, 8(r7)
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/* 8037076C 90 07 00 0C */ stw r0, 0xc(r7)
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lbl_80370770:
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/* 80370770 80 01 00 24 */ lwz r0, 0x24(r1)
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/* 80370774 83 E1 00 1C */ lwz r31, 0x1c(r1)
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/* 80370778 83 C1 00 18 */ lwz r30, 0x18(r1)
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/* 8037077C 7C 08 03 A6 */ mtlr r0
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/* 80370780 38 21 00 20 */ addi r1, r1, 0x20
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/* 80370784 4E 80 00 20 */ blr
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