mirror of
https://github.com/zeldaret/tww.git
synced 2026-07-05 12:53:36 -04:00
LagoLunatic
435 lines
7.8 KiB
C
435 lines
7.8 KiB
C
#include "dolphin/os/OSCache.h"
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#include "dolphin/base/PPCArch.h"
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#include "dolphin/db/db.h"
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#include "dolphin/os/OS.h"
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static ASM void DCEnable(void) {
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// clang-format off
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nofralloc
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sync
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mfspr r3, 0x3F0
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ori r3, r3, 0x4000
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mtspr 0x3F0, r3
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blr
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// clang-format on
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}
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ASM void DCInvalidateRange(register void* start, register u32 nBytes) {
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// clang-format off
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nofralloc
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cmplwi nBytes, 0
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blelr
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clrlwi r5, start, 0x1B
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add nBytes, nBytes, r5
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addi nBytes, nBytes, 0x1F
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srwi nBytes, nBytes, 5
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mtctr nBytes
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do_invalidate:
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dcbi 0, start
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addi start, start, 0x20
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bdnz do_invalidate
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blr
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// clang-format on
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}
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ASM void DCFlushRange(register void* start, register u32 nBytes) {
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// clang-format off
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nofralloc
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cmplwi nBytes, 0
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blelr
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clrlwi r5, start, 0x1B
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add nBytes, nBytes, r5
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addi nBytes, nBytes, 0x1F
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srwi nBytes, nBytes, 5
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mtctr nBytes
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do_flush:
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dcbf 0, start
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addi start, start, 0x20
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bdnz do_flush
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sc
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blr
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// clang-format on
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}
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ASM void DCStoreRange(register void* start, register u32 nBytes) {
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// clang-format off
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nofralloc
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cmplwi nBytes, 0
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blelr
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clrlwi r5, start, 0x1B
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add nBytes, nBytes, r5
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addi nBytes, nBytes, 0x1F
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srwi nBytes, nBytes, 5
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mtctr nBytes
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do_store:
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dcbst 0, start
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addi start, start, 0x20
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bdnz do_store
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sc
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blr
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// clang-format on
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}
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ASM void DCFlushRangeNoSync(register void* start, register u32 nBytes) {
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// clang-format off
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nofralloc
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cmplwi nBytes, 0
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blelr
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clrlwi r5, start, 0x1B
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add nBytes, nBytes, r5
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addi nBytes, nBytes, 0x1F
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srwi nBytes, nBytes, 5
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mtctr nBytes
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do_flush:
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dcbf 0, start
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addi start, start, 0x20
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bdnz do_flush
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blr
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// clang-format on
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}
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ASM void DCStoreRangeNoSync(register void* start, register u32 nBytes) {
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// clang-format off
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nofralloc
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cmplwi nBytes, 0
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blelr
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clrlwi r5, start, 0x1B
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add nBytes, nBytes, r5
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addi nBytes, nBytes, 0x1F
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srwi nBytes, nBytes, 5
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mtctr nBytes
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do_store:
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dcbst 0, start
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addi start, start, 0x20
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bdnz do_store
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blr
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// clang-format on
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}
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ASM void DCZeroRange(register void* start, register u32 nBytes) {
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// clang-format off
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nofralloc
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cmplwi nBytes, 0
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blelr
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clrlwi r5, start, 0x1B
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add nBytes, nBytes, r5
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addi nBytes, nBytes, 0x1F
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srwi nBytes, nBytes, 5
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mtctr nBytes
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do_zero:
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dcbz 0, start
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addi start, start, 0x20
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bdnz do_zero
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blr
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// clang-format on
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}
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ASM void ICInvalidateRange(register void* start, register u32 nBytes) {
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// clang-format off
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nofralloc
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cmplwi nBytes, 0
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blelr
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clrlwi r5, start, 0x1B
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add nBytes, nBytes, r5
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addi nBytes, nBytes, 0x1F
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srwi nBytes, nBytes, 5
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mtctr nBytes
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do_invalidate:
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icbi 0, start
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addi start, start, 0x20
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bdnz do_invalidate
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sync
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isync
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blr
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// clang-format on
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}
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ASM void ICFlashInvalidate(void) {
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// clang-format off
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nofralloc
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mfspr r3, 0x3F0
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ori r3, r3, 0x800
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mtspr 0x3F0, r3
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blr
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// clang-format on
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}
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static ASM void ICEnable(void) {
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// clang-format off
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nofralloc
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isync
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mfspr r3, 0x3F0
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ori r3, r3, 0x8000
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mtspr 0x3F0, r3
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blr
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// clang-format on
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}
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ASM void __LCEnable(void) {
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// clang-format off
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nofralloc
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mfmsr r5
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ori r5, r5, 0x1000
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mtmsr r5
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lis r3, 0x8000
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li r4, 0x400
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mtctr r4
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do_store:
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dcbt 0, r3
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dcbst 0, r3
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addi r3, r3, 0x20
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bdnz do_store
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mfspr r4, 0x398
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oris r4, r4, 0x100F
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mtspr 0x398, r4
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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lis r3, 0xE000
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ori r3, r3, 0x0002
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mtdbatl 3, r3
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ori r3, r3, 0x1FE
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mtdbatu 3, r3
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isync
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lis r3, 0xE000
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li r6, 0x200
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mtctr r6
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li r6, 0
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do_load:
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dcbz_l r6, r3
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addi r3, r3, 0x0020
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bdnz do_load
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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blr
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// clang-format on
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}
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void LCEnable(void) {
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BOOL interrupt = OSDisableInterrupts();
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__LCEnable();
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OSRestoreInterrupts(interrupt);
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}
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ASM void LCDisable(void) {
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// clang-format off
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nofralloc
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lis r3, 0xE000
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li r4, 0x200
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mtctr r4
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do_invalidate:
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dcbi 0, r3
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addi r3, r3, 0x20
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bdnz do_invalidate
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mfspr r4, 0x398
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rlwinm r4, r4, 0, 4, 2
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mtspr 0x398, r4
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blr
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// clang-format on
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}
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static ASM void LCStoreBlocks(register void* destAddr, register void* srcAddr,
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register u32 blockNum){
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// clang-format off
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nofralloc
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rlwinm r6, blockNum, 0x1E, 0x1B, 0x1F
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clrlwi destAddr, destAddr, 4
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or r6, r6, destAddr
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mtspr 0x39A, r6
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rlwinm r6, blockNum, 2, 0x1C, 0x1D
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or r6, r6, srcAddr
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ori r6, r6, 2
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mtspr 0x39B, r6
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blr
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// clang-format on
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} /* 8033B838-8033B8E4 336178 00AC+00 0/0 0/0 3/3 .text LCStoreData */
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u32 LCStoreData(void* destAddr, void* srcAddr, u32 nBytes) {
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u32 blocks = (nBytes + 31) / 32;
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u32 ret = (blocks + 127) / 128;
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while (blocks > 0) {
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if (blocks < 128) {
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LCStoreBlocks(destAddr, srcAddr, blocks);
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blocks = 0;
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} else {
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LCStoreBlocks(destAddr, srcAddr, 0);
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blocks -= 128;
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destAddr = (char*)destAddr + 0x1000;
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srcAddr = (char*)srcAddr + 0x1000;
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}
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}
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return ret;
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}
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ASM void LCQueueWait(register u32 len) {
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// clang-format off
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nofralloc
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addi len, len, 1
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LCQueueWait_04:
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mfspr r4, HID2
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rlwinm r4, r4, 8, 28, 31
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cmpw cr2, r4, len
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bge cr2, LCQueueWait_04
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blr
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// clang-format on
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}
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static void L2Disable(void) {
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__sync();
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PPCMtl2cr(PPCMfl2cr() & ~0x80000000);
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__sync();
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}
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void L2GlobalInvalidate(void) {
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L2Disable();
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PPCMtl2cr(PPCMfl2cr() | 0x00200000);
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while (PPCMfl2cr() & 0x00000001u)
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;
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PPCMtl2cr(PPCMfl2cr() & ~0x00200000);
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while (PPCMfl2cr() & 0x00000001u) {
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DBPrintf(">>> L2 INVALIDATE : SHOULD NEVER HAPPEN\n");
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}
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}
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void DMAErrorHandler(u16 error, OSContext* context, ...) {
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u32 hid2 = PPCMfhid2();
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OSReport("Machine check received\n");
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OSReport("HID2 = 0x%x SRR1 = 0x%x\n", hid2, context->srr1);
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if (!(hid2 & (HID2_DCHERR | HID2_DNCERR | HID2_DCMERR | HID2_DQOERR)) ||
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!(context->srr1 & SRR1_DMA_BIT)) {
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OSReport("Machine check was not DMA/locked cache related\n");
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OSDumpContext(context);
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PPCHalt();
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}
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OSReport("DMAErrorHandler(): An error occurred while processing DMA.\n");
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OSReport("The following errors have been detected and cleared :\n");
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if (hid2 & HID2_DCHERR) {
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OSReport("\t- Requested a locked cache tag that was already in the cache\n");
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}
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if (hid2 & HID2_DNCERR) {
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OSReport("\t- DMA attempted to access normal cache\n");
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}
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if (hid2 & HID2_DCMERR) {
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OSReport("\t- DMA missed in data cache\n");
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}
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if (hid2 & HID2_DQOERR) {
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OSReport("\t- DMA queue overflowed\n");
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}
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// write hid2 back to clear the error bits
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PPCMthid2(hid2);
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}
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static void L2Init(void) {
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u32 oldMSR;
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oldMSR = PPCMfmsr();
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__sync();
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PPCMtmsr(MSR_IR | MSR_DR);
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__sync();
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L2Disable();
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L2GlobalInvalidate();
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PPCMtmsr(oldMSR);
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}
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void L2Enable(void) {
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PPCMtl2cr((PPCMfl2cr() | L2CR_L2E) & ~L2CR_L2I);
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}
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void __OSCacheInit() {
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if (!(PPCMfhid0() & HID0_ICE)) {
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ICEnable();
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DBPrintf("L1 i-caches initialized\n");
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}
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if (!(PPCMfhid0() & HID0_DCE)) {
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DCEnable();
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DBPrintf("L1 d-caches initialized\n");
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}
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if (!(PPCMfl2cr() & L2CR_L2E)) {
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L2Init();
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L2Enable();
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DBPrintf("L2 cache initialized\n");
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}
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OSSetErrorHandler(OS_ERROR_MACHINE_CHECK, DMAErrorHandler);
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DBPrintf("Locked cache machine check handler installed\n");
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}
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