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https://github.com/patchzyy/wiicompiled
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patchzyy
237 lines
8.6 KiB
C++
237 lines
8.6 KiB
C++
// Data/instruction/locked cache maintenance HLE.
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#include <cstdint>
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#include <cstring>
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#include <iostream>
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#include "abi_bridge.h"
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#include "memory.h"
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#include "hle_stubs.h"
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#include "ppc_runtime.h"
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#include "runtime_log.h"
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#include "hle/gx/gx_internal.h"
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// ============================================================================
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// Data cache maintenance (DCInvalidate/Flush/Store)
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// These touch hardware on console; on host we fast-path them to avoid huge
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// translated loops while still validating the guest range.
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// ============================================================================
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namespace {
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struct CacheRange {
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uint32_t start = 0;
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uint32_t size = 0;
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};
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constexpr uint32_t kCacheLineSize = 32;
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bool NormalizeCacheRange(uint32_t addr, uint32_t length, CacheRange& out)
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{
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if (length == 0) {
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return false;
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}
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const uint32_t alignedStart = addr & ~(kCacheLineSize - 1u);
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const uint64_t end = static_cast<uint64_t>(addr) + static_cast<uint64_t>(length) + (kCacheLineSize - 1u);
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const uint64_t alignedEnd = end & ~(static_cast<uint64_t>(kCacheLineSize) - 1u);
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if (alignedEnd <= alignedStart || alignedEnd >= 0x100000000ull) {
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return false;
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}
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out.start = alignedStart;
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out.size = static_cast<uint32_t>(alignedEnd - alignedStart);
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return out.size != 0;
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}
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bool ValidateCacheRange(const char* label, const CacheRange& range)
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{
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if (range.size == 0) {
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return false;
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}
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if (!::Memory::Contains(range.start, range.size)) {
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RT_LOG(RT_TAG_OS) << label << ": range 0x" << std::hex << range.start
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<< " len=0x" << range.size << std::dec
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<< " outside guest memory; skipping" << std::endl;
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return false;
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}
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return true;
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}
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void DcRangeOp(const char* label, uint32_t addr, uint32_t length)
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{
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CacheRange range{};
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if (!NormalizeCacheRange(addr, length, range) || !ValidateCacheRange(label, range)) {
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return;
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}
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GxNotifyGuestRamDmaWrite(range.start, range.size);
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}
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} // namespace
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extern "C" void DCInvalidateRange_801a1600(uint32_t addr, uint32_t length)
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{
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DcRangeOp("DCInvalidateRange_801a1600", addr, length);
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}
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extern "C" void DCFlushRange_801a162c(uint32_t addr, uint32_t length)
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{
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DcRangeOp("DCFlushRange_801a162c", addr, length);
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}
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extern "C" void DCStoreRange_801a165c(uint32_t addr, uint32_t length)
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{
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DcRangeOp("DCStoreRange_801a165c", addr, length);
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}
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extern "C" void DCFlushRangeNoSync_801a168c(uint32_t addr, uint32_t length)
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{
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DcRangeOp("DCFlushRangeNoSync_801a168c", addr, length);
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}
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extern "C" void DCStoreRangeNoSync_801a16b8(uint32_t addr, uint32_t length)
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{
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DcRangeOp("DCStoreRangeNoSync_801a16b8", addr, length);
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}
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PPC_NATIVE_OVERRIDE_VOID(801A1600, DCInvalidateRange_801a1600, (uint32_t addr, uint32_t length), (addr, length));
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PPC_NATIVE_OVERRIDE_VOID(801A162C, DCFlushRange_801a162c, (uint32_t addr, uint32_t length), (addr, length));
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PPC_NATIVE_OVERRIDE_VOID(801A165C, DCStoreRange_801a165c, (uint32_t addr, uint32_t length), (addr, length));
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PPC_NATIVE_OVERRIDE_VOID(801A168C, DCFlushRangeNoSync_801a168c, (uint32_t addr, uint32_t length), (addr, length));
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PPC_NATIVE_OVERRIDE_VOID(801A16B8, DCStoreRangeNoSync_801a16b8, (uint32_t addr, uint32_t length), (addr, length));
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// ----------------------------------------------------------------------------
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// CPU Cache Maintenance Stubs (DC/IC/LC)
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// These are safe to no-op because the host CPU handles caching.
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// ----------------------------------------------------------------------------
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extern "C" void Cache_Maintenance_Stub()
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{
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}
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namespace {
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constexpr uint32_t kCacheOpLineSize = 32u;
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constexpr uint32_t kLcOpPageSize = 4096u;
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constexpr uint32_t kLcOpMaxBlocksPerTransfer = 128u;
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uint32_t AlignDown32(uint32_t value)
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{
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return value & ~(kCacheOpLineSize - 1u);
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}
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uint32_t AlignUp32(uint32_t value)
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{
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return (value + (kCacheOpLineSize - 1u)) & ~(kCacheOpLineSize - 1u);
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}
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uint32_t DecodeLcBlockCount(uint32_t encodedBlockCount)
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{
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const uint32_t blocks = encodedBlockCount & 0x7Fu;
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return blocks == 0 ? kLcOpMaxBlocksPerTransfer : blocks;
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}
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bool CopyGuestRange(uint32_t dstAddr, uint32_t srcAddr, uint32_t len, const char* opName)
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{
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if (len == 0) {
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return true;
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}
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try {
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auto* dst = ::Memory::GetPointer(dstAddr, len);
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auto* src = ::Memory::GetPointer(srcAddr, len);
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std::memmove(dst, src, len);
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return true;
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} catch (const ::Memory::AccessViolation& e) {
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RT_LOG(RT_TAG_OS) << opName << ": memory access failed @0x" << std::hex << e.address()
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<< " len=0x" << len << std::dec << " (" << e.reason() << ")" << std::endl;
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return false;
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}
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}
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} // namespace
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extern "C" void DCZeroRange_HLE_801a16e4(CpuContext* ctx)
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{
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const uint32_t addr = static_cast<uint32_t>(ctx->gpr[3]);
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const uint32_t len = static_cast<uint32_t>(ctx->gpr[4]);
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if (len == 0) {
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return;
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}
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const uint32_t alignedAddr = AlignDown32(addr);
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const uint32_t alignedLen = AlignUp32((addr - alignedAddr) + len);
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try {
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auto* dst = ::Memory::GetPointer(alignedAddr, alignedLen);
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std::memset(dst, 0, alignedLen);
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GxNotifyGuestRamDmaWrite(alignedAddr, alignedLen);
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} catch (const ::Memory::AccessViolation& e) {
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RT_LOG(RT_TAG_OS) << "DCZeroRange: memory access failed @0x" << std::hex << e.address()
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<< " len=0x" << alignedLen << std::dec << " (" << e.reason() << ")" << std::endl;
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}
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}
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extern "C" void LCLoadBlocks_HLE_801a1894(CpuContext* ctx)
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{
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const uint32_t dstAddr = static_cast<uint32_t>(ctx->gpr[3]);
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const uint32_t srcAddr = static_cast<uint32_t>(ctx->gpr[4]);
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const uint32_t blocks = DecodeLcBlockCount(static_cast<uint32_t>(ctx->gpr[5]));
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const uint32_t len = blocks * kCacheOpLineSize;
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if (CopyGuestRange(dstAddr, srcAddr, len, "LCLoadBlocks")) {
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// RAM->LC loads are DMA reads on console, but the destination range is
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// still a guest RAM alias as far as the runtime is concerned; notify it
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// the same way LCStoreBlocks below does.
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GxNotifyGuestRamDmaWrite(dstAddr, len);
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}
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}
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extern "C" void LCStoreBlocks_HLE_801a18b8(CpuContext* ctx)
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{
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const uint32_t dstAddr = static_cast<uint32_t>(ctx->gpr[3]);
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const uint32_t srcAddr = static_cast<uint32_t>(ctx->gpr[4]);
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const uint32_t blocks = DecodeLcBlockCount(static_cast<uint32_t>(ctx->gpr[5]));
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const uint32_t len = blocks * kCacheOpLineSize;
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if (CopyGuestRange(dstAddr, srcAddr, len, "LCStoreBlocks")) {
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// LC->RAM stores are DMA writes on console; no flush follows them.
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GxNotifyGuestRamDmaWrite(dstAddr, len);
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}
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}
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extern "C" uint32_t LCStoreData_HLE_801a18dc(CpuContext* ctx)
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{
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const uint32_t dstAddr = static_cast<uint32_t>(ctx->gpr[3]);
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const uint32_t srcAddr = static_cast<uint32_t>(ctx->gpr[4]);
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const uint32_t len = static_cast<uint32_t>(ctx->gpr[5]);
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if (CopyGuestRange(dstAddr, srcAddr, len, "LCStoreData") && len != 0) {
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GxNotifyGuestRamDmaWrite(dstAddr, len);
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}
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const uint32_t pagesQueued = len == 0 ? 0u : ((len + kLcOpPageSize - 1u) / kLcOpPageSize);
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ctx->gpr[3] = pagesQueued;
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return pagesQueued;
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}
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extern "C" uint32_t LCQueueLength_HLE_801a197c(CpuContext*)
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{
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// We execute LC transfers synchronously, so the DMA queue is always drained.
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return 0;
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}
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extern "C" void LCQueueWait_HLE_801a1988(CpuContext*)
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{
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// Synchronous HLE copy completes immediately.
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}
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PPC_NATIVE_OVERRIDE_VOID(801a15ec, Cache_Maintenance_Stub, (), ()); // DCEnable
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PPC_NATIVE_OVERRIDE_VOID(801a16e4, DCZeroRange_HLE_801a16e4, (CpuContext* ctx), (ctx)); // DCZeroRange
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PPC_NATIVE_OVERRIDE_VOID(801a1710, Cache_Maintenance_Stub, (), ()); // ICInvalidateRange
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PPC_NATIVE_OVERRIDE_VOID(801a1744, Cache_Maintenance_Stub, (), ()); // ICFlashInvalidate
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PPC_NATIVE_OVERRIDE_VOID(801a1754, Cache_Maintenance_Stub, (), ()); // ICEnable
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PPC_NATIVE_OVERRIDE_VOID(801a1768, Cache_Maintenance_Stub, (), ()); // __LCEnable
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PPC_NATIVE_OVERRIDE_VOID(801a1834, Cache_Maintenance_Stub, (), ()); // LCEnable
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PPC_NATIVE_OVERRIDE_VOID(801a186c, Cache_Maintenance_Stub, (), ()); // LCDisable
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PPC_NATIVE_OVERRIDE_VOID(801a1894, LCLoadBlocks_HLE_801a1894, (CpuContext* ctx), (ctx)); // LCLoadBlocks
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PPC_NATIVE_OVERRIDE_VOID(801a18b8, LCStoreBlocks_HLE_801a18b8, (CpuContext* ctx), (ctx)); // LCStoreBlocks
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PPC_NATIVE_OVERRIDE(801a18dc, LCStoreData_HLE_801a18dc, uint32_t, (CpuContext* ctx), (ctx)); // LCStoreData
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PPC_NATIVE_OVERRIDE(801a197c, LCQueueLength_HLE_801a197c, uint32_t, (CpuContext* ctx), (ctx)); // LCQueueLength
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PPC_NATIVE_OVERRIDE_VOID(801a1988, LCQueueWait_HLE_801a1988, (CpuContext* ctx), (ctx)); // LCQueueWait
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PPC_NATIVE_OVERRIDE_VOID(801a1ae4, Cache_Maintenance_Stub, (), ()); // OS____CacheInit
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