phase12: match func_8006F6F4 (709 bodies / 718 regions)

config/regions.tsv

@@ -359,6 +359,7 @@
 0x8006EC94	0x8006ECD4	src/func_8006EC94.c
 0x8006F28C	0x8006F2F4	src/func_8006F28C.c
 0x8006F6BC	0x8006F6F4	src/func_8006F6BC.c
+0x8006F6F4	0x8006F77C	src/func_8006F6F4.c
 0x8006F930	0x8006F944	src/func_8006F930.c
 0x8006F944	0x8006F95C	src/func_8006F944.c
 0x8006F9B4	0x8006FA78	src/func_8006F9B4.c

src/func_8006F6F4.c

@@ -0,0 +1,42 @@
+/*
+ * func_8006F6F4 — 136 bytes at 0x8006F6F4..0x8006F77C
+ *
+ * Sets the gp flag D_801224D0, copies the four-word block at a1 to the
+ * absolute block at 0x80133230, and writes three signed half-scaled corrections
+ * to the absolute words at 0x801332A0, 0x801332A4, and 0x801332A8. The first
+ * correction uses the newly copied word; the next two use the absolute words at
+ * 0x80133234 and 0x80133238.
+ *
+ * The V4 assignment is intentional: it gives the target's four consecutive loads
+ * followed by four stores. The arithmetic is signed (`sra` after the integer
+ * division), and the direct address-named globals force the repeated `lui`/offset
+ * materializations in the target.
+ *
+ * LIMITS: field meanings and the global flag's purpose are not inferred. The
+ * addresses, V4 width, copy order, signed shift, subtraction order, and return
+ * are byte evidence.
+ */
+
+typedef struct V4 {
+    int w0;
+    int w1;
+    int w2;
+    int w3;
+} V4;
+
+extern int D_801224D0;
+extern V4 D_80133230;
+extern int D_80133234;
+extern int D_80133238;
+extern int D_801332A0;
+extern int D_801332A4;
+extern int D_801332A8;
+
+void func_8006F6F4(V4 *a0, V4 *a1)
+{
+    D_801224D0 = 1;
+    D_80133230 = *a1;
+    D_801332A0 = a0->w0 - (D_80133230.w0 >> 1);
+    D_801332A4 = a0->w1 - (D_80133234 >> 1);
+    D_801332A8 = a0->w2 - (D_80133238 >> 1);
+}