phase12: match func_800F50B0 (692 bodies / 701 regions)

config/match_worklist.tsv

@@ -987,7 +987,7 @@
 980	0x801007E0	0x80100808	40	fallthrough	3	frame	1	-	1
 #
 # listed=980
-# excluded_already_registered=698
+# excluded_already_registered=699
 # excluded_bad_extent_start=8
 # excluded_degenerate_body=252
 # excluded_delay_slot_start=5
@@ -996,6 +996,6 @@
 # excluded_low_confidence_grade=90
 # excluded_named_exclusion=9
 # excluded_no_extent=0
-# excluded_recorded_negative=102
+# excluded_recorded_negative=101
 # excluded_restores_unsaved=11
 # excluded_trapping_arith=48

config/regions.tsv

@@ -567,6 +567,7 @@
 0x800F44D0	0x800F452C	src/func_800F44D0.c	maspsx=epilogue
 0x800F452C	0x800F459C	src/func_800F452C.c	maspsx=epilogue
 0x800F4B88	0x800F4C08	src/func_800F4B88.c	maspsx=epilogue
+0x800F50B0	0x800F50D0	src/func_800F50B0.c
 0x800F5200	0x800F521C	src/func_800F5200.c
 0x800F5AF8	0x800F5B40	src/func_800F5AF8.c
 0x800F5B40	0x800F5B70	src/func_800F5B40.c

phase-ends/CURRENT_PHASE.md

@@ -6,19 +6,19 @@
 
 ## STATE — SOLO CONTINUATION, 2026-09-24 (current)
 
-**691 bodies / 700 regions**, from 685 / 694 at the last session stop — **+6 bodies / +6 regions**.
-The Phase 12 milestone remains 750 bodies, so **+59 remains**. The promoted whole-binary gate is green:
-`c_regions=700`, `differing_bytes=0`, SHA-1
+**692 bodies / 701 regions**, from 685 / 694 at the last session stop — **+7 bodies / +7 regions**.
+The Phase 12 milestone remains 750 bodies, so **+58 remains**. The promoted whole-binary gate is green:
+`c_regions=701`, `differing_bytes=0`, SHA-1
 `e173426c157384ebf1b6caf8c6fea18a85a14af9`; 344 synthetic tests pass and extents report
-`regions=700 disagreements=0 result=AGREE`.
+`regions=701 disagreements=0 result=AGREE`.
 
-Tasks 1–6/10 completed `0x80102F58` (60 bytes, plus three proven gp symbol rows), `0x80027BE8`
+Tasks 1–8/10 completed `0x80102F58` (60 bytes, plus three proven gp symbol rows), `0x80027BE8`
 (92 bytes, first spelling), `0x8006BB88` (128 bytes), `0x8008A400` (124 bytes), `0x800376CC`
-(164 bytes), and `0x80027D00` (136 bytes). The sixth required explicit non-overlapping register
-bindings, reversed-subtraction source forms, and the final `>=` branch spelling. Worklist regeneration
-is now 980 rows; `excluded_already_registered=698` continues the already-characterised two-row
-registry lag and is not a correctness issue because the 700-region gate proves the registry
-simultaneously.
+(164 bytes), `0x80027D00` (136 bytes), and `0x800F50B0` (32 bytes). The seventh scratchpad
+candidate and `0x80028698`/`0x8003570C` were bounded negatives; the eighth closes the small
+flag-builder with source block order plus v1/v0 bindings. Worklist regeneration remains 980 rows;
+`excluded_already_registered=699` continues the already-characterised two-row registry lag and is
+not a correctness issue because the 701-region gate proves the registry simultaneously.
 
 ## STATE — SESSION STOP, 2026-09-24 23:35 (historical; superseded by the state above, kept for provenance)
 

phase-ends/logs/Phase12.md

@@ -1961,3 +1961,33 @@ under `.run/p12/solo/`.
   `excluded_already_registered=698`, preserving the known two-row lag.
 
 **Count after task 6: 691 bodies / 700 regions (+89 bodies from the Phase 12 open baseline).**
+
+### Bounded attempts before task 8 — stopped without registration
+
+* `0x80030414` (196 B): the scratchpad macro shape, callbacks, frame, and all three stack switches
+  matched, but the original has `move a0,s0` before the first callback-era call. Explicit `$16`
+  binding and volatile pointer handoff did not make cc1 materialize that move; no inline move was
+  forced because it is not a developer-authorized structural exemption.
+* `0x80028698` (184 B): explicit result arrays produced the exact frame and local offsets, but the
+  three result stores landed in each call's delay slot rather than the target's staggered slots.
+  Volatile results did not change the layout.
+* `0x8003570C` (200 B): pointer bindings fixed the branch/length and much of the register shape, but
+  scalar value bindings removed required load-delay nops and produced 192 B. The remaining residual
+  is a source-order/register-liveness tie, not a missing semantic operation.
+
+### Task 8/10 — `0x800F50B0` (32 B) MATCH
+
+* Exact extent: `0x800F50B0..0x800F50D0`, 32 bytes, grade `exact`, no duplicate group.
+* The staged draft computed the low half before the high half. Swapping the source blocks reproduces
+  the original's `beqz a1` / high-base sequence, then `beqz a0` / low-mask sequence.
+* Binding the high accumulator to v1 and the low accumulator to v0 is byte-required: it produces the
+  target's final `or v0,v1,v0` in the jump delay slot.
+* Tracked source md5: `8bde98ac3ef3fd99aaf085d1158298c1`. Fresh tracked range: 32 bytes,
+  `differing_bytes=0 result=MATCH`.
+* `sf3_merge` accepted the claim. Candidate whole-binary gate: 701 regions, 0 differing bytes, both
+  SHA-1 values `e173426c157384ebf1b6caf8c6fea18a85a14af9`, exit 0.
+* Promoted `make check`: 344 tests OK; extents `regions=701 disagreements=0`; gate
+  `c_regions=701 differing_bytes=0 result=MATCH`. Worklist remains 980 rows and reports
+  `excluded_already_registered=699`, preserving the known two-row lag.
+
+**Count after task 8: 692 bodies / 701 regions (+90 bodies from the Phase 12 open baseline).**

src/func_800F50B0.c

@@ -0,0 +1,30 @@
+/*
+ * func_800F50B0 — 32 bytes at 0x800F50B0..0x800F50D0
+ *
+ * Builds a 32-bit value from two conditional flag groups. The high base is 0xe1000000;
+ * a nonzero second argument adds 0x200. The low value starts as the third argument masked
+ * with 0x9ff, and a nonzero first argument adds 0x400. The two halves are then ORed.
+ *
+ * The source order is byte-required: the original tests the second argument and materializes
+ * the high base first, then tests the first argument and materializes the low mask. Reversing
+ * those blocks changes the branch/constant schedule. The register bindings are also required:
+ * the high result is kept in v1 and the low result in v0, yielding the original's final
+ * `or v0,v1,v0` in the jump delay slot.
+ *
+ * LIMITS: the flag-bit semantics are not inferred beyond the observed constants and masks.
+ * The argument tests, constants, mask, ordering, and return composition are byte evidence.
+ */
+
+int func_800F50B0(int a0, int a1, int a2)
+{
+    register int v0 __asm__("$2");
+    register int v1 __asm__("$3");
+
+    v1 = 0xe1000000;
+    if (a1 != 0)
+        v1 |= 0x200;
+    v0 = a2 & 0x9ff;
+    if (a0 != 0)
+        v0 |= 0x400;
+    return v1 | v0;
+}