feat(decomp): ov_SC03_024 — 4 resolver-held drafts banked after the T2b surgery (func_8017D890, func_801812C4, func_801826E8, func_801848F4); re-verified byte-identical from a clean rebuild; T2b log (P31 S62)

phase-ends/CURRENT_PHASE.md

@@ -2312,3 +2312,14 @@ Fix: order re-aligned to the yaml, pads `0,0,0` (`commit:3084`); R22 clean rebui
 switch fns updated yaml+mk; re-verified clean). Lesson for R59: a blanket restore of overlays.mk
 must be diffed against every yaml it describes (order ⇔ subseg sequence) — `tools/`-worthy check.
 **NEXT: T2b** — ov_SC03_024 (+4 rodata shift in jr_8017AE2C.o; Max, solo).
+
+**T2b DONE (ov_SC03_024 GREEN, red 4 → 3, +4 banks).** The "+4 rodata shift in jr_8017AE2C.o":
+the object emits two 5-entry tables that retail lays back-to-back (+0x0, +0x14); with NO
+`JTBL_PADS` line for the object (git log -S: it never existed) the pads stage never ran and the
+default `.align 3` inserted a 4-byte zero word between them → every %lo downstream +4, binary +4
+(+1 trim), 1,041 sparse diffs from 0x4B8. S61's "pads-VALUE search found no unique winner" was a
+search over a nonexistent line (R40). Spec `0,0` added (`commit:3086`), R22 clean rebuild
+byte-identical (`c2cd16c4`), then its 4 held resolver drafts gated 4/4, re-verified clean.
+`.run/t1/interleave_check.py` (order ⇔ yaml) is ALIGNED for SC06_022/SC04_018 and shows a DRIFT on
+ov_SC02_005 (`jr_8018EA04.o` + `tail21` in the order, absent from the yaml) — T2e input.
+**NEXT: T2c** — ov_SC06_022 ('consumed 1 but 2'; Max, solo).

src/ov_SC03_024/ov_SC03_024_jr_8017AE2C.c

@@ -4446,7 +4446,30 @@ void func_8017D804(s32 param) {
 }
 
 
-INCLUDE_ASM("asm/ov_SC03_024/nonmatchings/ov_SC03_024_jr_8017AE2C", func_8017D890);
+extern u8 D_801C11F4;
+extern u8 D_801C11F5;
+extern u8 D_801C11F6;
+
+void func_8017D890(arg0, a1)
+void *arg0;
+void *a1;
+{
+    s16 var;
+
+    a1 = *(void **)((s32)arg0 + 0x20);
+    var = *(u16 *)((s32)a1 + 0x1A) + 0x200;
+    *(u16 *)((s32)a1 + 0x1A) = var;
+    *(u16 *)((s32)a1 + 0x18) = var;
+    if (var >= 0x1001) {
+        D_801C11F4 = 0xFF;
+        D_801C11F5 = 0xFF;
+        D_801C11F6 = 0xFF;
+        *(u16 *)((s32)a1 + 0x1A) = 0x1000;
+        *(u16 *)((s32)a1 + 0x18) = 0x1000;
+        *(u16 *)((s32)arg0 + 2) = *(u16 *)((s32)arg0 + 2) + 1;
+    }
+}
+
 
 
 /* func_8017D900 — fade the 4-byte colour quad at D_801C11F0 one step toward 0

src/ov_SC03_024/ov_SC03_024_jr_8017DF84.c

@@ -4788,7 +4788,44 @@ void func_80181230(void *a0)
 }
 
 
-INCLUDE_ASM("asm/ov_SC03_024/nonmatchings/ov_SC03_024_jr_8017DF84", func_801812C4);
+extern s32 rand(void);
+extern u16 D_800B99DA;
+extern u8 *func_801290DC(s32 arg0, u8 *arg1);
+extern u8 D_800AF630[];
+extern s32 D_801C1280;
+
+void func_801812C4(s32 param_1)
+{
+    register u8 *m __asm__("$4");
+    register s32 *cnt __asm__("$3");
+    u16 sp10[3];
+    s32 i;
+    s32 r;
+    s32 cond;
+
+    m = D_800AF630;
+    cond = D_800B99DA & 1;
+    cnt = &D_801C1280;
+    *cnt = cond ? 0xC0 : 0xB0;
+    if ((*(u16 *)(m + 0xA3AA) & 3) == 0) {
+        sp10[1] = *(u16 *)(param_1 + 0xA);
+        for (i = 0; i < 2; i++) {
+            r = rand();
+            {
+                register s32 t __asm__("$3") = *(u16 *)(param_1 + 6) - 0x10;
+                sp10[0] = t + (r & 0x1F);
+            }
+            r = rand();
+            cond = r & 0x1F;
+            {
+                register s32 u __asm__("$3") = *(u16 *)(param_1 + 0xE) - 0x10;
+                sp10[2] = u + cond;
+            }
+            func_801290DC(0x65, (u8 *)sp10);
+        }
+    }
+}
+
 
 
 extern void (*D_8018B0A4[])(void);
@@ -5671,7 +5708,41 @@ void func_801826B4(void *a0) {
     }
 
 
-INCLUDE_ASM("asm/ov_SC03_024/nonmatchings/ov_SC03_024_jr_8017DF84", func_801826E8);
+extern s32 func_80182784(s32 arg0, s32 arg1, s32 arg2);
+
+int func_801826E8(int a0, void* a1)
+{
+    s16 stack_buf[8];
+    register s16 *s0 __asm__("$16") = (s16 *)a1;
+    s16 v0;
+    s32 result;
+    s32 ret;
+
+    v0 = s0[2];
+    stack_buf[0] = v0;
+    v0 = s0[3];
+    stack_buf[4] = v0;
+    v0 = s0[5];
+    stack_buf[5] = v0;
+    stack_buf[1] = v0;
+    v0 = s0[6];
+    stack_buf[6] = v0;
+    stack_buf[2] = v0;
+
+    result = func_80182784((s32)a0, (s32)&stack_buf[0], (s32)&stack_buf[4]);
+
+    if (result != 0) {
+        ret = 1;
+    } else {
+        v0 = s0[7];
+        stack_buf[6] = v0;
+        stack_buf[2] = v0;
+        result = func_80182784((s32)a0, (s32)&stack_buf[0], (s32)&stack_buf[4]);
+        ret = (result != 0);
+    }
+    return ret;
+}
+
 
 extern s32 *D_80126B78;
 extern s32 *D_80126B90;

src/ov_SC03_024/ov_SC03_024_jr_80183BF8.c

@@ -3358,7 +3358,19 @@ INCLUDE_ASM("asm/ov_SC03_024/nonmatchings/ov_SC03_024_jr_80183BF8", func_8018481
 
 INCLUDE_ASM("asm/ov_SC03_024/nonmatchings/ov_SC03_024_jr_80183BF8", func_80184884);
 
-INCLUDE_ASM("asm/ov_SC03_024/nonmatchings/ov_SC03_024_jr_80183BF8", func_801848F4);
+void func_801848F4(int param_1)
+{
+    extern int func_8001AAA0(void);
+    extern s32 func_80178B18(s32 param_1, s32 param_2);
+    extern void (*D_8018B458[])(void *);
+
+    if (((s32 (*)(s32))func_8001AAA0)(0x69) != 0) {
+        *(unsigned short *)(param_1 + 2) = *(unsigned short *)(param_1 + 2) + 1;
+        func_80178B18(param_1, (s32)&D_8018B458);
+    }
+    return;
+}
+
 
 INCLUDE_ASM("asm/ov_SC03_024/nonmatchings/ov_SC03_024_jr_80183BF8", func_80184940);