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https://github.com/Druthulu/BFM-decomp
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feat(phase-32): T3 (8) — main: func_80023BF0 (281 ins) BANKED byte-identical 143dbb89 via gate_main — the OT link is libgpu's P_TAG 24-bit BITFIELD store (§364), not a hand-written mask/or
- the 11-18 plateau had two mutually-exclusive halves under (A & 0xFF000000) | (B & 0xFFFFFF): preheader hoist order
of the two masks vs &otab[idx], and the $t3/$t4 pairing of the mask register and the slot pointer. store_field ->
store_fixed_bit_field expands the RHS bitfield extract BEFORE the destination read, which fixes loop.c's movable
order [&otab[idx]; 0xFFFFFF; 0xFF000000] AND the ior operand roles at once (operand swap alone = 35). Third witness
for §364's -O2 half (func_8001D3FC/func_80021284/func_80023570 in the same TU already use the idiom).
- kept from the S79 90->18 chain (re-measured): the §194-A fence in both arms, `code` split from its base with
compound accumulation, register u32 base __asm__("$3"), and exactly 13 zero-byte fences after pkt = D_800A5E60
(0->15, 8->13, 10/11/12->7, 13->MATCH). Dropped as now inert: the m24 $11 and e1 $4 pins.
- the S80 permuter waypoint (closeness 11) was semantically UNSOUND (m24 sunk into one arm) and was not used (R63).
- rtu_match MATCH 281/281 (coordinator-verified); gate_main --apply 1/1, main byte-identical
This commit is contained in:
Drew T
@@ -15511,7 +15511,273 @@ void func_8002374C(s32 arg0)
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}
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INCLUDE_ASM("asm/nonmatchings/800", func_80023BF0);
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/* func_80023BF0 (main, src/800.c, 281 ins) -- MATCH, closeness 0.
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* Real TU (rtu_match --tu src/800.c) agrees: MATCH. Came in at 18 (the S79w opus
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* draft) / 11 (the S80 permuter waypoint, which was semantically UNSOUND -- it had
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* sunk `m24 = 0xFFFFFF` into the `c == 0x3870` arm of the sprite loop, leaving the
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* mask register undefined on any first iteration that takes the other arm).
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*
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* ============================================================================
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* WHAT CLOSED IT: THE OT LINK IS A libgpu P_TAG 24-BIT BITFIELD, NOT A MASK/OR
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* ============================================================================
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* Cookbook §364 + the func_8017FD64 addendum (L30700) describe this residual
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* EXACTLY and this function is a third witness for the -O2 half of it:
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*
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* symptom : a hand-written `(A & 0xFF000000) | (B & 0xFFFFFF)` OT link that
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* plateaus at closeness 10-18, where every remaining row is
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* (a) the paired lui/ori mask registers two-cycle-swapped against
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* the OT-slot pointer ($t3 <-> $t4 here), and
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* (b) the loop PREHEADER emitting the two mask constants BEFORE the
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* `sll/addu` that forms &otab[idx], where the target emits them
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* after -- in BOTH loop preheaders and again in the epilogue.
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* fix : write it as the bitfield store the SDK macro expands to
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* typedef struct { u32 addr : 24; u32 len : 8; } PTag;
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* ((PTag *)pkt)->addr = otab[idx].addr; -- setaddr(p, getaddr(ot))
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* otab[idx].addr = (u32)pkt; -- setaddr(ot, p)
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* ((PTag *)pkt)->len = 1; -- was pkt[3] = 1
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* mechanism: expand_assignment routes a bitfield destination through
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* store_field -> store_fixed_bit_field, which expands the VALUE
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* (the RHS bitfield EXTRACT: &otab[idx], lw, and-0xFFFFFF) before it
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* touches the destination (lw pkt, and-0xFF000000, ior, sw). That
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* single ordering change does three things at once:
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* * loop.c's movable list is built in body order, so the hoists
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* come out as [&otab[idx] ; 0xFFFFFF ; 0xFF000000] -- the
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* target's preheader order, in both arms;
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* * expand_binop(ior_optab, temp, value) puts the DEST-masked word
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* first, giving the target's `or $v1,$v1,$v0` operand roles and
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* therefore its $v0/$v1 assignment;
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* * the store-side `expand_and(value, mask)` is what emits the
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* target's `and $v1,$t1,$t3` (pkt & 0xFFFFFF) AHEAD of the slot
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* reload, which no hand-written spelling reproduces.
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* Writing the OR by hand fixes the emitted body but is unreachable
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* in the preheader: swapping the `|` operands to `(otab[idx] &
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* 0xFFFFFF) | (*(u32*)pkt & 0xFF000000)` DOES buy the target's hoist
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* order (measured: the preheader goes byte-exact) but then inverts
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* the body's two loads and the ior roles -- 35. The two halves are
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* mutually exclusive from a hand-written mask/or, and the bitfield
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* satisfies both because the pass order, not the source order, is
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* what differs. §364's -O2 veto (MEM_IN_STRUCT_P letting the alias
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* oracle CSE a global load across the tag store) does NOT bite here:
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* the only global read near the links is D_800B9A02, loaded once in
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* the prologue, so there is nothing to CSE away.
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*
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* The whole 90 -> 18 chain from the S79w draft was NOT wasted and is still load
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* bearing -- keep every one of these, each re-measured against this body:
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* 1. THE §194-A FENCE IN **BOTH** ARMS (the `__asm__ __volatile__("")` before
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* `c = *prims;`). Removing it: WIDTH, lhu != lbu. It stops sched1 hoisting
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* `lhu c` to the top of the block, which shortens c1's live_length 24 -> 16
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* and lifts its allocno priority above giv1's -- the only way to the target's
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* `c1 == arg0 == $a2` / `giv1 == $a3` / `x == $t0` triple.
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* 2. `code` SPLIT FROM ITS 0x74/0x76 BASE, accumulated compound
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* (`code = b26<<16; code |= (b25<<8)|base; code |= b24;`) so the first insn's
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* scratch is what set_preference (global.c:1535) hands `code`, plus
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* 3. `register u32 base __asm__("$3")`. Still REQUIRED (dropping the pin
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* re-colours the whole file from insn 9 on): base is a global allocno and so
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* invisible to local-alloc, so only a hard reg makes regs_live_at see $v1
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* occupied over the scratch's 2-insn window and push the scratch to $a0.
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* 4. THIRTEEN zero-byte fences after `pkt = D_800A5E60;` (pure §47 live-length
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* arithmetic). Re-measured on THIS body: 0 -> 15, 8 -> 13, 10/11/12 -> 7,
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* 13 -> MATCH. 13 is the minimum; 14 and 16 also match.
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* DROPPED as no longer needed once the bitfield lands (each re-measured MATCH):
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* `register u32 m24 __asm__("$11")` (the 0xFFFFFF pin -- the bitfield hoists
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* it into $t3 on its own, which is the point), and `register u32 e1
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* __asm__("$4")` for 0xE1000015 (now a plain literal).
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*
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* STRUCTURE (inherited from S69/S76/S77/S79, all still byte-verified -- keep it):
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* the dispatch is a balance_case_nodes median tree, source case order 0x1850,
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* 0x1858, 0x3870, 0x3871, 0x3872, default; 0x1850/0x1858 SHARE one body whose
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* head is stolen into the beq delay slot (§164-36b); the emit block appears
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* ONCE; packet fields are written PKT-RELATIVE so loop.c emits ONE combined
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* giv; `c` is declared INSIDE each arm; `tpage` is built through the `tp` temp,
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* never in place; and an intermediate the target computes in a SCRATCH register
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* is a NESTED EXPRESSION, not a second assignment to the same variable.
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* Do NOT introduce an explicit `u32 *ot = &otab[idx]` (function-scope, arm-local
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* or pinned): re-measured here too, it is an extra global allocno, buys a 4th
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* callee-saved register and costs +3 instructions (284).
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*
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* Symbols audited against this target's own relocation lines (law 1c): the .s
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* carries %hi/%lo of D_800AF630, D_800A6610, D_800B9A02, D_800A5E60 and no jal.
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*/
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extern u8 D_800AF630[];
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extern u8 D_800A6610[];
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extern u16 D_800B9A02;
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extern u8 *D_800A5E60;
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typedef struct { s16 vx, vy, vz, pad; } SVEC_80023BF0;
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typedef struct { u32 addr : 24; u32 len : 8; } PTag_80023BF0;
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#define SetRot_80023BF0(m) __asm__ volatile ( \
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"lw $12, 0(%0);" "lw $13, 4(%0);" "ctc2 $12, $0;" "ctc2 $13, $1;" \
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"lw $12, 8(%0);" "lw $13, 12(%0);" "lw $14, 16(%0);" \
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"ctc2 $12, $2;" "ctc2 $13, $3;" "ctc2 $14, $4" \
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: : "r"(m) : "$12", "$13", "$14")
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#define SetTrans_80023BF0(m) __asm__ volatile ( \
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"lw $12, 20(%0);" "lw $13, 24(%0);" "ctc2 $12, $5;" \
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"lw $14, 28(%0);" "ctc2 $13, $6;" "ctc2 $14, $7" \
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: : "r"(m) : "$12", "$13", "$14")
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void func_80023BF0(s32 arg0)
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{
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SVEC_80023BF0 v;
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u32 xy;
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u32 sxy2;
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u32 mac0;
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s32 z;
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u32 flags;
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u16 *prims;
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u16 b9;
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u16 idx;
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s32 x;
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s32 y;
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PTag_80023BF0 *otab;
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u8 *pkt;
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u32 code;
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s32 tpage;
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s32 tp;
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u8 *mat;
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register u32 base __asm__("$3");
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mat = D_800AF630;
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prims = *(u16 **)(arg0 + 0x20);
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b9 = D_800B9A02;
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flags = *(u32 *)(arg0 + 4);
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otab = (PTag_80023BF0 *)(b9 * 0x4000 + D_800A6610);
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if (flags & 0x4000000) {
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u8 *m = mat + 0x18;
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SetRot_80023BF0(m);
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SetTrans_80023BF0(m);
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v.vx = *(u16 *)(arg0 + 8) + *(u16 *)(arg0 + 0x2E);
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v.vy = *(u16 *)(arg0 + 0xA) + *(u16 *)(arg0 + 0x30);
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v.vz = *(u16 *)(arg0 + 0xC) + *(u16 *)(arg0 + 0x32);
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__asm__ volatile("lwc2 $0, 0(%0);lwc2 $1, 4(%0)" : : "r"(&v));
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__asm__ volatile("nop;nop;rtps");
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__asm__ volatile("swc2 $14, 0(%0)" : : "r"(&xy) : "memory");
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__asm__ volatile("swc2 $8, 0(%0)" : : "r"(&sxy2) : "memory");
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__asm__ volatile("cfc2 $12, $31;nop;sw $12, 0(%0)" : : "r"(&mac0) : "$12", "memory");
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__asm__ volatile("mfc2 $12, $19;nop;sra $12, $12, 2;sw $12, 0(%0)" : : "r"(&z) : "$12", "memory");
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if (z <= 0) {
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return;
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}
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idx = z + 1;
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{
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u32 t = xy;
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x = *(u16 *)(arg0 + 0xE) + t;
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y = t >> 16;
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}
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} else {
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x = *(u16 *)(arg0 + 0xE) + (*(u16 *)(arg0 + 8) + *(u16 *)(arg0 + 0x2E));
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idx = *(u16 *)(arg0 + 0x2C);
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y = *(u16 *)(arg0 + 0xA) + *(u16 *)(arg0 + 0x30);
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}
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tp = (*(u8 *)(arg0 + 0x27) + 0x100) << 6;
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if (*(u8 *)(arg0 + 0x27) < 0xE0) {
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tpage = tp | 0x16;
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} else {
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tpage = tp | 0x10;
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}
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pkt = D_800A5E60;
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__asm__ __volatile__("");
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__asm__ __volatile__("");
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__asm__ __volatile__("");
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__asm__ __volatile__("");
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__asm__ __volatile__("");
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__asm__ __volatile__("");
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__asm__ __volatile__("");
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__asm__ __volatile__("");
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__asm__ __volatile__("");
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__asm__ __volatile__("");
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__asm__ __volatile__("");
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__asm__ __volatile__("");
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__asm__ __volatile__("");
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if (!(flags & 0x400000)) {
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u16 c;
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base = 0x74000000;
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if (flags & 0x40000000) {
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base = 0x76000000;
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}
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code = *(u8 *)(arg0 + 0x26) << 16;
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code = code | ((*(u8 *)(arg0 + 0x25) << 8) | base);
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code = code | *(u8 *)(arg0 + 0x24);
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__asm__ __volatile__("");
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c = *prims;
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if (c != 0xFFFF) {
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do {
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switch (c) {
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case 0x1850:
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case 0x1858:
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*(u16 *)(pkt + 8) = x + 4;
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*(u16 *)(pkt + 0xA) = y - 7;
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break;
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case 0x3870:
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x += 7;
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prims++;
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continue;
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case 0x3871:
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x += 4;
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prims++;
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continue;
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case 0x3872:
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x += 2;
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prims++;
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continue;
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default:
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*(u16 *)(pkt + 8) = x;
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x += 7;
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*(u16 *)(pkt + 0xA) = y;
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break;
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}
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*(u32 *)pkt = 0x3000000;
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*(u32 *)(pkt + 4) = code;
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*(u16 *)(pkt + 0xC) = *prims++;
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*(u16 *)(pkt + 0xE) = tpage;
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((PTag_80023BF0 *)pkt)->addr = otab[idx].addr;
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otab[idx].addr = (u32)pkt;
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pkt += 0x10;
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} while ((c = *prims) != 0xFFFF);
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}
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} else {
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u16 c;
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base = 0x64000000;
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if (flags & 0x40000000) {
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base = 0x66000000;
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}
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code = *(u8 *)(arg0 + 0x26) << 16;
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code = code | ((*(u8 *)(arg0 + 0x25) << 8) | base);
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code = code | *(u8 *)(arg0 + 0x24);
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__asm__ __volatile__("");
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c = *prims;
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if (c != 0xFFFF) {
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do {
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if (c == 0x3870) {
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x += 0x10;
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prims++;
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} else {
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*(u16 *)(pkt + 8) = x;
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x += 0x10;
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*(u16 *)(pkt + 0xA) = y;
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*(u32 *)pkt = 0x4000000;
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*(u32 *)(pkt + 4) = code;
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*(u16 *)(pkt + 0xC) = *prims++;
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*(u16 *)(pkt + 0xE) = tpage;
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*(u32 *)(pkt + 0x10) = 0x180010;
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((PTag_80023BF0 *)pkt)->addr = otab[idx].addr;
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otab[idx].addr = (u32)pkt;
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pkt += 0x14;
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}
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} while ((c = *prims) != 0xFFFF);
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}
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}
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((PTag_80023BF0 *)pkt)->len = 1;
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*(u32 *)(pkt + 4) = ((flags >> 23) & 0x60) | 0xE1000015;
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((PTag_80023BF0 *)pkt)->addr = otab[idx].addr;
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D_800A5E60 = pkt + 0x40;
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otab[idx].addr = (u32)pkt;
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}
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s32 func_80024054(u8 *arg0, s16 *arg1)
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