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phase-36: S104 e11 packs (ov_SC04_011_jr_8017D494 batch)

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This commit is contained in:
Drew T
2026-09-11 01:38:07 -06:00
parent d9a6af0669
commit 04cf4c6168
33 changed files with 869 additions and 4 deletions
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.run/P36/agents/ORDER.tsv
+5 -4
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@@ -1,5 +1,6 @@
rank fn alias copies best needed kinds regs tu
90 func_80014DEC main 1 1 1 pin $2 src/800.c
313 func_80020598 main 1 9 1 pin $8 src/800.c
98 func_80015208 main 1 17 1 launder src/800.c
321 func_80021174 main 1 29 1 pin $2 src/800.c
1 func_80183E20 ov_SC04_011 1 2 1 barrier src/ov_SC04_011/ov_SC04_011_jr_8017D494.c
2 func_801833D4 ov_SC04_011 1 5 1 pin $19 src/ov_SC04_011/ov_SC04_011_jr_8017D494.c
5 func_80185214 ov_SC02_005 1 5 4 barrier,pin $16,$2,$4 src/ov_SC02_005/ov_SC02_005_jr_80185060.c
142 func_80185214 ov_SC04_011 1 6 1 pin $16 src/ov_SC04_011/ov_SC04_011_jr_8017D494.c
161 func_80186020 ov_SC04_011 1 7 1 pin $2 src/ov_SC04_011/ov_SC04_011_jr_8017D494.c
1 rank fn alias copies best needed kinds regs tu
2 90 1 func_80014DEC func_80183E20 main ov_SC04_011 1 1 2 1 pin barrier $2 src/800.c src/ov_SC04_011/ov_SC04_011_jr_8017D494.c
3 313 2 func_80020598 func_801833D4 main ov_SC04_011 1 9 5 1 pin $8 $19 src/800.c src/ov_SC04_011/ov_SC04_011_jr_8017D494.c
4 98 5 func_80015208 func_80185214 main ov_SC02_005 1 17 5 1 4 launder barrier,pin $16,$2,$4 src/800.c src/ov_SC02_005/ov_SC02_005_jr_80185060.c
5 321 142 func_80021174 func_80185214 main ov_SC04_011 1 29 6 1 pin $2 $16 src/800.c src/ov_SC04_011/ov_SC04_011_jr_8017D494.c
6 161 func_80186020 ov_SC04_011 1 7 1 pin $2 src/ov_SC04_011/ov_SC04_011_jr_8017D494.c
.run/P36/agents/ov_SC04_011__func_801833D4/body_free.c
+61
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@@ -0,0 +1,61 @@
s32 impl_801833D4(s32 a0, s32 a1)
{
/* $a1 is call-saved across func_801852BC/func_801853D0/func_80185648 until its one use
far below; gcc puts its param->hardreg move in the branch's delay slot rather than up
front. A plain local didn't reproduce that ordering vs. the s4=0 init -- pin it to $19
($s3, its natural hardreg) so the mid-fn scheduling matches (cookbook lever B/pin). */
s32 r1 = a1;
u16 s0;
s32 obj;
s32 s4;
/* v[2..4] is a 3-word (vel-like x/y/z) struct passed by address to func_800484EC; the
real local apparently has 2 leading words of other data ahead of it in the frame (its
address-taken struct forces gcc to reserve stack starting 2 words earlier than our x
field) -- v[0]/v[1] are unused padding needed only to reproduce the frame layout. */
s32 v[5];
s0 = D_801EFD20;
s4 = 0;
obj = aFC4C[s0];
if (D_801EFD40 & 0x4) {
func_801852BC(s0);
func_801853D0(s0);
func_80185648(s0);
v[3] = 0;
v[2] = 0;
if (D_801EFD40 & 0x20) {
v[4] = 0xFFD80000;
} else {
v[4] = 0xFFEC0000;
}
func_800484EC(*(s32 *)(obj + 0x20) + 0x34, (s32)&v[2], (s32)&v[2]);
*(s32 *)(obj + 0x4) += v[2];
*(s32 *)(obj + 0x8) += v[3];
*(s32 *)(obj + 0xC) += v[4];
*(u16 *)(*(s32 *)(obj + 0x20) + 0x14) =
*(u16 *)(*(s32 *)(obj + 0x20) + 0x14) + r1;
func_80183BF0(a0);
*(u16 *)(*(s32 *)(obj + 0x20) + 0x10) =
*(u16 *)(a0 + 0xFE) + *(u16 *)(a0 + 0x102);
if (func_801836D4((void *)a0, (void *)obj) != 0) {
s4 = 1;
} else {
if (D_801EFD40 & 0x20) {
s0 = 0x40;
} else {
s0 = 0x20;
}
func_80185960(*(s16 *)(a0 + 0x106), (u16 *)(*(s32 *)(obj + 0x20) + 0x12), s0);
func_80185960(*(s16 *)(a0 + 0x100), (u16 *)(a0 + 0xFE), s0);
}
}
return s4;
}
.run/P36/agents/ov_SC04_011__func_801833D4/body_tree.c
+61
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@@ -0,0 +1,61 @@
s32 impl_801833D4(s32 a0, s32 a1)
{
/* $a1 is call-saved across func_801852BC/func_801853D0/func_80185648 until its one use
far below; gcc puts its param->hardreg move in the branch's delay slot rather than up
front. A plain local didn't reproduce that ordering vs. the s4=0 init -- pin it to $19
($s3, its natural hardreg) so the mid-fn scheduling matches (cookbook lever B/pin). */
register s32 r1 __asm__("$19") = a1; // !FAKE: pin $19 — NEEDED DIFFERS (P36 rung B t3_tus1)
u16 s0;
s32 obj;
s32 s4;
/* v[2..4] is a 3-word (vel-like x/y/z) struct passed by address to func_800484EC; the
real local apparently has 2 leading words of other data ahead of it in the frame (its
address-taken struct forces gcc to reserve stack starting 2 words earlier than our x
field) -- v[0]/v[1] are unused padding needed only to reproduce the frame layout. */
s32 v[5];
s0 = D_801EFD20;
s4 = 0;
obj = aFC4C[s0];
if (D_801EFD40 & 0x4) {
func_801852BC(s0);
func_801853D0(s0);
func_80185648(s0);
v[3] = 0;
v[2] = 0;
if (D_801EFD40 & 0x20) {
v[4] = 0xFFD80000;
} else {
v[4] = 0xFFEC0000;
}
func_800484EC(*(s32 *)(obj + 0x20) + 0x34, (s32)&v[2], (s32)&v[2]);
*(s32 *)(obj + 0x4) += v[2];
*(s32 *)(obj + 0x8) += v[3];
*(s32 *)(obj + 0xC) += v[4];
*(u16 *)(*(s32 *)(obj + 0x20) + 0x14) =
*(u16 *)(*(s32 *)(obj + 0x20) + 0x14) + r1;
func_80183BF0(a0);
*(u16 *)(*(s32 *)(obj + 0x20) + 0x10) =
*(u16 *)(a0 + 0xFE) + *(u16 *)(a0 + 0x102);
if (func_801836D4((void *)a0, (void *)obj) != 0) {
s4 = 1;
} else {
if (D_801EFD40 & 0x20) {
s0 = 0x40;
} else {
s0 = 0x20;
}
func_80185960(*(s16 *)(a0 + 0x106), (u16 *)(*(s32 *)(obj + 0x20) + 0x12), s0);
func_80185960(*(s16 *)(a0 + 0x100), (u16 *)(a0 + 0xFE), s0);
}
}
return s4;
}
.run/P36/agents/ov_SC04_011__func_801833D4/history.txt
+14
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@@ -0,0 +1,14 @@
s5: verdict NO-MATCH start 5 best 5 compiles 185 path
best-scoring single candidates of the last trace (move -> score [residual class]):
R18 bystander @6911->6913 -> 5 [ORDER] (from 5)
R9 swap-stmts @6904 -> 5 [ORDER] (from 5)
R7 block @6904 -> 5 [ORDER] (from 5)
R6 inline r1 @6894 -> 5 [ORDER] (from 5)
R9 swap-stmts @6905 -> 5 [ORDER] (from 5)
R7 block @6905 -> 5 [ORDER] (from 5)
R7 block @6906 -> 5 [ORDER] (from 5)
R7 block @6909 -> 5 [ORDER] (from 5)
R7 do-while @6909 -> 5 [ORDER] (from 5)
R7 block @6910 -> 5 [ORDER] (from 5)
R7 do-while @6910 -> 5 [ORDER] (from 5)
R7 block @6911 -> 5 [ORDER] (from 5)
.run/P36/agents/ov_SC04_011__func_801833D4/neighbours.txt
+8
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@@ -0,0 +1,8 @@
--- every @class/@stuck/@crack note in this translation unit ---
// @class: schedule
// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// @class: struct
// @stuck: none — MATCH (fn-ptr table %lo-fold via extern array of code ptrs)
/* @class: instruction-scheduling (SOLVED — natural statement order)
// @class: loose-typing
// @stuck: none — MATCH (99 ins). short* for param_2/param_3: gcc emits lh where sign is live (<<1 for signed div), lhu where truncated to short (arith result / direct copy)
.run/P36/agents/ov_SC04_011__func_801833D4/related.txt
+169
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@@ -0,0 +1,169 @@
=== lever-free bodies in ov_SC04_011 sharing a callee or global with func_801833D4 (48 found; top 6 by shared symbols) — read them for the SHAPE ===
--- func_80183880 (src/ov_SC04_011/ov_SC04_011_jr_8017D494.c:7142) shares 8: D_801EFD20 D_801EFD40 func_800484EC func_80183BF0 func_801852BC func_801853D0 func_80185648 func_80185960 ---
void func_80183880(s32 a0)
{
extern u16 D_801EFD20;
extern u16 D_801EFD40;
extern s32 D_801EFC4C[];
extern void func_801852BC(s32);
extern void func_801853D0(s32);
extern void func_80185648();
extern void func_800484EC(s32, s32, s32);
extern s32 func_80183BF0(s32);
extern void func_80185960(s32, u16 *, s32);
u16 idx;
s32 obj;
s32 v[3];
s32 step;
s32 sub;
idx = D_801EFD20;
obj = D_801EFC4C[idx];
if (D_801EFD40 & 4) {
func_801852BC(idx);
func_801853D0(idx);
func_80185648(idx);
v[1] = 0;
v[0] = 0;
if (D_801EFD40 & 0x20) {
v[2] = 0xFFD80000;
} else {
v[2] = 0xFFEC0000;
}
func_800484EC(*(s32 *)(obj + 0x20) + 0x34, (s32)&v[0], (s32)&v[0]);
*(s32 *)(obj + 0x4) += v[0];
*(s32 *)(obj + 0x8) += v[1];
*(s32 *)(obj + 0xC) += v[2];
func_80183BF0(a0);
*(u16 *)(*(s32 *)(obj + 0x20) + 0x10) =
*(u16 *)(a0 + 0xFE) + *(u16 *)(a0 + 0x102);
func_80185960(*(s16 *)(a0 + 0x100), (u16 *)(a0 + 0xFE), 0x20);
if (D_801EFD40 & 0x20) {
step = 0x40;
} else {
step = 0x20;
}
sub = *(s32 *)(obj + 0x20);
if (*(s16 *)(sub + 0x12) < *(s16 *)(a0 + 0x106) + 0x1000) {
*(s16 *)(sub + 0x12) += step;
if (!(*(s16 *)(*(s32 *)(obj + 0x20) + 0x12) < *(s16 *)(a0 + 0x106) + 0x1000)) {
*(s16 *)(*(s32 *)(obj + 0x20) + 0x12) = *(s16 *)(a0 + 0x106) + 0x2000;
}
} else {
*(s16 *)(sub + 0x12) -= step;
if (!(*(s16 *)(a0 + 0x106) + 0x1000 < *(s16 *)(*(s32 *)(obj + 0x20) + 0x12))) {
*(s16 *)(*(s32 *)(obj + 0x20) + 0x12) = *(s16 *)(a0 + 0x106);
}
}
}
}
--- func_80187008 (src/ov_SC04_011/ov_SC04_011_jr_8017D494.c:9658) shares 5: D_801EFD20 D_801EFD40 func_801852BC func_801853D0 func_80185648 ---
void func_80187008(s32 arg0) {
s32 g = D_801EFD20;
func_801805F8(arg0);
if (D_801EFD40 & 4) {
func_801852BC(g);
func_801853D0(g);
func_80185648(g);
}
}
--- func_80183BF0 (src/ov_SC04_011/ov_SC04_011_jr_8017D494.c:7304) shares 2: D_801EFD40 func_80185960 ---
void impl_80183BF0(s32 a0)
{
s16 sVar1;
if (D_801EFD40 & 0x40) {
sVar1 = *(s16 *)(a0 + 0x102) + *(s16 *)(a0 + 0x104);
*(s16 *)(a0 + 0x102) = sVar1;
if (sVar1 < -0x17F) {
*(u16 *)(a0 + 0x104) = 0x20;
}
if (*(s16 *)(a0 + 0x102) >= 0x180) {
*(s16 *)(a0 + 0x104) = -0x20;
}
} else {
func_80185960(0, (u16 *)(a0 + 0x102), 0x20);
}
}
--- func_801858DC (src/ov_SC04_011/ov_SC04_011_jr_8017D494.c:8574) shares 2: D_801EFD40 func_80185960 ---
void func_801858DC(void *a0)
{
u16 step;
u16 flag;
flag = D_801EFD40;
step = 0x20;
if (flag & 0x20) {
step = 0x40;
}
func_80185960(*(s16 *)((s32)a0 + 0xE4),
(u16 *)((s32)(*(void **)((s32)a0 + 0x20)) + 0x10), step);
func_80185960(*(s16 *)((s32)a0 + 0xE6),
(u16 *)((s32)(*(void **)((s32)a0 + 0x20)) + 0x12), step);
func_80185960(*(s16 *)((s32)a0 + 0xE8),
(u16 *)((s32)(*(void **)((s32)a0 + 0x20)) + 0x14), step);
}
--- func_80180E80 (src/ov_SC04_011/ov_SC04_011_jr_8017D494.c:4928) shares 2: D_801EFD20 D_801EFD40 ---
void func_80180E80(u8 *self) {
s32 obj;
s32 vp1;
s32 vp2;
obj = aFC4C[D_801EFD20];
vp1 = *(s32 *)(obj + 0x20);
*(s16 *)(obj + 6) = 0x640;
*(s16 *)(obj + 0xA) = -0x980;
*(s16 *)(obj + 0xE) = 0x240;
*(s16 *)(vp1 + 0x12) = 0x600;
vp2 = *(s32 *)(obj + 0x20);
*(s16 *)(vp2 + 0x10) = 0;
*(s16 *)(self + 0xFE) = 0;
func_80186710();
*(s16 *)(self + 0xF4) = 0;
*(s16 *)(self + 0xF2) = 0;
func_80183564((s32)self, (s16 *)D_80194490);
D_801EFD40 = D_801EFD40 & 0xFDFF;
func_8012AD44((s32 *)self, 4);
}
--- func_80181868 (src/ov_SC04_011/ov_SC04_011_jr_8017D494.c:5319) shares 2: D_801EFD20 D_801EFD40 ---
void func_80181868(u8 *self) {
s32 obj;
s32 vp;
obj = aFC4C[D_801EFD20];
if (!(D_801EFD40 & 0x400)) {
D_801EFD18 = func_80188E00(obj, D_801944D0);
}
vp = *(s32 *)(obj + 0x20);
*(s16 *)(obj + 6) = 0x500;
*(s16 *)(obj + 0xA) = -0xD88;
*(s16 *)(obj + 0xE) = 0x1980;
*(s16 *)(vp + 0x12) = 0;
vp = *(s32 *)(obj + 0x20);
*(s16 *)(vp + 0x10) = 0x380;
*(s16 *)(self + 0xFE) = 0x380;
func_80186710();
func_80183BD0(self);
D_801EFD40 = D_801EFD40 & 0xFFF7;
func_80183564((s32)self, (s16 *)D_801944D0);
func_80186BD8();
func_8012AD44((s32 *)self, 7);
}
.run/P36/agents/ov_SC04_011__func_801833D4/residual.txt
+10
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@@ -0,0 +1,10 @@
src/ov_SC04_011/ov_SC04_011_jr_8017D494.c:func_801833D4: score 5 (ORDER; mine 100 ins, target 100) — not yet
register pairs (mine -> target, count): zero->a1 x1, s4->s3 x1
insert mine[8:8] target[8:10]
8 -- | sw s4,56(sp)
9 -- | move s4,zero
delete mine[9:11] target[11:11]
9 move s3,a1 | --
10 sw s4,56(sp) | --
replace mine[19:20] target[19:20]
19 move s4,zero | move s3,a1
.run/P36/agents/ov_SC04_011__func_801833D4/sites.txt
+1
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@@ -0,0 +1 @@
NEEDED pin $19 line 6998
.run/P36/agents/ov_SC04_011__func_801833D4/tu.txt
+2
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@@ -0,0 +1,2 @@
src/ov_SC04_011/ov_SC04_011_jr_8017D494.c
func_801833D4
.run/P36/agents/ov_SC04_011__func_80183E20/body_free.c
+30
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@@ -0,0 +1,30 @@
void aF80183E20(void *a0) {
extern u16 D_801EFD40;
extern u16 aEFD24 __asm__("D_801EFD24");
u16 flags;
u16 cnt;
s32 v0;
s32 v1;
s32 v1b;
flags = D_801EFD40;
if (flags & 0x80) {
v0 = *(u16 *)((u8 *)a0 + 0x76);
v1 = *(u16 *)((u8 *)a0 + 0x60);
*(u16 *)((u8 *)a0 + 0x60) = 0;
v0 = v0 - v1;
*(u16 *)((u8 *)a0 + 0x76) = v0;
v1b = *(s16 *)((u8 *)a0 + 0x76);
D_801EFD40 = flags & 0xFF7F;
if (v1b < 0) {
*(u16 *)((u8 *)a0 + 0x76) = 0;
}
}
cnt = aEFD24;
if (cnt != 0) {
cnt = cnt - 1;
aEFD24 = cnt;
if (cnt == 0) {
func_80186AB8();
}
}
}
.run/P36/agents/ov_SC04_011__func_80183E20/body_tree.c
+31
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@@ -0,0 +1,31 @@
void aF80183E20(void *a0) {
extern u16 D_801EFD40;
extern u16 aEFD24 __asm__("D_801EFD24");
u16 flags;
u16 cnt;
s32 v0;
s32 v1;
s32 v1b;
flags = D_801EFD40;
if (flags & 0x80) {
v0 = *(u16 *)((u8 *)a0 + 0x76);
v1 = *(u16 *)((u8 *)a0 + 0x60);
*(u16 *)((u8 *)a0 + 0x60) = 0;
v0 = v0 - v1;
*(u16 *)((u8 *)a0 + 0x76) = v0;
__asm__("":::"memory"); // !FAKE: barrier memory — NEEDED DIFFERS (P36 rung B t3_tus1)
v1b = *(s16 *)((u8 *)a0 + 0x76);
D_801EFD40 = flags & 0xFF7F;
if (v1b < 0) {
*(u16 *)((u8 *)a0 + 0x76) = 0;
}
}
cnt = aEFD24;
if (cnt != 0) {
cnt = cnt - 1;
aEFD24 = cnt;
if (cnt == 0) {
func_80186AB8();
}
}
}
.run/P36/agents/ov_SC04_011__func_80183E20/history.txt
+14
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@@ -0,0 +1,14 @@
s5: verdict NO-MATCH start 5 best 2 compiles 188 path R7 do-while @7410 + R9 swap-stmts @7411
best-scoring single candidates of the last trace (move -> score [residual class]):
R9 swap-stmts @7411 -> 2 [ORDER] (from 4)
R9 swap-stmts @7410 -> 3 [COUNT] (from 5)
R8 temp tmp0 @7407 -> 3 [COUNT] (from 3)
R7 block @7405 -> 3 [COUNT] (from 3)
R9 swap-stmts @7407 -> 3 [COUNT] (from 3)
R6 inline v1 @7408 -> 3 [COUNT] (from 3)
R8 base tmp0 @7407 -> 3 [COUNT] (from 3)
R8 base-shared tmp0 @7407 -> 3 [COUNT] (from 3)
R7 block @7407 -> 3 [COUNT] (from 3)
R9 swap-stmts @7409 -> 3 [COUNT] (from 3)
R12 width v1 s32->u16 @7403 -> 3 [COUNT] (from 3)
R8 temp tmp0 @7408 -> 3 [COUNT] (from 3)
.run/P36/agents/ov_SC04_011__func_80183E20/neighbours.txt
+8
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@@ -0,0 +1,8 @@
--- every @class/@stuck/@crack note in this translation unit ---
// @class: schedule
// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// @class: struct
// @stuck: none — MATCH (fn-ptr table %lo-fold via extern array of code ptrs)
/* @class: instruction-scheduling (SOLVED — natural statement order)
// @class: loose-typing
// @stuck: none — MATCH (99 ins). short* for param_2/param_3: gcc emits lh where sign is live (<<1 for signed div), lhu where truncated to short (arith result / direct copy)
.run/P36/agents/ov_SC04_011__func_80183E20/related.txt
+68
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@@ -0,0 +1,68 @@
=== lever-free bodies in ov_SC04_011 sharing a callee or global with func_80183E20 (30 found; top 6 by shared symbols) — read them for the SHAPE ===
--- func_80186940 (src/ov_SC04_011/ov_SC04_011_jr_8017D494.c:9295) shares 2: D_801EFD24 D_801EFD40 ---
void func_80186940(void *a0, s32 a1, s32 a2) {
s16 ret;
s16 a2s;
s32 msg;
a2s = a2;
D_801EFD40 |= 0x80;
ret = func_80186A20(D_801EFC48, (s16)a1);
*(u16 *)(D_801EFC48 + 0x60) = *(u16 *)(D_801EFC48 + 0x60) + ret;
if (a2s != 0) {
func_8016AA50((s32)a0, ret);
}
*(u16 *)&D_801EFD24 = 8;
if (ret != 0) {
func_80186A68();
msg = 0xBA9;
if (*(u16 *)&D_801EFD28 - *(s16 *)(D_801EFC48 + 0x60) > 0) {
msg = 0x906;
}
func_8002D4C8(msg, 0);
}
}
--- func_80183BAC (src/ov_SC04_011/ov_SC04_011_jr_8017D494.c:7265) shares 1: D_801EFD40 ---
void func_80183BAC(u8 *a0) {
u16 v = D_801EFD40;
*(s16 *)(a0 + 0x104) = -0x20;
D_801EFD40 = v | 0x40;
}
--- func_8018637C (src/ov_SC04_011/ov_SC04_011_jr_8017D494.c:9036) shares 1: D_801EFD40 ---
void func_8018637C(s32 arg0, s32 arg1)
{
func_8012A828();
D_801EFD40 |= 0x10;
}
--- func_80183BD0 (src/ov_SC04_011/ov_SC04_011_jr_8017D494.c:7274) shares 1: D_801EFD40 ---
void func_80183BD0(s32 a0) {
u16 f;
f = D_801EFD40;
*(s16 *)(a0 + 0x104) = 0;
D_801EFD40 = f & 0xFFBF;
}
--- func_801863B4 (src/ov_SC04_011/ov_SC04_011_jr_8017D494.c:9047) shares 1: D_801EFD40 ---
void func_801863B4(s32 a0) {
u16 f;
f = D_801EFD40;
*(s16 *)(a0 + 0x98) = 0;
D_801EFD40 = f & 0xFFEF;
}
--- func_80187008 (src/ov_SC04_011/ov_SC04_011_jr_8017D494.c:9658) shares 1: D_801EFD40 ---
void func_80187008(s32 arg0) {
s32 g = D_801EFD20;
func_801805F8(arg0);
if (D_801EFD40 & 4) {
func_801852BC(g);
func_801853D0(g);
func_80185648(g);
}
}
.run/P36/agents/ov_SC04_011__func_80183E20/residual.txt
+10
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@@ -0,0 +1,10 @@
src/ov_SC04_011/ov_SC04_011_jr_8017D494.c:func_80183E20: score 5 (COUNT; mine 34 ins, target 34) — not yet
register pairs (mine -> target, count): v1->v0 x1, v0->v1 x1
delete mine[10:11] target[10:10]
10 andi v1,a1,0xff7f | --
replace mine[12:13] target[11:13]
12 sll v0,v0,0x10 | lh v1,118(a0)
13 -- | andi v0,a1,0xff7f
replace mine[14:16] target[14:16]
14 sh v1,0(at) | sh v0,0(at)
15 bgez v0,69d4 <func_80183E20+0x48> | bgez v1,69d4 <func_80183E20+0x48>
.run/P36/agents/ov_SC04_011__func_80183E20/sites.txt
+1
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@@ -0,0 +1 @@
NEEDED barrier memory line 7516
.run/P36/agents/ov_SC04_011__func_80183E20/tu.txt
+2
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@@ -0,0 +1,2 @@
src/ov_SC04_011/ov_SC04_011_jr_8017D494.c
func_80183E20
.run/P36/agents/ov_SC04_011__func_80185214/body_free.c
+24
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@@ -0,0 +1,24 @@
void func_80185214(s32 a0)
{
extern s32 D_801EFC48;
extern u8 D_80194724[];
extern void func_80185A18(s32 idx, s32 val);
s32 s0;
s32 s1;
s32 s2;
s32 c;
s2 = a0;
s0 = *(s32 *)(D_801EFC48 + 0xCC);
s1 = s0 + 0x28;
do {
c = *(u8 *)(s0 + 6);
if (c < 0x15 && D_80194724[c] == 0) {
func_80185A18(c, (s16)(*(u16 *)(s0 + 2) + s2));
}
if (*(s16 *)(s0 + 6) & 0x8000) {
break;
}
s0 += 8;
} while (s0 < s1);
}
.run/P36/agents/ov_SC04_011__func_80185214/body_tree.c
+24
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@@ -0,0 +1,24 @@
void func_80185214(s32 a0)
{
extern s32 D_801EFC48;
extern u8 D_80194724[];
extern void func_80185A18(s32 idx, s32 val);
register s32 s0 __asm__("$16"); // !FAKE: pin $16 — NEEDED DIFFERS (P36 rung B t3_tus1)
s32 s1;
s32 s2;
s32 c;
s2 = a0;
s0 = *(s32 *)(D_801EFC48 + 0xCC);
s1 = s0 + 0x28;
do {
c = *(u8 *)(s0 + 6);
if (c < 0x15 && D_80194724[c] == 0) {
func_80185A18(c, (s16)(*(u16 *)(s0 + 2) + s2));
}
if (*(s16 *)(s0 + 6) & 0x8000) {
break;
}
s0 += 8;
} while (s0 < s1);
}
.run/P36/agents/ov_SC04_011__func_80185214/history.txt
+14
View File
@@ -0,0 +1,14 @@
s5: verdict NO-MATCH start 6 best 6 compiles 161 path
best-scoring single candidates of the last trace (move -> score [residual class]):
R8 temp tmp0 @8361 -> 6 [COUNT] (from 6)
R7 block @8362 -> 6 [COUNT] (from 6)
R10 param-alias s2->a0 @8360 -> 6 [COUNT] (from 6)
R4 decl-move s0 2->0 -> 6 [COUNT] (from 6)
R6 inline s2 @8360 -> 6 [COUNT] (from 6)
R8 base tmp0 @8361 -> 6 [COUNT] (from 6)
R7 do-while @8362 -> 6 [COUNT] (from 6)
R9 swap-stmts @8360 -> 6 [COUNT] (from 6)
R10 param-copy a0 @8359 -> 6 [COUNT] (from 6)
R4 decl-move s0 2->1 -> 6 [COUNT] (from 6)
R8 temp tmp0 @8364 -> 6 [COUNT] (from 6)
R7 block @8361 -> 6 [COUNT] (from 6)
.run/P36/agents/ov_SC04_011__func_80185214/neighbours.txt
+8
View File
@@ -0,0 +1,8 @@
--- every @class/@stuck/@crack note in this translation unit ---
// @class: schedule
// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// @class: struct
// @stuck: none — MATCH (fn-ptr table %lo-fold via extern array of code ptrs)
/* @class: instruction-scheduling (SOLVED — natural statement order)
// @class: loose-typing
// @stuck: none — MATCH (99 ins). short* for param_2/param_3: gcc emits lh where sign is live (<<1 for signed div), lhu where truncated to short (arith result / direct copy)
.run/P36/agents/ov_SC04_011__func_80185214/related.txt
+93
View File
@@ -0,0 +1,93 @@
=== lever-free bodies in ov_SC04_011 sharing a callee or global with func_80185214 (20 found; top 6 by shared symbols) — read them for the SHAPE ===
--- func_80185FAC (src/ov_SC04_011/ov_SC04_011_jr_8017D494.c:8866) shares 1: D_80194724 ---
void func_80185FAC(void) {
s32 i;
for (i = 0; i < 0x15; i++) {
if (D_80194724[i] == 0) {
*(u8 *)(((s32 *)&D_801EFC4C)[i] + 0x10A) = 0;
}
}
}
--- func_8018681C (src/ov_SC04_011/ov_SC04_011_jr_8017D494.c:9242) shares 1: D_80194724 ---
void func_8018681C(s32 a0, void *a1) {
s32 i;
for (i = a0 + 1; i < 0x15; i++) {
if (D_80194724[i] == 0) {
func_801868A0((void *)aFC4C[i], a1);
}
}
}
--- func_80183C74 (src/ov_SC04_011/ov_SC04_011_jr_8017D494.c:7328) shares 1: D_801EFC48 ---
void func_80183C74(s32 a0, u16 a1)
{
s32 id;
s32 v;
v = func_8012B6D4((s16 *)(a0 + 4), (s16 *)&D_80126B5C);
id = v & 0xFFF;
if (id < 0x800) {
id = (id < 0x221) ? id : 0x220;
} else {
if (id < 0xDE0) id = 0xDE0;
}
func_80185960(id, (u16 *)(*(s32 *)(D_801EFC48 + 0x20) + 0x12), a1);
}
--- func_80184840 (src/ov_SC04_011/ov_SC04_011_jr_8017D494.c:7850) shares 1: D_801EFC48 ---
void func_80184840(void) {
extern s32 D_801EFC48;
extern s32 D_801EFC4C;
extern s32 D_801EFC54;
s32 p;
s32 obj;
p = D_801EFC4C;
*(s16 *)(p + 0x76) = 0x240;
*(s16 *)(D_801EFC48 + 0x76) = 0x1000;
p = D_801EFC54;
obj = *(s32 *)(p + 0x20);
*(s16 *)(obj + 0x1C) = 0x1000;
*(s16 *)(obj + 0x1A) = 0x1000;
*(s16 *)(obj + 0x18) = 0x1000;
}
--- func_80185C5C (src/ov_SC04_011/ov_SC04_011_jr_8017D494.c:8754) shares 1: D_801EFC48 ---
void func_80185C5C(u16 id)
{
extern s32 D_801EFC48;
extern s32 D_801EFC4C[];
s32 obj;
s32 q;
obj = D_801EFC4C[*(u8 *)(id * 8 + *(s32 *)(D_801EFC48 + 0xCC) + 6)];
if (obj != 0) {
*(u16 *)(obj + 0xF6) = *(u16 *)(obj + 0xF6) + *(u16 *)(obj + 0xFA);
q = func_8004787C(*(s16 *)(obj + 0xF6)) / 22;
*(s16 *)(obj + 0xF4) = q;
*(s16 *)(obj + 0xE8) = *(u16 *)(obj + 0xF8) + q;
}
}
--- func_80185B04 (src/ov_SC04_011/ov_SC04_011_jr_8017D494.c:8686) shares 1: D_801EFC48 ---
void func_80185B04(u16 a0, u16 a1)
{
extern s32 D_801EFC48;
extern s32 D_801EFC4C[];
s32 obj;
u16 t;
obj = D_801EFC4C[*(u8 *)(a0 * 8 + *(s32 *)(D_801EFC48 + 0xCC) + 6)];
if (obj != 0) {
t = *(u16 *)(obj + 0xE4);
*(u16 *)(obj + 0xEC) = 0;
*(u16 *)(obj + 0xEE) = 0;
*(u16 *)(obj + 0xF2) = a1;
*(u16 *)(obj + 0xF0) = t;
}
}
.run/P36/agents/ov_SC04_011__func_80185214/residual.txt
+12
View File
@@ -0,0 +1,12 @@
src/ov_SC04_011/ov_SC04_011_jr_8017D494.c:func_80185214: score 6 (COUNT; mine 43 ins, target 42) — not yet
register pairs (mine -> target, count): v0->s0 x1
replace mine[7:8] target[7:8]
7 lw v0,204(v0) | lw s0,204(v0)
replace mine[9:12] target[9:11]
9 addiu s0,v0,6 | addiu s1,s0,40
10 addiu s1,v0,46 | lbu a0,6(s0)
11 lbu a0,0(s0) | --
replace mine[22:23] target[21:22]
22 lhu a1,-4(s0) | lhu a1,2(s0)
replace mine[28:29] target[27:28]
28 lh v0,0(s0) | lh v0,6(s0)
.run/P36/agents/ov_SC04_011__func_80185214/sites.txt
+3
View File
@@ -0,0 +1,3 @@
NEEDED pin $16 line 8459
REMOVED pin $17 line 8460
REMOVED pin $18 line 8461
.run/P36/agents/ov_SC04_011__func_80185214/tu.txt
+2
View File
@@ -0,0 +1,2 @@
src/ov_SC04_011/ov_SC04_011_jr_8017D494.c
func_80185214
.run/P36/agents/ov_SC04_011__func_80186020/body_free.c
+40
View File
@@ -0,0 +1,40 @@
void func_80186020(void *a0) {
s32 p;
u16 x;
/* $v0 pin (cookbook "register pin" lever): without it sched1's birthing boost
hands $v0 to the wrong temp and the two lhu's swap registers (residual 12). */
u16 y;
if ((D_801EFD40 & 2) != 0) {
if ((s16)D_801EFD48 >= 0x120) {
*(s16 *)&D_801EFD4C = -0x60;
} else if ((s16)D_801EFD48 < -0x5F) {
*(s16 *)&D_801EFD4C = 0x60;
}
x = D_801EFD48;
y = D_801EFD4C;
p = *(s32 *)((s32)a0 + 0x20);
x = x + y;
y = D_801EFD44;
D_801EFD48 = x;
y = y + x;
*(u16 *)(p + 0x10) = y;
} else {
if ((D_801EFD40 & 1) != 0) {
if ((s16)D_801EFD48 >= 0x120) {
return;
}
y = (s16)D_801EFD48 + 0x60;
} else {
if ((s16)D_801EFD48 < -0x5F) {
return;
}
y = (s16)D_801EFD48 - 0x60;
}
x = D_801EFD44;
p = *(s32 *)((s32)a0 + 0x20);
D_801EFD48 = y;
x = x + y;
*(u16 *)(p + 0x10) = x;
}
}
.run/P36/agents/ov_SC04_011__func_80186020/body_tree.c
+40
View File
@@ -0,0 +1,40 @@
void func_80186020(void *a0) {
s32 p;
u16 x;
/* $v0 pin (cookbook "register pin" lever): without it sched1's birthing boost
hands $v0 to the wrong temp and the two lhu's swap registers (residual 12). */
register u16 y __asm__("$2"); // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B t3_tus1)
if ((D_801EFD40 & 2) != 0) {
if ((s16)D_801EFD48 >= 0x120) {
*(s16 *)&D_801EFD4C = -0x60;
} else if ((s16)D_801EFD48 < -0x5F) {
*(s16 *)&D_801EFD4C = 0x60;
}
x = D_801EFD48;
y = D_801EFD4C;
p = *(s32 *)((s32)a0 + 0x20);
x = x + y;
y = D_801EFD44;
D_801EFD48 = x;
y = y + x;
*(u16 *)(p + 0x10) = y;
} else {
if ((D_801EFD40 & 1) != 0) {
if ((s16)D_801EFD48 >= 0x120) {
return;
}
y = (s16)D_801EFD48 + 0x60;
} else {
if ((s16)D_801EFD48 < -0x5F) {
return;
}
y = (s16)D_801EFD48 - 0x60;
}
x = D_801EFD44;
p = *(s32 *)((s32)a0 + 0x20);
D_801EFD48 = y;
x = x + y;
*(u16 *)(p + 0x10) = x;
}
}
.run/P36/agents/ov_SC04_011__func_80186020/history.txt
+14
View File
@@ -0,0 +1,14 @@
s5: verdict NO-MATCH start 22 best 7 compiles 188 path R18 bystander @8914->8918 + R6 inline y @8918
best-scoring single candidates of the last trace (move -> score [residual class]):
R6 inline y @8918 -> 7 [COUNT] (from 10)
R18 bystander @8914->8919 -> 7 [COUNT] (from 10)
R18 bystander @8914->8920 -> 7 [COUNT] (from 10)
R9 swap-stmts @8917 -> 7 [COUNT] (from 12)
R18 bystander @8915->8920 -> 8 [COUNT] (from 10)
R18 bystander @8914->8918 -> 10 [COUNT] (from 22)
R8 hoist tmp0 @8927 -> 10 [COUNT] (from 10)
R18 bystander @8915->8918 -> 10 [COUNT] (from 10)
R7 block @8927 -> 10 [COUNT] (from 10)
R5 swap + @8916 -> 10 [COUNT] (from 10)
R12 width x u16->s16 @8903 -> 10 [COUNT] (from 10)
R6 inline y @8914 -> 10 [COUNT] (from 10)
.run/P36/agents/ov_SC04_011__func_80186020/neighbours.txt
+8
View File
@@ -0,0 +1,8 @@
--- every @class/@stuck/@crack note in this translation unit ---
// @class: schedule
// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// @class: struct
// @stuck: none — MATCH (fn-ptr table %lo-fold via extern array of code ptrs)
/* @class: instruction-scheduling (SOLVED — natural statement order)
// @class: loose-typing
// @stuck: none — MATCH (99 ins). short* for param_2/param_3: gcc emits lh where sign is live (<<1 for signed div), lhu where truncated to short (arith result / direct copy)
.run/P36/agents/ov_SC04_011__func_80186020/related.txt
+58
View File
@@ -0,0 +1,58 @@
=== lever-free bodies in ov_SC04_011 sharing a callee or global with func_80186020 (31 found; top 6 by shared symbols) — read them for the SHAPE ===
--- func_80185FF4 (src/ov_SC04_011/ov_SC04_011_jr_8017D494.c:8878) shares 3: D_801EFD44 D_801EFD48 D_801EFD4C ---
void func_80185FF4(void *a0)
{
extern u16 D_801EFD44;
extern u16 D_801EFD48;
extern u16 D_801EFD4C;
s32 obj;
obj = *(s32 *)((s32)a0 + 0x20);
D_801EFD48 = 0;
D_801EFD44 = *(u16 *)(obj + 0x10);
D_801EFD4C = 0x60;
}
--- func_80183BAC (src/ov_SC04_011/ov_SC04_011_jr_8017D494.c:7265) shares 1: D_801EFD40 ---
void func_80183BAC(u8 *a0) {
u16 v = D_801EFD40;
*(s16 *)(a0 + 0x104) = -0x20;
D_801EFD40 = v | 0x40;
}
--- func_8018637C (src/ov_SC04_011/ov_SC04_011_jr_8017D494.c:9036) shares 1: D_801EFD40 ---
void func_8018637C(s32 arg0, s32 arg1)
{
func_8012A828();
D_801EFD40 |= 0x10;
}
--- func_80183BD0 (src/ov_SC04_011/ov_SC04_011_jr_8017D494.c:7274) shares 1: D_801EFD40 ---
void func_80183BD0(s32 a0) {
u16 f;
f = D_801EFD40;
*(s16 *)(a0 + 0x104) = 0;
D_801EFD40 = f & 0xFFBF;
}
--- func_801863B4 (src/ov_SC04_011/ov_SC04_011_jr_8017D494.c:9047) shares 1: D_801EFD40 ---
void func_801863B4(s32 a0) {
u16 f;
f = D_801EFD40;
*(s16 *)(a0 + 0x98) = 0;
D_801EFD40 = f & 0xFFEF;
}
--- func_80187008 (src/ov_SC04_011/ov_SC04_011_jr_8017D494.c:9658) shares 1: D_801EFD40 ---
void func_80187008(s32 arg0) {
s32 g = D_801EFD20;
func_801805F8(arg0);
if (D_801EFD40 & 4) {
func_801852BC(g);
func_801853D0(g);
func_80185648(g);
}
}
.run/P36/agents/ov_SC04_011__func_80186020/residual.txt
+31
View File
@@ -0,0 +1,31 @@
src/ov_SC04_011/ov_SC04_011_jr_8017D494.c:func_80186020: score 22 (COUNT; mine 60 ins, target 60) — not yet
register pairs (mine -> target, count): v0->v1 x9, v1->v0 x8
replace mine[18:22] target[18:22]
18 lui v0,0x0 | lui v1,0x0
19 lhu v0,0(v0) | lhu v1,0(v1)
20 lui v1,0x0 | lui v0,0x0
21 lhu v1,0(v1) | lhu v0,0(v0)
insert mine[23:23] target[23:28]
23 -- | addu v1,v1,v0
24 -- | lui v0,0x0
25 -- | lhu v0,0(v0)
26 -- | lui at,0x0
27 -- | sh v1,0(at)
delete mine[24:29] target[29:29]
24 lui v1,0x0 | --
25 lhu v1,0(v1) | --
26 lui at,0x0 | --
27 sh v0,0(at) | --
28 addu v1,v1,v0 | --
replace mine[30:31] target[30:31]
30 sh v1,16(a0) | sh v0,16(a0)
replace mine[40:41] target[40:41]
40 addiu v1,v1,96 | addiu v0,v1,96
replace mine[49:52] target[49:52]
49 addiu v1,v1,-96 | addiu v0,v1,-96
50 lui v0,0x0 | lui v1,0x0
51 lhu v0,0(v0) | lhu v1,0(v1)
replace mine[54:57] target[54:57]
54 sh v1,0(at) | sh v0,0(at)
55 addu v0,v0,v1 | addu v1,v1,v0
56 sh v0,16(a0) | sh v1,16(a0)
.run/P36/agents/ov_SC04_011__func_80186020/sites.txt
+1
View File
@@ -0,0 +1 @@
NEEDED pin $2 line 9093
.run/P36/agents/ov_SC04_011__func_80186020/tu.txt
+2
View File
@@ -0,0 +1,2 @@
src/ov_SC04_011/ov_SC04_011_jr_8017D494.c
func_80186020