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docs(phase-32): T4b (1) ledger — func_800391D4 unpinned (config/wave_exclude.txt 6 kept / 1 dropped by exclude_audit), backlog re-rendered (15 open), the Fable draft + report + verdict kept (R20)
This commit is contained in:
Drew T
@@ -308,3 +308,4 @@ unsloth_compiled_cache/
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!/.run/P32/t5x/reports/
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/.run/P32/t5x/reports/*
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!/.run/P32/t5x/reports/*.md
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!/.run/P32/t5x/verdicts.jsonl
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@@ -0,0 +1,62 @@
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/* func_800391D4 (main / src/800_c.c, 75 ins) -- MATCH in match_one AND rtu_match (real TU), Fable T5x 2026-09-05.
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* Levers, all measured (see .run/P32/t5x/reports/func_800391D4.md):
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* - `register s32 i __asm__("$7")`: a hard reg is not a biv (loop.c:3572), so D_80073140[i] is never a giv ->
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* the target's per-iteration sll/lui/addu/lw stays (S79).
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* - `extern s32 D_80073140[][1]` + `[i][0]`: load-bearing spelling of the table access (S79; the TU now carries it).
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* - `a1v = arg1;` BEFORE `off = 0;`: the s16 parameter's sign-extend becomes preheader SOURCE code emitted before
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* off's init. Left implicit, the extend is an in-loop invariant that move_movables splices in front of
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* NOTE_INSN_LOOP_BEG, i.e. AFTER `off = 0` (loop.c:1652/1708) -- the S79 closeness-3 residual.
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* - NINE `__asm__("")` pads: insn_count knife-edge. move_movables hoists the D_800C6DD0 address iff
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* threshold(58) * savings(1) * lifetime(1) >= insn_count (loop.c:1631). The target does NOT hoist it, so the
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* loop must count >= 59 real insns; moving the extend out of the body cost 2, so 7 pads -> 9.
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*/
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void func_800391D4(s32 arg0, s16 arg1, s16 arg2) {
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extern u8 D_800C6DD0[];
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extern u8 D_800C6DD4[];
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extern s32 D_80073140[][1];
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extern s32 D_800C7D20;
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extern s32 D_800A2B98;
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extern u8 *D_800762B0;
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extern u8 D_800762B4[];
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u8 *base;
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u8 *entry;
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register s32 i __asm__("$7");
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s32 off;
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s32 mask;
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s32 a1v;
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i = 0;
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base = arg0 + arg2 * 0x1A;
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a1v = arg1;
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off = 0;
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do {
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__asm__("");
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__asm__("");
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__asm__("");
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__asm__("");
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__asm__("");
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__asm__("");
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__asm__("");
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__asm__("");
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__asm__("");
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if (*(base + i + 0x23) != 0 && *(s16 *)&D_800C6DD4[off] == a1v) {
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entry = &D_800C6DD0[(s16)i * 0x60];
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if (entry[0x5A] != 0) {
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s32 off2;
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u8 *base2;
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off2 = *(s16 *)(entry + 6) * 0x1A;
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base2 = *(s32 *)(entry + 0x50);
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*(base2 + off2 + (s16)i + 0x23) = 0;
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entry[0x5A] = 0;
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}
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mask = D_80073140[i][0];
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D_800C7D20 &= ~mask;
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D_800A2B98 |= mask;
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D_800762B0[i] = 2;
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D_800762B4[i] = 0;
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}
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i++;
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off += 0x60;
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} while (i < 0x10);
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}
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@@ -0,0 +1,62 @@
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# func_800391D4 (main, src/800_c.c, 75 ins) — MATCH (Fable, T5x, 2026-09-05)
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**Verdict:** `MATCH (75 ins)` from `tools/match_one.py` AND from `tools/rtu_match.py` in the real TU
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(`--tu src/800_c.c`, block-scope `extern s32 D_80073140[][1]` — the TU carries that spelling now).
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Draft: `.run/P32/t5x/fable/func_800391D4.c`. Seed: `.run/S79w/sonnet/func_800391D4.c` (closeness 3).
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## The residual (S79, closeness 3) and what it actually was
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idx 9–11: the draft emitted `move $t0,$zero` (`off = 0`) BEFORE arg1's `sll/sra` sign-extend; the target has it AFTER.
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RTL read (`dumps_d0/d0.i.loop`, private copy of cc1_dumps at `.run/P32/t5x/work/func_800391D4/dump.sh`):
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```
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Insn 71: regno 99 (life 2), savings 2 moved to 196
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Insn 72: regno 98 (life 1), cond forces 71 savings 1 moved to 197
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Insn 86: regno 106 (life 1), move-insn savings 1 not desirable <- lui/addiu D_800C6DD0 stays in-loop
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Loop from 38 to 189: 59 real insns.
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```
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The implicit promotion of the `s16 arg1` parameter (compare `lh == arg1`) is an in-loop invariant pair; `move_movables`
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splices movables with `emit_insn_before (.., loop_start)` (loop.c:1652/1708), i.e. immediately before
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`NOTE_INSN_LOOP_BEG` and therefore AFTER every preheader source insn including insn 36 (`off = 0`). sched1 cannot
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rescue it: the `.sched` dump gives every preheader insn priority 1, the backward list scheduler breaks ties by LUID,
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so RTL order is emitted verbatim. Hence the order is fixed by WHERE the extend is born, not by scheduling.
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## The lever that closed it: explicit promotion + insn_count re-padding
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1. `s32 a1v; a1v = arg1;` written BEFORE `off = 0;`, compare against `a1v`. The sign-extend is now preheader SOURCE
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code and precedes `off = 0` in RTL order (T1 of NOTES.md). Alone this measures 18 — the S83 note recorded that
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number and stopped; the dump shows why it looked worse:
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```
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t1: Loop from 41 to 190: 57 real insns.
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Insn 87: regno 106 (life 1), move-insn savings 1 moved to 198 <- D_800C6DD0 la HOISTED (+2 preheader, idx 12-13 lui/addiu $t2)
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```
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Removing the two extend insns from the body dropped `insn_count` 59→57, so the desirability test
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`threshold * savings * lifetime >= insn_count` (loop.c:1631; threshold = 2*(1+28) = 58, no call) flipped from
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58 < 59 (not desirable) to 58 ≥ 57 (moved). The whole 18 was that one hoist plus its register cascade.
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2. Restore the knife-edge: the S79 draft's 7 `__asm__("")` pads (each counts as one real insn for `insn_count`, emits
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nothing) become 9. Result:
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```
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t1b: Loop from 41 to 194: 59 real insns.
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Insn 91: regno 106 (life 1), move-insn savings 1 not desirable
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preheader tail: sll $5,$5,16 / sra $5,$5,16 / move $8,$0 <- target order
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```
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match_one: `MATCH (75 ins)`; rtu_match (real TU): `MATCH (75 ins)`.
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## Measured inert / refuted this session
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- E1 `off = i * 0x60;` at the top of the body (make `off` a reduced giv so its init comes from `strength_reduce`, which
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runs AFTER `move_movables` — loop.c:966 vs :975, giv init at :3878 `emit_iv_add_mult(.., loop_start)`): 77 ins /
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63 mismatched. The `$7` pin makes `i` a hard register, which `strength_reduce` skips as a biv (loop.c:3572
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`REGNO (dest_reg) < FIRST_PSEUDO_REGISTER`), so no biv → no giv → `off` is plainly recomputed each iteration.
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The giv-init route and the pin that kills the `D_80073140[i]` giv are mutually exclusive; the mechanism is right but
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unreachable from this shape.
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- The S83 verdict "T1 = 18, worse" was a confound, not a measurement of the lever: the promotion itself was correct and
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the regression was the hidden `insn_count` side-effect. Generalizable rule: **any edit that moves insns out of a
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loop body must be re-measured with the pad count re-tuned**, because the S79-class pads encode an `insn_count`
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knife-edge (58 vs 59 here) and every body insn removed silently re-arms `move_movables`.
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## Symbols (law 1c) — checked against the target's own relocation lines
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D_800C6DD4, D_800C6DD0, D_80073140, D_800C7D20, D_800A2B98, D_800762B0, D_800762B4 — all seven `%hi/%lo` in
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`asm/nonmatchings/800_c/func_800391D4.s`; no `jal`. Literals 0x23, 0x60, 0x5A, 6, 0x50, 0x1A, 2, 0x10 from the .s.
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## Files
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- draft: `.run/P32/t5x/fable/func_800391D4.c`
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- scratch: `.run/P32/t5x/work/func_800391D4/{d0,d1,t1,t1b}.c`, `dumps_{d0,d1,t1,t1b}/` (`.loop`, `.sched`, `.greg` ...), `dump.sh`
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- rtu: `.run/P32/t5x/rtu/func_800391D4/`
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@@ -0,0 +1 @@
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{"fn": "func_800391D4", "binary": "main", "arm": "fable", "status": "MATCH", "closeness": 0, "compiles": true, "draft_path": ".run/P32/t5x/fable/func_800391D4.c", "note": "explicit promotion `a1v = arg1` before `off = 0` (the extend becomes preheader source) + insn_count knife-edge re-padded 7 -> 9 __asm__(\"\") so loop.c:1631 keeps the D_800C6DD0 address un-hoisted (threshold 58 vs insn_count 59); coordinator rtu MATCH 75/75; gate_main BANKED 143dbb89", "session": "491895ad"}
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@@ -1,11 +1,10 @@
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# regenerated by tools/exclude_audit.py from config/wave_exclude.txt
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# 7 still-valid of 8; 1 dropped as stale (banked / linked / blocker-since-fixed).
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# 6 still-valid of 7; 1 dropped as stale (banked / linked / blocker-since-fixed).
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# An exclude list records what the TOOLING could not do — regenerate it as
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# part of every tool fix, or it becomes a list of work you decided not to do.
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ov_SC03_105:func_801834A4 # WALL: loop.c movable ordering, closeness 6 (S71) | T4 S83: re-probed in the real TU (3 stored variants) DIFF 6 — CANDIDATE, unchanged
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ov_SC06_022:func_8017DF28 # WALL: expand_block_move copy_addr_to_reg pseudo cse-reused for both later &mtx args (cse_expr.md [A23-2]/§H) — the addiu $s2,sp,0x10 sits in the jal's delay slot vs the target's bnez slot; closeness 2 on five RTL-verified attempts (S71/S79); permuter_ils 8x150s (S80) reported 1 but its waypoint REPLACED the addiu with `sw zero,48(sp)` — a divergent rewrite, not a closer body: closeness stays 2 | T4 S83: re-probed in the real TU DIFF 2 (addiu/nop slot swap idx 25/28) — CANDIDATE, unchanged; citation [A23-2] current
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main:func_80032A74 # WALL: candidate: 422/422, frame/offsets/27 symbols exact, sole residual idx 244 `lh` vs `lhu` — extendhisi2 is a force_not_mem EXPAND (an orphan frame slot is minted only at an lh), the target's 8 extra frame bytes are §172 producer 3 (caller-save area, reload1.c:1445); ~200 byte-probes incl. a 100-variant retyping sweep (S79 Opus) + permuter_ils 8x150s null (S80); closeness 1 | T4 S83: the S79w draft was a CC1 FAIL only for PLUMBING (7 header typedefs + 4 decl spellings); synced copy .run/P32/t4/drafts/func_80032A74_tuclean.c re-run in the real TU DIFF 1 (idx 244 lh vs lhu) — CANDIDATE, unchanged
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main:func_80020DA4 # WALL: candidate: 100/100, phantom 16-byte frame reproduced (address-taken frame_pad[3]); residual = mflo destination $t0 vs $a2 (REGALLOC-PERM), pinning regresses to 79; 5 attempts 51→20→14→8→2 (S7x/S79) + permuter_ils 8x150s null (S80); closeness 2 | T4 S83: re-probed in the real TU DIFF 2 — CANDIDATE, unchanged
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main:func_800391D4 # WALL: candidate: 75/75, residual = a 3-insn SCHEDULE-REORDER (off=0 vs arg1's sll/sra pair) — move_movables splices hoisted invariants after any pre-existing preheader flow code (loop.c), so off's init cannot follow arg1's hoisted sign-extend from C; 4 prior attempts + S79 Sonnet (64→3: i=$7 pin kills combine_givs, D_80073140[][1] decl, 7 asm("") insn_count pads) + permuter_ils 8x150s null (S80); closeness 3 | T4 S83: CC1 FAIL was the draft's load-bearing `D_80073140[][1]` vs the TU's `[]`; sandbox TU with [][1] externs: DIFF 3 (idx 9-11) — CANDIDATE, unchanged; the TU-compatible spellings all regress to 65
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main:func_80011380 # WALL: §474 PROVED C-level floor (closeness 6) — fold-const.c:882 split_tree merges MULT(MULT(i,2),2); the two escapes each cost one instruction (stupid.c:497 adjacency / expand_decl use-brackets); §388 -O0 colouring oracle. Pinned S79 #8. | T4 S83: re-probed in the real TU (rtu --o0) DIFF 6 — PROVED (§474), unchanged
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main:func_80039DEC # WALL: candidate: 74/74 exact length; the $a3<->$t0 swap of the two K&R raw-preserve parameter copies is fixed by ARGUMENT POSITION in gcc-2.7.2's narrow-parameter promotion (2nd param -> $a3, 3rd -> $t0) before the global allocator runs — every pin on the raw-preserve values regresses to 60-75; 3 attempts corroborate (S7x/S79 Sonnet 9) + permuter_ils 8x150s 9 -> 2 (S80); closeness 2 | T4 S83: CC1 FAIL was the TU's prototype (800_c.c:3496) vs the K&R definition; sandbox TU with the no-proto decl: permuter draft DIFF 2 (idx 0/56 t1 vs a3) — CANDIDATE, unchanged
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+11
-12
@@ -2,7 +2,7 @@
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> Generated by `tools/backlog.py render` from `.run/backlog.jsonl`. These are functions the Phase-21 automation got **close** on but did NOT byte-match. The whole-binary byte-gate is the sole arbiter (G3/P9): **byte-matches bank and are NOT listed here** — only genuine near-misses/blockers are. Ranked by hand-session priority: **reach** (×N propagation leverage) → **closeness** (match_one mismatch count, lower = closer) → **size**. Each row's `best_draft` is the closest C the machine reached — resume from there.
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**Open near-misses:** 16 · by status {'near': 15, 'failed': 1} · by class {'WALL-CANDIDATE': 6, 'REGALLOC-PERM': 1, 'WALL-PROVED': 1, 'SCHED': 4, 'REGALLOC': 1, 'ALIAS': 1, 'FRAME': 1, None: 1}
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**Open near-misses:** 15 · by status {'near': 14, 'failed': 1} · by class {'WALL-CANDIDATE': 5, 'REGALLOC-PERM': 1, 'WALL-PROVED': 1, 'SCHED': 4, 'REGALLOC': 1, 'ALIAS': 1, 'FRAME': 1, None: 1}
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| # | addr | reach | class | nins | status | closeness | where it stuck | best draft |
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|--:|------|------:|-------|-----:|--------|----------:|----------------|------------|
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@@ -11,14 +11,13 @@
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| 3 | func_80020DA4 | None | WALL-CANDIDATE | 100 | near | 2 | WALL candidate CONFIRMED (S83 rtu DIFF 2): 100/100, phantom 16-byte frame reproduced (address-taken frame_pad[3]); residual = mflo destination $t0 vs $a2 (REGALLOC-PERM), pinning regresses to 79; 5 attempts 51->20->14->8->2 + permuter_ils null (S80) | `.run/S79w/sonnet/func_80020DA4.c` |
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| 4 | func_8017DF28 | None | WALL-CANDIDATE | 119 | near | 2 | WALL candidate CONFIRMED (S83 rtu DIFF 2): expand_block_move copy_addr_to_reg pseudo cse-reused for both later &mtx args (gcc-2.7.2-map cse_expr.md [A23-2]/§H); 119/119; the addiu $s2,sp,0x10 sits in the jal delay slot vs the target bnez slot; five RTL-verified attempts (S71/S79); permuter_ils (S80) "1" was a divergent rewrite (R63). Citation current ([A23-2] present in cse_expr.md) | `.run/S79w/sonnet/func_8017DF28.c` |
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| 5 | func_800CD674 | None | REGALLOC-PERM | 174 | near | 2 | $a3<->$t1 across two masked prim pointers (one shared local can be only one; splitting = +1 pseudo displacing two hoisted constants, 31); SPRT-with-tpage family, §364 mirror (non-struct field stores). Inert: pin order (8 perms), assignment placement (6), volatile index, p+=0x18 spellings, u8* cursor, every pin subset. NEXT: permuter_ils on the pinned seed (§494 recipe) | `.run/P32/t3/opus/func_800CD674.c` |
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| 6 | func_800391D4 | None | WALL-CANDIDATE | 75 | near | 3 | WALL candidate CONFIRMED (S83 sandbox-TU rtu DIFF 3: idx 9-11 `move t0,zero` before vs after arg1 sll/sra): 75/75, a 3-insn SCHEDULE-REORDER — move_movables splices hoisted invariants after any pre-existing preheader flow code (loop.c 2.7.2:1529, map loop.md L4), so off init cannot follow arg1 hoisted sign-extend from C; 4 prior attempts + S79 Sonnet 64->3 + permuter_ils null (S80). Banking would need the TU externs -> [][1] (whole-EXE sha decides) — only worth it at closeness 0 | `.run/S79w/sonnet/func_800391D4.c` |
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| 7 | func_801834A4 | None | WALL-CANDIDATE | 106 | near | 6 | WALL candidate: loop.c movable ordering, closeness 6 (S71); re-probed S83 in the real TU: DIFF 6 for all three stored variants (unchanged) | `.run/S71_gate14/ov_SC03_105-cn-cast-rc-sd/func_801834A4.c` |
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| 8 | func_80011380 | None | WALL-PROVED | 192 | near | 6 | §474 PROVED C-level floor (boot -O0): fold-const.c:882 split_tree merges MULT(MULT(i,2),2); the two escapes each cost one instruction (stupid.c:497 adjacency / expand_decl use-brackets); §388 -O0 colouring oracle. Pinned S79 #8; re-probed S83 in the real TU: DIFF 6 (unchanged) | `.run/m3/opus/func_80011380.c` |
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| 9 | func_800CD92C | None | SCHED | 247 | near | 15 | map §S7 prologue WEAVE: the {sw,lui,ori} groups for 0xE100008D/8F land after the 9-insn li block instead of before — the §17 pins reproduce the ALLOCATION but the hoist happens in sched2. Same SPRT family as func_800CD674 (§364 mirror levers applied) | `.run/P32/t3/opus/func_800CD92C.c` |
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| 10 | func_80039308 | None | REGALLOC | 518 | near | 17 | sched2 + cross-block regalloc: preheader 49/50 swap, un-spellable addu $a2,$a0,$zero (every p=r form cse-propagated), a temp on $t0 vs $s7, and 11 insns of one alias fact (2nd D_80073140[j] load cannot schedule above the D_800C7D20 store from C; /s unlock costs the address allocation, net 20-24). 34->17 via s16 b4 widening copy + dead-local identity sweep (.run/P32/t3/restored/sweep_func_80039308.py) + $2 pin. permuter_ils --klass REGALLOC 2x150s: no gain | `.run/P32/t3/opus/func_80039308.c` |
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| 11 | func_800CF3E8 | None | ALIAS | 469 | near | 27 | ONE cause: the pinned-base alias basin (§500-D1) in the p5/p6 tail; blocks 1-2 byte-exact (idx 0-361). 54->27 via blk2 constant birth order + birthing-boost local w60 + §194-A fence relocation. Inert: all 9 pins load-bearing (+5..+1409), asm position x7, h6 hoist 32x2, tag reshape, P_TAG ADDPRIM, array p6 stores, ~92k annealed variants. Untested: an unpinned alias of p6 for the tag load alone (ONE Opus second look allowed) | `.run/P32/t3/opus/func_800CF3E8.c` |
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| 12 | func_80185810 | None | SCHED | 489 | near | 35 | [permuter] 4 emission windows (see report .run/P32/t3/reports/func_80185810__opus__*.md); exact length, rtu-clean | `.run/P32/t3/opus/func_80185810.c` |
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| 13 | func_8017DC80 | None | FRAME | 346 | near | 46 | the historic -33 LENGTH wall CLOSED (GTE macros must be REAL macros — the TU house block; the splat Handwritten tag is wrong): 346/346, exact 0x70 frame + 9 callee-saved. Residual: reload-slot frame + the la $a0 slot; cse1 unifies OT index and n<4 across func_80010A08(8) (§500-D2 zero-byte asm retire) | `.run/P32/t3/opus/func_8017DC80.c` |
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| 14 | func_800CF408 | None | SCHED | 178 | near | 49 | [permuter] 3 hunks: two prologue sched2 slots, an mlo/mhi allocno tie, a 3-insn block-2 head hoist. Two LENGTH-bearing pins found (tp $17 shared by 0xE1000087/97 = the 6th callee-saved; ob $10 fixes the $t1/$t2/$t3 rotation, 56->49). §351 family (func_8001212C -O0 / func_8017DD04 -O2 exemplars) | `.run/P32/t3/opus/func_800CF408.c` |
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| 15 | func_800CF6D0 | None | SCHED | 249 | near | 137 | sched1 rank_for_schedule last-insn-CLASS tie (every store priority 2, equal refs; QImode stores grouped, loads floated, HImode after — 5 of 6 blocks) + $t1<->$t3 local-alloc swap of the two masks. 249/249 exact length only with tpage-before-len field order (19 swept). Inert at 137: pins on tpage constants/masks, asm re-ties, volatile/memory fences, /s-denial on any store subset, *0x4000 vs <<14, p++ vs p+0x18, / swap. decomp-permuter 122 was semantically wrong (R63) | `.run/P32/t3/opus/func_800CF6D0.c` |
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| 16 | func_80062144 | None | | None | failed | | won't compile standalone (loose-typing / missing decl) | |
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| 6 | func_801834A4 | None | WALL-CANDIDATE | 106 | near | 6 | WALL candidate: loop.c movable ordering, closeness 6 (S71); re-probed S83 in the real TU: DIFF 6 for all three stored variants (unchanged) | `.run/S71_gate14/ov_SC03_105-cn-cast-rc-sd/func_801834A4.c` |
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| 7 | func_80011380 | None | WALL-PROVED | 192 | near | 6 | §474 PROVED C-level floor (boot -O0): fold-const.c:882 split_tree merges MULT(MULT(i,2),2); the two escapes each cost one instruction (stupid.c:497 adjacency / expand_decl use-brackets); §388 -O0 colouring oracle. Pinned S79 #8; re-probed S83 in the real TU: DIFF 6 (unchanged) | `.run/m3/opus/func_80011380.c` |
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| 8 | func_800CD92C | None | SCHED | 247 | near | 15 | map §S7 prologue WEAVE: the {sw,lui,ori} groups for 0xE100008D/8F land after the 9-insn li block instead of before — the §17 pins reproduce the ALLOCATION but the hoist happens in sched2. Same SPRT family as func_800CD674 (§364 mirror levers applied) | `.run/P32/t3/opus/func_800CD92C.c` |
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| 9 | func_80039308 | None | REGALLOC | 518 | near | 17 | sched2 + cross-block regalloc: preheader 49/50 swap, un-spellable addu $a2,$a0,$zero (every p=r form cse-propagated), a temp on $t0 vs $s7, and 11 insns of one alias fact (2nd D_80073140[j] load cannot schedule above the D_800C7D20 store from C; /s unlock costs the address allocation, net 20-24). 34->17 via s16 b4 widening copy + dead-local identity sweep (.run/P32/t3/restored/sweep_func_80039308.py) + $2 pin. permuter_ils --klass REGALLOC 2x150s: no gain | `.run/P32/t3/opus/func_80039308.c` |
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| 10 | func_800CF3E8 | None | ALIAS | 469 | near | 27 | ONE cause: the pinned-base alias basin (§500-D1) in the p5/p6 tail; blocks 1-2 byte-exact (idx 0-361). 54->27 via blk2 constant birth order + birthing-boost local w60 + §194-A fence relocation. Inert: all 9 pins load-bearing (+5..+1409), asm position x7, h6 hoist 32x2, tag reshape, P_TAG ADDPRIM, array p6 stores, ~92k annealed variants. Untested: an unpinned alias of p6 for the tag load alone (ONE Opus second look allowed) | `.run/P32/t3/opus/func_800CF3E8.c` |
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| 11 | func_80185810 | None | SCHED | 489 | near | 35 | [permuter] 4 emission windows (see report .run/P32/t3/reports/func_80185810__opus__*.md); exact length, rtu-clean | `.run/P32/t3/opus/func_80185810.c` |
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| 12 | func_8017DC80 | None | FRAME | 346 | near | 46 | the historic -33 LENGTH wall CLOSED (GTE macros must be REAL macros — the TU house block; the splat Handwritten tag is wrong): 346/346, exact 0x70 frame + 9 callee-saved. Residual: reload-slot frame + the la $a0 slot; cse1 unifies OT index and n<4 across func_80010A08(8) (§500-D2 zero-byte asm retire) | `.run/P32/t3/opus/func_8017DC80.c` |
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| 13 | func_800CF408 | None | SCHED | 178 | near | 49 | [permuter] 3 hunks: two prologue sched2 slots, an mlo/mhi allocno tie, a 3-insn block-2 head hoist. Two LENGTH-bearing pins found (tp $17 shared by 0xE1000087/97 = the 6th callee-saved; ob $10 fixes the $t1/$t2/$t3 rotation, 56->49). §351 family (func_8001212C -O0 / func_8017DD04 -O2 exemplars) | `.run/P32/t3/opus/func_800CF408.c` |
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| 14 | func_800CF6D0 | None | SCHED | 249 | near | 137 | sched1 rank_for_schedule last-insn-CLASS tie (every store priority 2, equal refs; QImode stores grouped, loads floated, HImode after — 5 of 6 blocks) + $t1<->$t3 local-alloc swap of the two masks. 249/249 exact length only with tpage-before-len field order (19 swept). Inert at 137: pins on tpage constants/masks, asm re-ties, volatile/memory fences, /s-denial on any store subset, *0x4000 vs <<14, p++ vs p+0x18, / swap. decomp-permuter 122 was semantically wrong (R63) | `.run/P32/t3/opus/func_800CF6D0.c` |
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| 15 | func_80062144 | None | | None | failed | | won't compile standalone (loose-typing / missing decl) | |
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Reference in New Issue
Block a user