mirror of
https://github.com/Druthulu/BFM-decomp
synced 2026-09-26 21:36:06 -04:00
feat(decomp): ox wave g0b overlays — 9 banked
Committed before the main batch: gate_main reverts on failure and would take these with it.
This commit is contained in:
Drew T
+1
-2
@@ -864,7 +864,7 @@ ov_SC02_005_ELF := $(ov_SC02_005_OUT).elf
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ov_SC02_005_MAPFILE := $(ov_SC02_005_OUT).map
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ov_SC02_005_LD_SCRIPT := $(ov_SC02_005_OUT).ld
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ov_SC02_005_SPLAT_YAML := config/splat.ov_SC02_005.yaml
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ov_SC02_005_JTBL_INTERLEAVE := --order tail.data.o,ov_SC02_005.o,ov_SC02_005_jr_8012ACE0.o,tail2.data.o,ov_SC02_005_jr_80135888.o,tail3.data.o,ov_SC02_005_jr_80135A4C.o,tail4.data.o,ov_SC02_005_jr_80135D20.o,tail5.data.o,ov_SC02_005_jr_801380E0.o,ov_SC02_005_o0c.o,tail6.data.o,ov_SC02_005_jr_8013F350.o,tail7.data.o,ov_SC02_005_jr_8013FFD8.o,tail8.data.o,ov_SC02_005_jr_80140608.o,tail9.data.o,ov_SC02_005_jr_8015444C.o,ov_SC02_005_jr_80154C24.o,ov_SC02_005_jr_801588CC.o,ov_SC02_005_jr_80159C84.o,tail10.data.o,ov_SC02_005_jr_8015A3C8.o,tail11.data.o,ov_SC02_005_jr_8015AE2C.o,tail12.data.o,ov_SC02_005_jr_8015C32C.o,tail13.data.o,ov_SC02_005_jr_8016AB6C.o,tail14.data.o,ov_SC02_005_jr_80171B4C.o,ov_SC02_005_jr_801734BC.o,tail15.data.o,ov_SC02_005_jr_801789AC.o,ov_SC02_005_jr_80178D40.o,tail16.data.o,ov_SC02_005_jr_8017A4AC.o,tail17.data.o,ov_SC02_005_jr_8017AE2C.o,tail18.data.o,ov_SC02_005_jr_8017CF90.o,tail19.data.o,ov_SC02_005_jr_80181984.o,ov_SC02_005_jr_80181D30.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve
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ov_SC02_005_JTBL_INTERLEAVE := --order tail.data.o,ov_SC02_005.o,ov_SC02_005_jr_8012ACE0.o,tail2.data.o,ov_SC02_005_jr_80135888.o,tail3.data.o,ov_SC02_005_jr_80135A4C.o,tail4.data.o,ov_SC02_005_jr_80135D20.o,tail5.data.o,ov_SC02_005_jr_801380E0.o,ov_SC02_005_o0c.o,tail6.data.o,ov_SC02_005_jr_8013F350.o,tail7.data.o,ov_SC02_005_jr_8013FFD8.o,tail8.data.o,ov_SC02_005_jr_80140608.o,tail9.data.o,ov_SC02_005_jr_8015444C.o,ov_SC02_005_jr_80154C24.o,ov_SC02_005_jr_801588CC.o,ov_SC02_005_jr_80159C84.o,tail10.data.o,ov_SC02_005_jr_8015A3C8.o,tail11.data.o,ov_SC02_005_jr_8015AE2C.o,tail12.data.o,ov_SC02_005_jr_8015C32C.o,tail13.data.o,ov_SC02_005_jr_8016AB6C.o,tail14.data.o,ov_SC02_005_jr_80171B4C.o,ov_SC02_005_jr_801734BC.o,tail15.data.o,ov_SC02_005_jr_801789AC.o,ov_SC02_005_jr_80178D40.o,tail16.data.o,ov_SC02_005_jr_8017A4AC.o,tail17.data.o,ov_SC02_005_jr_8017AE2C.o,tail18.data.o,ov_SC02_005_jr_8017CF90.o,tail19.data.o,ov_SC02_005_jr_80181984.o,ov_SC02_005_jr_80181D30.o,tail20.data.o,ov_SC02_005_jr_8018EA04.o,tail21.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve
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build/src/ov_SC02_005/ov_SC02_005.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14
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build/src/ov_SC02_005/ov_SC02_005_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0
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build/src/ov_SC02_005/ov_SC02_005_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18
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@@ -877,7 +877,6 @@ build/src/ov_SC02_005/ov_SC02_005_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (
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build/src/ov_SC02_005/ov_SC02_005_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20
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build/src/ov_SC02_005/ov_SC02_005_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20
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build/src/ov_SC02_005/ov_SC02_005_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178
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build/src/ov_SC02_005/ov_SC02_005_jr_80181D30.o: JTBL_PADS := 0 # §8e pads — one table since wave dd banked func_80183524 (P31 S60)
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build/src/ov_SC02_005/ov_SC02_005_o0c.o: JTBL_PADS := 0,4,4,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x38,+0xa8,+0x118
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ov_SC02_005_CHECK_SHA := config/check.ov_SC02_005.sha
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ov_SC02_005_SYMBOLS := config/symbols.ov_SC02_005.txt
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@@ -444,7 +444,47 @@ void func_800CFFEC(void) {
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INCLUDE_ASM("asm/md_MAIN_003/nonmatchings/md_MAIN_003", func_800D0100);
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INCLUDE_ASM("asm/md_MAIN_003/nonmatchings/md_MAIN_003", func_800D0174);
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__asm__(".text\n.align 2\n.globl func_800D0174\n.ent\tfunc_800D0174\n"
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"func_800D0174:\n.frame $sp,32,$31\n.mask 0xC0010000,-16\n.fmask 0,0\n"
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".set\tnoreorder\n"
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"addiu $sp, $sp, -32\n"
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"sw $ra, 24($sp)\n"
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"sw $fp, 20($sp)\n"
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"sw $s0, 16($sp)\n"
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"addu $fp, $sp, $zero\n"
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"lui $s0, %hi(D_800AF630)\n"
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"addiu $s0, $s0, %lo(D_800AF630)\n"
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"addiu $v0, $zero, 1\n"
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"lui $at, 1\n"
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"addu $at, $s0, $at\n"
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"sb $v0, -23583($at)\n"
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"jal func_8001C044\n"
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"nop\n"
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"jal func_80015310\n"
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"nop\n"
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"jal func_8002D858\n"
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"nop\n"
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"lui $a0, %hi(D_800D93FC)\n"
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"addiu $a0, $a0, %lo(D_800D93FC)\n"
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"jal func_800183E0\n"
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"nop\n"
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"lui $at, %hi(D_800EC894)\n"
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"sh $zero, %lo(D_800EC894)($at)\n"
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"jal func_800D1E18\n"
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"nop\n"
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"lui $at, %hi(D_800EC8B0)\n"
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"sw $v0, %lo(D_800EC8B0)($at)\n"
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"jal func_800118AC\n"
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"nop\n"
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"addu $sp, $fp, $zero\n"
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"lw $ra, 24($sp)\n"
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"lw $fp, 20($sp)\n"
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"lw $s0, 16($sp)\n"
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"addiu $sp, $sp, 32\n"
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"jr $ra\n"
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"nop\n"
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".set\treorder\n.end\tfunc_800D0174\n");
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INCLUDE_ASM("asm/md_MAIN_003/nonmatchings/md_MAIN_003", func_800D0204);
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@@ -638,7 +678,78 @@ INCLUDE_ASM("asm/md_MAIN_003/nonmatchings/md_MAIN_003", func_800D0D6C);
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INCLUDE_ASM("asm/md_MAIN_003/nonmatchings/md_MAIN_003", func_800D12D0);
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INCLUDE_ASM("asm/md_MAIN_003/nonmatchings/md_MAIN_003", func_800D1D14);
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__asm__(".text\n.align 2\n.globl func_800D1D14\n.ent\tfunc_800D1D14\n"
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"func_800D1D14:\n.frame $sp,32,$31\n.mask 0xC0010000,-16\n.fmask 0,0\n"
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".set\tnoreorder\n"
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"addiu $sp, $sp, -32\n"
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"sw $ra, 28($sp)\n"
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"sw $fp, 24($sp)\n"
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"addu $fp, $sp, $zero\n"
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"sw $a0, 32($fp)\n"
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"sw $a1, 36($fp)\n"
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"lw $v0, 36($fp)\n"
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"nop\n"
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"bnez $v0, .L800D1D88\n"
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"nop\n"
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"lw $v0, 32($fp)\n"
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"nop\n"
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"addu $v1, $v0, $zero\n"
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"sll $v0, $v1, 2\n"
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"lui $a0, %hi(D_800D3630)\n"
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"addiu $a0, $a0, %lo(D_800D3630)\n"
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"addu $v1, $v0, $a0\n"
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"lh $v0, 0($v1)\n"
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"sw $zero, 16($sp)\n"
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"sw $zero, 20($sp)\n"
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"addu $a0, $v0, $zero\n"
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"lui $a1, %hi(D_800D3618)\n"
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"addiu $a1, $a1, %lo(D_800D3618)\n"
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"addu $a2, $zero, $zero\n"
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"addu $a3, $zero, $zero\n"
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"jal func_8001534C\n"
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"nop\n"
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"j .L800D1E00\n"
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"nop\n"
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".L800D1D88:\n"
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"lw $v0, 32($fp)\n"
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"nop\n"
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"addu $v1, $v0, $zero\n"
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"sll $v0, $v1, 2\n"
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"lui $a0, %hi(D_800D3630)\n"
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"addiu $a0, $a0, %lo(D_800D3630)\n"
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"addu $v1, $v0, $a0\n"
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"lh $v0, 0($v1)\n"
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"lw $v1, 32($fp)\n"
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"nop\n"
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"addu $a0, $v1, $zero\n"
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"sll $v1, $a0, 2\n"
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"lui $a0, %hi(D_800D3624)\n"
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"addiu $a0, $a0, %lo(D_800D3624)\n"
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"addu $v1, $v1, $a0\n"
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"lw $a0, 32($fp)\n"
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"lui $a1, %hi(D_800D3620)\n"
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"addiu $a1, $a1, %lo(D_800D3620)\n"
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"addu $a0, $a0, $a1\n"
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"lbu $a1, 0($a0)\n"
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"nop\n"
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"sll $a0, $a1, 16\n"
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"sra $a3, $a0, 16\n"
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"sw $zero, 16($sp)\n"
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"sw $zero, 20($sp)\n"
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"addu $a0, $v0, $zero\n"
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"lw $a1, 0($v1)\n"
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"addiu $a2, $zero, 80\n"
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"jal func_8001534C\n"
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"nop\n"
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".L800D1E00:\n"
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"addu $sp, $fp, $zero\n"
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"lw $ra, 28($sp)\n"
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"lw $fp, 24($sp)\n"
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"addiu $sp, $sp, 32\n"
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"jr $ra\n"
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"nop\n"
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".set\treorder\n.end\tfunc_800D1D14\n");
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typedef struct {
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s32 unk00; /* +0x00 */
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@@ -104,7 +104,37 @@ void func_800CFBF0(void) {
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INCLUDE_ASM("asm/md_MAIN_011/nonmatchings/md_MAIN_011", func_800CFC58);
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INCLUDE_ASM("asm/md_MAIN_011/nonmatchings/md_MAIN_011", func_800CFCBC);
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void func_800CFCBC(void) {
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extern s32 D_800D4C94;
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extern void func_800D0964(void);
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extern void func_800D0BDC(void);
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extern void func_800D1254(void);
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extern void func_800D1B00(void);
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extern void func_800D235C(void);
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extern void func_800D2BC4(void);
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if (D_800D4C94 != 0) {
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if (D_800D4C94 > 0) {
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func_800D0964();
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}
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if (D_800D4C94 >= 2) {
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func_800D0BDC();
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}
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if (D_800D4C94 >= 3) {
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func_800D1254();
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}
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if (D_800D4C94 >= 4) {
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func_800D1B00();
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}
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if (D_800D4C94 >= 5) {
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func_800D235C();
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}
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if (D_800D4C94 >= 6) {
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func_800D2BC4();
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}
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}
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}
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INCLUDE_ASM("asm/md_MAIN_011/nonmatchings/md_MAIN_011", func_800CFDB4);
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@@ -144,7 +174,32 @@ INCLUDE_ASM("asm/md_MAIN_011/nonmatchings/md_MAIN_011", func_800D04F4);
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INCLUDE_ASM("asm/md_MAIN_011/nonmatchings/md_MAIN_011", func_800D0828);
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INCLUDE_ASM("asm/md_MAIN_011/nonmatchings/md_MAIN_011", func_800D0858);
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void func_800D0858(void) {
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extern s32 func_800149E0(s32 a0);
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extern s32 func_80014B10(s32 a0);
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extern u16 D_800D4C9C;
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extern u16 D_800D4C98;
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extern u16 D_800D4CA0;
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extern u16 D_800D4CA4;
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D_800D4C9C = func_800149E0(0);
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D_800D4C98 = func_80014B10(0);
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if (D_800D4C98 != 0) {
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if (D_800D4C98 == D_800D4CA0) {
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if (--D_800D4CA4 == 0) {
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D_800D4C9C = D_800D4C98 & 0xF000;
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D_800D4CA4 = 3;
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}
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} else {
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D_800D4CA0 = D_800D4C98;
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D_800D4CA4 = 6;
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}
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} else {
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D_800D4CA0 = 0;
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D_800D4CA4 = 12;
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}
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}
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INCLUDE_ASM("asm/md_MAIN_011/nonmatchings/md_MAIN_011", func_800D0964);
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@@ -119,7 +119,46 @@ void func_800CB370(void *arg0) {
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}
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INCLUDE_ASM("asm/md_MAIN_013/nonmatchings/md_MAIN_013", func_800CB3CC);
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void func_800CB3CC(void *arg0) {
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extern void func_800D2318(void);
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extern void RotMatrixYXZ();
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extern void ApplyMatrixSV();
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extern void func_800D1FC8();
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extern s32 func_800D21C4();
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extern void func_80128EA8();
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extern void func_80146C3C();
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extern u8 D_800CB8FC[];
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extern u8 D_800CB8BC[];
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s16 sp10[8];
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s16 sp20[16];
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s32 p;
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func_800D2318();
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sp10[0] = *(u16 *)((s32)arg0 + 0x12);
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sp10[1] = *(u16 *)((s32)arg0 + 0x16);
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sp10[2] = 0;
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RotMatrixYXZ(sp10, sp20);
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sp10[1] = -8;
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sp10[0] = 0;
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sp10[2] = -0x10;
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ApplyMatrixSV(sp20, sp10, sp10);
|
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*(s32 *)((s32)arg0 + 0x4C) = (s16)(*(u16 *)((s32)arg0 + 6) = *(u16 *)((s32)arg0 + 6) + (u16)sp10[0]);
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||||
*(s32 *)((s32)arg0 + 0x50) = (s16)(*(u16 *)((s32)arg0 + 0xA) = *(u16 *)((s32)arg0 + 0xA) + (u16)sp10[1]);
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||||
*(s32 *)((s32)arg0 + 0x54) = (s16)(*(u16 *)((s32)arg0 + 0xE) = *(u16 *)((s32)arg0 + 0xE) + (u16)sp10[2]);
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func_800D1FC8(arg0, 6);
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p = func_800D21C4(arg0, D_800CB8FC, 0x19);
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if (p != 0) {
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*(s32 *)((s32)arg0 + 0x20) = p;
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*(u16 *)(p + 0x1A) = 0x3000;
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*(u16 *)(p + 0x18) = 0x3000;
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*(s32 *)(p + 4) |= 0x50000000;
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func_80128EA8(p, (s32)arg0 + 0x24, D_800CB8BC);
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*(u16 *)((s32)arg0 + 2) = *(u16 *)((s32)arg0 + 2) + 1;
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||||
} else {
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||||
((void (*)(s32))func_80146C3C)(arg0);
|
||||
}
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||||
}
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||||
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||||
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||||
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||||
extern void func_80146C3C(void);
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||||
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@@ -4053,7 +4053,83 @@ extern s32 func_8012AD50(void *a0);
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||||
}
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||||
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||||
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INCLUDE_ASM("asm/ov_SC02_016/nonmatchings/ov_SC02_016_jr_8017DC70", func_80180154);
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extern u8 D_800AF648[];
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extern u16 D_800AF7BE;
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||||
extern u8 *D_8018850C[];
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extern void func_80015978(s32 a0, s32 *a1);
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||||
extern void func_801802C8(u8 *a0, u8 *a1);
|
||||
|
||||
#define gte_SetRotMatrix(r0) __asm__ volatile ( \
|
||||
"lw $12, 0( %0 );" \
|
||||
"lw $13, 4( %0 );" \
|
||||
"ctc2 $12, $0;" \
|
||||
"ctc2 $13, $1;" \
|
||||
"lw $12, 8( %0 );" \
|
||||
"lw $13, 12( %0 );" \
|
||||
"lw $14, 16( %0 );" \
|
||||
"ctc2 $12, $2;" \
|
||||
"ctc2 $13, $3;" \
|
||||
"ctc2 $14, $4" \
|
||||
: \
|
||||
: "r"( r0 ) \
|
||||
: "$12", "$13", "$14" )
|
||||
#define gte_SetTransMatrix(r0) __asm__ volatile ( \
|
||||
"lw $12, 20( %0 );" \
|
||||
"lw $13, 24( %0 );" \
|
||||
"ctc2 $12, $5;" \
|
||||
"lw $14, 28( %0 );" \
|
||||
"ctc2 $13, $6;" \
|
||||
"ctc2 $14, $7" \
|
||||
: \
|
||||
: "r"( r0 ) \
|
||||
: "$12", "$13", "$14" )
|
||||
#define gte_ldv0(r0) __asm__ volatile ( \
|
||||
"lwc2 $0, 0( %0 );" \
|
||||
"lwc2 $1, 4( %0 )" \
|
||||
: \
|
||||
: "r"( r0 ) )
|
||||
#define gte_rtps() __asm__ volatile ("nop;nop;rtps")
|
||||
#define gte_stsxy(r0) __asm__ volatile ( \
|
||||
"swc2 $14, 0( %0 )" \
|
||||
: \
|
||||
: "r"( r0 ) \
|
||||
: "memory" )
|
||||
#define gte_stflg(r0) __asm__ volatile ( \
|
||||
"cfc2 $12, $31;" \
|
||||
"nop;" \
|
||||
"sw $12, 0( %0 )" \
|
||||
: \
|
||||
: "r"( r0 ) \
|
||||
: "$12", "memory" )
|
||||
|
||||
void func_80180154(s32 param_1)
|
||||
{
|
||||
s32 *m;
|
||||
u8 *rec;
|
||||
short sv[4];
|
||||
long flag;
|
||||
|
||||
rec = D_8018850C[*(s16 *)(param_1 + 0xFC)];
|
||||
m = (s32 *)D_800AF648;
|
||||
gte_SetRotMatrix(m);
|
||||
gte_SetTransMatrix(m);
|
||||
func_80015978(param_1 + 4, (s32 *)sv);
|
||||
gte_ldv0(sv);
|
||||
gte_rtps();
|
||||
gte_stsxy(sv);
|
||||
gte_stflg(&flag);
|
||||
if (((-D_800AF7BE / 2 < sv[1]) && (sv[1] < D_800AF7BE / 2 + 0x20)) && (flag >= 0)) {
|
||||
if (*(s32 *)(param_1 + 0x1C) == 0) {
|
||||
while (*(s16 *)(rec + 6) != 0xFF) {
|
||||
func_801802C8(param_1, rec);
|
||||
rec += 8;
|
||||
}
|
||||
*(s32 *)(param_1 + 0x1C) = *(s32 *)(param_1 + 0xDC);
|
||||
}
|
||||
*(s32 *)(param_1 + 0x1C) -= 1;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
extern u8 *func_801290DC(s32 a0, u8 *a1);
|
||||
|
||||
|
||||
@@ -3622,7 +3622,34 @@ s32 func_8017D65C(s32 a0) {
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_121/nonmatchings/ov_SC03_121_jr_8017BEBC", func_8017D788);
|
||||
u32 func_8017D788(s32 arg0, s16 arg1, s16 arg2) {
|
||||
s16 vec1[3];
|
||||
s16 vec2[3];
|
||||
u32 ret;
|
||||
s32 t;
|
||||
s32 x;
|
||||
s32 y;
|
||||
|
||||
t = func_8004787C(*(u16 *)(*(u32 *)(arg0 + 0x20) + 0x12) & 0xFFF);
|
||||
x = *(u16 *)(arg0 + 6) - (t * arg1 >> 12);
|
||||
vec1[0] = x;
|
||||
vec1[1] = *(u16 *)(arg0 + 0xA) - 0x10;
|
||||
t = func_80047948(*(u16 *)(*(u32 *)(arg0 + 0x20) + 0x12) & 0xFFF);
|
||||
y = *(u16 *)(arg0 + 0xE) - (t * arg1 >> 12);
|
||||
vec1[2] = y;
|
||||
vec2[0] = vec1[0];
|
||||
vec2[1] = vec1[1] + 0x20;
|
||||
vec2[2] = y;
|
||||
ret = func_80133784(1, vec1, vec2);
|
||||
if (((ret & 0x6000) == 0) && (arg2 != 0)) {
|
||||
t = func_8004787C(*(u16 *)(*(u32 *)(arg0 + 0x20) + 0x12) & 0xFFF);
|
||||
*(u16 *)(arg0 + 6) = vec2[0] + (t * arg1 >> 12);
|
||||
t = func_80047948(*(u16 *)(*(u32 *)(arg0 + 0x20) + 0x12) & 0xFFF);
|
||||
*(u16 *)(arg0 + 0xE) = vec2[2] + (t * arg1 >> 12);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_121/nonmatchings/ov_SC03_121_jr_8017BEBC", func_8017D8D4);
|
||||
|
||||
|
||||
@@ -3960,7 +3960,30 @@ void func_80181D50(void *a0) {
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC05_017/nonmatchings/ov_SC05_017_jr_801808D4", func_80181E0C);
|
||||
extern void func_80172710(void);
|
||||
extern s32 func_801845DC(void);
|
||||
extern s32 func_80185F5C(void *);
|
||||
extern s32 func_80178BF8(void);
|
||||
|
||||
#define func_80181E0C func_80181E0C_definition
|
||||
s32 func_80181E0C(void *a0) __asm__("func_80181E0C");
|
||||
s32 func_80181E0C(void *a0)
|
||||
{
|
||||
void *s0 = a0;
|
||||
|
||||
if (*(u16 *)(*(void **)(s0 + 0x64) + 2) == 2) {
|
||||
if (func_801845DC() != 0) {
|
||||
if (func_80185F5C(*(void **)(s0 + 0x64)) == 0) {
|
||||
*(u16 *)(*(void **)(s0 + 0x64) + 2) += 1;
|
||||
func_80178BF8();
|
||||
return (s32)func_80172710;
|
||||
}
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
#undef func_80181E0C
|
||||
|
||||
|
||||
|
||||
/* func_80181E90 — state-entry init (family exemplar, reach x11).
|
||||
|
||||
@@ -8295,7 +8295,52 @@ void func_8018494C(s32 p)
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_008/nonmatchings/ov_SC06_008_jr_8017C294", func_801849A8);
|
||||
extern void func_80015978(s32 a0, s32 *a1);
|
||||
extern s32 func_80183FF0(void);
|
||||
extern s32 func_80146A6C(s32 a0, void *a1, s32 a2, s32 a3, s32 a4, s32 a5, s32 a6);
|
||||
extern int rand(void);
|
||||
extern void func_80184AEC(s32 a0);
|
||||
extern void func_80159B3C(void *a0);
|
||||
extern void func_80165718(s32 a0);
|
||||
|
||||
void func_801849A8(s32 param_1)
|
||||
{
|
||||
s16 buf[4];
|
||||
s32 i;
|
||||
s32 slot;
|
||||
s32 r1;
|
||||
s32 r2;
|
||||
s32 r3;
|
||||
s16 rnd;
|
||||
u8 cnt;
|
||||
|
||||
func_80015978(param_1 + 4, (s32 *)buf);
|
||||
buf[1] -= 0x40;
|
||||
|
||||
i = 0;
|
||||
do {
|
||||
slot = func_80183FF0();
|
||||
if (slot >= 0) {
|
||||
func_80146A6C(0x51, (void *)param_1, buf[0], buf[1], buf[2], slot, 0);
|
||||
|
||||
r1 = rand();
|
||||
r2 = rand();
|
||||
r3 = rand();
|
||||
rnd = (r1 & 3) * 0x400 + (r2 & 3) * 0xfa + (r3 & 3) * 0x44;
|
||||
func_80146A6C(0x52, (void *)param_1, 0, -0x20, 0x10, rnd, 0);
|
||||
}
|
||||
i++;
|
||||
} while (i < 3);
|
||||
|
||||
cnt = *(u8 *)(param_1 + 0xde);
|
||||
*(u8 *)(param_1 + 0xde) = cnt + 0xff;
|
||||
if (cnt == 0) {
|
||||
func_80184AEC(param_1);
|
||||
func_80159B3C((void *)param_1);
|
||||
func_80165718(param_1);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
extern void func_80147364(u16 a0, s32 a1);
|
||||
extern void func_80147324(s32 a0);
|
||||
|
||||
Reference in New Issue
Block a user