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feat(phase-29): T58 — 8-family batch: 1 of 6 banked (func_8012A1BC 137/137, +10,686 ins)
Ran the batch with the T57 recipe (--band all --normalize-self-decls, live stubs derived from src/ not the stale map). 6 of 8 selected (two still filtered — selection line read this time). 821 candidate members across 6 families BANKED 137 — func_8012A1BC (78 ins) 137/137 failed 684 — the other FIVE families banked 0 each Attribution from git diff (137 x func_8012A1BC), not the per-group log lines whose split-name field my first aggregation mangled. THE SHAPE OF THE REMAINING FRONTIER — the finding. Across T56->T58 the per-family outcome is BINARY and near-total: a family banks ~137/137 or ~0/137, nothing in between. And each 0/N so far has had its OWN distinct cause — DATA decl scope (T56), FUNCTION decl scope (T57), jtbl table-count drift (func_8014032C), plus five more undiagnosed here. The mechanical lever is done pulling by itself: from here each family costs one diagnosis. A batch is now a DIAGNOSIS QUEUE, not a harvest, and the next phase of this work should be planned on that economics. GATES: R22 clean-fleet 140 passed, 0 failed of 140; tools-health OK (corpus 0 PHANTOM + 0 TRUNCATED, cdecl, audit-binaries, dedup 1886/0); 0 NON_MATCHING (G4). METRICS: instr 86.0% (11297091 -> 11307777 = +10,686 ins); fn-count 90.73% -> 90.77% (+137); distinct-code 76.7% -> 76.7% (+0). The distinct-code anomaly now has FOUR data points and still no explanation: T52 +125, T57 +125, T56 +0, T58 +0. All four families are PURE; the exemplar overlay does not separate them either (T56 and T57 both templated from ov_SC01_077 and disagree). Two behaviours, no identified variable. Still not guessed at — it stays the queued probe.
This commit is contained in:
Drew T
+1615
-1616
File diff suppressed because it is too large
Load Diff
+142
-142
@@ -4,157 +4,157 @@
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# cross-binary collapsible-byte leverage: docs/duplicates.cross.md.
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# THREE progress metrics (all matter — see the labels):
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FLEET fn-count byte-ident: 320924 / 353720 = 90.73% (REAL+LINKED+empties; FUNCTION-count, ×134-inflated — one crack counts per overlay)
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FLEET instr-weighted : 11297091 / 13141652 = 86.0% (shipped .text across main + resident + 138 overlays; the decomp.dev-DISPLAY number)
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FLEET fn-count byte-ident: 321061 / 353720 = 90.77% (REAL+LINKED+empties; FUNCTION-count, ×134-inflated — one crack counts per overlay)
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FLEET instr-weighted : 11307777 / 13141652 = 86.0% (shipped .text across main + resident + 138 overlays; the decomp.dev-DISPLAY number)
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FLEET distinct-code(uniq): 4322517 / 5634875 = 76.7% (67937/87459 unique fns; the DISTINCT-RE number)
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MAIN game-code weighted : 436 / 60201 = 0.7% (INCLUDED in the fleet numbers above since 2026-07-22 — roadmap §1 metrics contract; LINKED-excluding Ghidra sig dated 2026-06-14; caveat is R34: no independent second oracle for a PS-X EXE, NOT drift)
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(fleet EXCLUDING main, for continuity with pre-2026-07-22 readings: 11296655 / 13081451 = 86.4%)
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(fleet EXCLUDING main, for continuity with pre-2026-07-22 readings: 11307341 / 13081451 = 86.4%)
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FLEET REAL substantive : 319069 (of which dedup-shared 239530 via 1886 groups / 239604 instances)
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FLEET REAL substantive : 319206 (of which dedup-shared 239530 via 1886 groups / 239604 instances)
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FLEET LINKED PsyQ objs : 959
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FLEET NON_MATCHING : 7 (0 in any default build — G4)
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FLEET INCLUDE_ASM stubs : 32789
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FLEET INCLUDE_ASM stubs : 32652
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FLEET matchable : 353720
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| binary | REAL | shared | LINKED | byte-ident | matchable | byte-ident % |
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|---|---:|---:|---:|---:|---:|---:|
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| main | 54 | 2 | 959 | 1055 | 2096 | 50.3% |
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| resident | 129 | 0 | 0 | 131 | 145 | 90.3% |
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| ov_SC01_000 | 2286 | 1742 | 0 | 2286 | 2403 | 95.1% |
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| ov_SC01_001 | 2291 | 1743 | 0 | 2293 | 2466 | 93.0% |
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| ov_SC01_004 | 2281 | 1734 | 0 | 2282 | 2414 | 94.5% |
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| ov_SC01_005 | 2311 | 1757 | 0 | 2311 | 2503 | 92.3% |
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| ov_SC01_006 | 2311 | 1757 | 0 | 2311 | 2503 | 92.3% |
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| ov_SC01_008 | 2281 | 1734 | 0 | 2283 | 2426 | 94.1% |
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| ov_SC01_009 | 2307 | 1735 | 0 | 2308 | 2507 | 92.1% |
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| ov_SC01_074 | 2285 | 1735 | 0 | 2287 | 2425 | 94.3% |
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| ov_SC01_077 | 2464 | 1702 | 0 | 2466 | 2585 | 95.4% |
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| ov_SC01_080 | 2323 | 1738 | 0 | 2323 | 2512 | 92.5% |
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| ov_SC01_084 | 2330 | 1738 | 0 | 2335 | 2579 | 90.5% |
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| ov_SC02_000 | 2383 | 1773 | 0 | 2383 | 2683 | 88.8% |
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| ov_SC02_003 | 2383 | 1773 | 0 | 2383 | 2683 | 88.8% |
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| ov_SC02_004 | 2289 | 1738 | 0 | 2289 | 2401 | 95.3% |
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| ov_SC02_005 | 2397 | 1734 | 0 | 2407 | 2927 | 82.2% |
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| ov_SC02_011 | 2410 | 1741 | 0 | 2421 | 2893 | 83.7% |
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| ov_SC02_015 | 2291 | 1740 | 0 | 2291 | 2414 | 94.9% |
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| ov_SC02_016 | 2325 | 1740 | 0 | 2328 | 2545 | 91.5% |
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| ov_SC02_017 | 2369 | 1740 | 0 | 2377 | 2732 | 87.0% |
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| ov_SC02_021 | 2297 | 1740 | 0 | 2297 | 2437 | 94.3% |
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| ov_SC02_026 | 2312 | 1738 | 0 | 2318 | 2572 | 90.1% |
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| ov_SC02_027 | 2335 | 1738 | 0 | 2344 | 2692 | 87.1% |
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| ov_SC02_028 | 2337 | 1738 | 0 | 2347 | 2701 | 86.9% |
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| ov_SC02_031 | 2323 | 1739 | 0 | 2328 | 2562 | 90.9% |
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| ov_SC02_035 | 2298 | 1738 | 0 | 2301 | 2520 | 91.3% |
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| ov_SC02_039 | 2282 | 1738 | 0 | 2282 | 2416 | 94.5% |
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| ov_SC02_041 | 2320 | 1738 | 0 | 2323 | 2561 | 90.7% |
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| ov_SC03_001 | 2417 | 1739 | 0 | 2434 | 2869 | 84.8% |
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| ov_SC03_002 | 2343 | 1743 | 0 | 2358 | 2631 | 89.6% |
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| ov_SC03_003 | 2292 | 1738 | 0 | 2293 | 2423 | 94.6% |
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| ov_SC03_006 | 2360 | 1744 | 0 | 2369 | 2767 | 85.6% |
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| ov_SC03_007 | 2337 | 1738 | 0 | 2341 | 2623 | 89.2% |
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| ov_SC03_010 | 2300 | 1738 | 0 | 2300 | 2471 | 93.1% |
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| ov_SC03_011 | 2306 | 1738 | 0 | 2312 | 2527 | 91.5% |
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| ov_SC03_012 | 2284 | 1738 | 0 | 2285 | 2406 | 95.0% |
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| ov_SC03_013 | 2305 | 1738 | 0 | 2305 | 2493 | 92.5% |
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| ov_SC03_014 | 2363 | 1763 | 0 | 2363 | 2685 | 88.0% |
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| ov_SC03_015 | 2363 | 1763 | 0 | 2363 | 2685 | 88.0% |
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| ov_SC03_023 | 2291 | 1738 | 0 | 2292 | 2435 | 94.1% |
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| ov_SC03_024 | 2351 | 1743 | 0 | 2358 | 2641 | 89.3% |
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| ov_SC03_028 | 2331 | 1738 | 0 | 2335 | 2664 | 87.7% |
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| ov_SC03_029 | 2333 | 1740 | 0 | 2343 | 2644 | 88.6% |
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| ov_SC03_030 | 2306 | 1743 | 0 | 2308 | 2495 | 92.5% |
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| ov_SC03_031 | 2302 | 1738 | 0 | 2305 | 2514 | 91.7% |
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| ov_SC03_089 | 2319 | 1738 | 0 | 2326 | 2581 | 90.1% |
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| ov_SC03_090 | 2320 | 1738 | 0 | 2328 | 2625 | 88.7% |
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| ov_SC03_091 | 2323 | 1738 | 0 | 2331 | 2640 | 88.3% |
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| ov_SC03_092 | 2333 | 1738 | 0 | 2345 | 2587 | 90.6% |
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| ov_SC03_093 | 2309 | 1738 | 0 | 2313 | 2563 | 90.2% |
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| ov_SC03_094 | 2304 | 1738 | 0 | 2310 | 2577 | 89.6% |
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| ov_SC03_095 | 2294 | 1738 | 0 | 2297 | 2474 | 92.8% |
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| ov_SC03_096 | 2294 | 1738 | 0 | 2297 | 2465 | 93.2% |
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| ov_SC03_097 | 2324 | 1738 | 0 | 2331 | 2603 | 89.6% |
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| ov_SC03_098 | 2302 | 1738 | 0 | 2305 | 2541 | 90.7% |
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| ov_SC03_099 | 2295 | 1738 | 0 | 2298 | 2504 | 91.8% |
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| ov_SC03_100 | 2305 | 1738 | 0 | 2309 | 2539 | 90.9% |
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| ov_SC03_101 | 2305 | 1738 | 0 | 2309 | 2528 | 91.3% |
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| ov_SC03_102 | 2298 | 1738 | 0 | 2301 | 2492 | 92.3% |
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| ov_SC03_103 | 2301 | 1740 | 0 | 2304 | 2510 | 91.8% |
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| ov_SC03_104 | 2327 | 1738 | 0 | 2334 | 2616 | 89.2% |
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| ov_SC03_105 | 2318 | 1738 | 0 | 2325 | 2597 | 89.5% |
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| ov_SC03_108 | 2285 | 1738 | 0 | 2285 | 2443 | 93.5% |
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| ov_SC03_109 | 2289 | 1738 | 0 | 2291 | 2424 | 94.5% |
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| ov_SC03_110 | 2293 | 1738 | 0 | 2293 | 2468 | 92.9% |
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| ov_SC03_111 | 2304 | 1738 | 0 | 2307 | 2510 | 91.9% |
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| ov_SC03_112 | 2300 | 1740 | 0 | 2302 | 2526 | 91.1% |
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| ov_SC03_113 | 2293 | 1740 | 0 | 2296 | 2468 | 93.0% |
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| ov_SC03_114 | 2282 | 1738 | 0 | 2284 | 2415 | 94.6% |
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| ov_SC03_115 | 2299 | 1738 | 0 | 2301 | 2472 | 93.1% |
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| ov_SC03_116 | 2290 | 1738 | 0 | 2293 | 2438 | 94.1% |
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| ov_SC03_117 | 2317 | 1738 | 0 | 2323 | 2557 | 90.8% |
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| ov_SC03_118 | 2363 | 1762 | 0 | 2364 | 2685 | 88.0% |
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| ov_SC03_119 | 2362 | 1762 | 0 | 2363 | 2685 | 88.0% |
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| ov_SC03_121 | 2297 | 1738 | 0 | 2300 | 2459 | 93.5% |
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| ov_SC03_124 | 2375 | 1734 | 0 | 2395 | 2741 | 87.4% |
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| ov_SC03_125 | 2331 | 1738 | 0 | 2343 | 2588 | 90.5% |
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| ov_SC03_126 | 2294 | 1740 | 0 | 2294 | 2423 | 94.7% |
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| ov_SC04_000 | 2310 | 1742 | 0 | 2319 | 2546 | 91.1% |
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| ov_SC04_002 | 2329 | 1738 | 0 | 2333 | 2636 | 88.5% |
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| ov_SC04_003 | 2305 | 1738 | 0 | 2309 | 2502 | 92.3% |
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| ov_SC04_004 | 2314 | 1738 | 0 | 2316 | 2558 | 90.5% |
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| ov_SC04_005 | 2324 | 1738 | 0 | 2330 | 2612 | 89.2% |
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| ov_SC04_006 | 2294 | 1738 | 0 | 2296 | 2454 | 93.6% |
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| ov_SC04_007 | 2318 | 1738 | 0 | 2322 | 2569 | 90.4% |
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| ov_SC04_008 | 2286 | 1738 | 0 | 2286 | 2415 | 94.7% |
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| ov_SC04_009 | 2301 | 1738 | 0 | 2304 | 2441 | 94.4% |
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| ov_SC04_010 | 2291 | 1738 | 0 | 2292 | 2419 | 94.7% |
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| ov_SC04_011 | 2349 | 1738 | 0 | 2355 | 2803 | 84.0% |
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| ov_SC04_012 | 2288 | 1738 | 0 | 2289 | 2420 | 94.6% |
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| ov_SC04_015 | 2353 | 1739 | 0 | 2364 | 2611 | 90.5% |
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| ov_SC04_016 | 2291 | 1738 | 0 | 2293 | 2440 | 94.0% |
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| ov_SC04_018 | 2401 | 1773 | 0 | 2401 | 2857 | 84.0% |
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| ov_SC04_019 | 2407 | 1773 | 0 | 2407 | 2857 | 84.2% |
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| ov_SC04_020 | 2318 | 1738 | 0 | 2330 | 2567 | 90.8% |
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| ov_SC04_021 | 2295 | 1740 | 0 | 2295 | 2423 | 94.7% |
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| ov_SC05_000 | 2292 | 1742 | 0 | 2295 | 2422 | 94.8% |
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| ov_SC05_001 | 2314 | 1738 | 0 | 2319 | 2574 | 90.1% |
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| ov_SC05_002 | 2297 | 1738 | 0 | 2300 | 2442 | 94.2% |
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| ov_SC05_003 | 2294 | 1738 | 0 | 2295 | 2481 | 92.5% |
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| ov_SC05_004 | 2290 | 1738 | 0 | 2292 | 2464 | 93.0% |
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| ov_SC05_005 | 2295 | 1738 | 0 | 2296 | 2491 | 92.2% |
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| ov_SC05_006 | 2288 | 1738 | 0 | 2288 | 2430 | 94.2% |
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| ov_SC05_007 | 2298 | 1738 | 0 | 2303 | 2482 | 92.8% |
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| ov_SC05_008 | 2315 | 1738 | 0 | 2317 | 2543 | 91.1% |
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| ov_SC05_009 | 2294 | 1738 | 0 | 2298 | 2438 | 94.3% |
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| ov_SC05_010 | 2321 | 1738 | 0 | 2325 | 2588 | 89.8% |
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| ov_SC05_011 | 2290 | 1738 | 0 | 2291 | 2409 | 95.1% |
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| ov_SC05_017 | 2397 | 1735 | 0 | 2408 | 2842 | 84.7% |
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| ov_SC05_018 | 2344 | 1738 | 0 | 2357 | 2673 | 88.2% |
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| ov_SC05_019 | 2295 | 1740 | 0 | 2295 | 2423 | 94.7% |
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| ov_SC06_000 | 2359 | 1747 | 0 | 2362 | 2691 | 87.8% |
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| ov_SC06_006 | 2311 | 1738 | 0 | 2312 | 2511 | 92.1% |
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| ov_SC06_008 | 2331 | 1740 | 0 | 2337 | 2542 | 91.9% |
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| ov_SC06_010 | 2311 | 1738 | 0 | 2316 | 2517 | 92.0% |
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| ov_SC06_011 | 2299 | 1738 | 0 | 2303 | 2468 | 93.3% |
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| ov_SC06_013 | 2293 | 1738 | 0 | 2294 | 2425 | 94.6% |
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| ov_SC06_014 | 2299 | 1738 | 0 | 2301 | 2453 | 93.8% |
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| ov_SC06_015 | 2296 | 1738 | 0 | 2296 | 2421 | 94.8% |
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| ov_SC06_016 | 2314 | 1738 | 0 | 2316 | 2549 | 90.9% |
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| ov_SC06_018 | 2323 | 1740 | 0 | 2330 | 2665 | 87.4% |
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| ov_SC06_020 | 2303 | 1740 | 0 | 2304 | 2518 | 91.5% |
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| ov_SC06_022 | 2322 | 1738 | 0 | 2330 | 2642 | 88.2% |
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| ov_SC06_024 | 2332 | 1738 | 0 | 2338 | 2667 | 87.7% |
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| ov_SC06_025 | 2316 | 1738 | 0 | 2321 | 2572 | 90.2% |
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| ov_SC06_027 | 2281 | 1738 | 0 | 2282 | 2408 | 94.8% |
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| ov_SC06_029 | 2342 | 1738 | 0 | 2354 | 2662 | 88.4% |
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| ov_SC06_030 | 2295 | 1738 | 0 | 2295 | 2456 | 93.4% |
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| ov_SC06_032 | 2317 | 1739 | 0 | 2324 | 2658 | 87.4% |
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| ov_SC06_033 | 2319 | 1739 | 0 | 2326 | 2631 | 88.4% |
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| ov_SC07_000 | 2310 | 1742 | 0 | 2312 | 2521 | 91.7% |
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| ov_SC07_001 | 2294 | 1738 | 0 | 2296 | 2454 | 93.6% |
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| ov_SC07_002 | 2322 | 1738 | 0 | 2326 | 2579 | 90.2% |
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| ov_SC01_000 | 2287 | 1742 | 0 | 2287 | 2403 | 95.2% |
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| ov_SC01_001 | 2292 | 1743 | 0 | 2294 | 2466 | 93.0% |
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| ov_SC01_004 | 2282 | 1734 | 0 | 2283 | 2414 | 94.6% |
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| ov_SC01_005 | 2312 | 1757 | 0 | 2312 | 2503 | 92.4% |
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| ov_SC01_006 | 2312 | 1757 | 0 | 2312 | 2503 | 92.4% |
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| ov_SC01_008 | 2282 | 1734 | 0 | 2284 | 2426 | 94.1% |
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| ov_SC01_009 | 2308 | 1735 | 0 | 2309 | 2507 | 92.1% |
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| ov_SC01_074 | 2286 | 1735 | 0 | 2288 | 2425 | 94.4% |
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| ov_SC01_077 | 2465 | 1702 | 0 | 2467 | 2585 | 95.4% |
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| ov_SC01_080 | 2324 | 1738 | 0 | 2324 | 2512 | 92.5% |
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| ov_SC01_084 | 2331 | 1738 | 0 | 2336 | 2579 | 90.6% |
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| ov_SC02_000 | 2384 | 1773 | 0 | 2384 | 2683 | 88.9% |
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| ov_SC02_003 | 2384 | 1773 | 0 | 2384 | 2683 | 88.9% |
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| ov_SC02_004 | 2290 | 1738 | 0 | 2290 | 2401 | 95.4% |
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| ov_SC02_005 | 2398 | 1734 | 0 | 2408 | 2927 | 82.3% |
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| ov_SC02_011 | 2411 | 1741 | 0 | 2422 | 2893 | 83.7% |
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| ov_SC02_015 | 2292 | 1740 | 0 | 2292 | 2414 | 94.9% |
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| ov_SC02_016 | 2326 | 1740 | 0 | 2329 | 2545 | 91.5% |
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| ov_SC02_017 | 2370 | 1740 | 0 | 2378 | 2732 | 87.0% |
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| ov_SC02_021 | 2298 | 1740 | 0 | 2298 | 2437 | 94.3% |
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| ov_SC02_026 | 2313 | 1738 | 0 | 2319 | 2572 | 90.2% |
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| ov_SC02_027 | 2336 | 1738 | 0 | 2345 | 2692 | 87.1% |
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| ov_SC02_028 | 2338 | 1738 | 0 | 2348 | 2701 | 86.9% |
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| ov_SC02_031 | 2324 | 1739 | 0 | 2329 | 2562 | 90.9% |
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| ov_SC02_035 | 2299 | 1738 | 0 | 2302 | 2520 | 91.3% |
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| ov_SC02_039 | 2283 | 1738 | 0 | 2283 | 2416 | 94.5% |
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| ov_SC02_041 | 2321 | 1738 | 0 | 2324 | 2561 | 90.7% |
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| ov_SC03_001 | 2418 | 1739 | 0 | 2435 | 2869 | 84.9% |
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| ov_SC03_002 | 2344 | 1743 | 0 | 2359 | 2631 | 89.7% |
|
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| ov_SC03_003 | 2293 | 1738 | 0 | 2294 | 2423 | 94.7% |
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| ov_SC03_006 | 2361 | 1744 | 0 | 2370 | 2767 | 85.7% |
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| ov_SC03_007 | 2338 | 1738 | 0 | 2342 | 2623 | 89.3% |
|
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| ov_SC03_010 | 2301 | 1738 | 0 | 2301 | 2471 | 93.1% |
|
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| ov_SC03_011 | 2307 | 1738 | 0 | 2313 | 2527 | 91.5% |
|
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| ov_SC03_012 | 2285 | 1738 | 0 | 2286 | 2406 | 95.0% |
|
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| ov_SC03_013 | 2306 | 1738 | 0 | 2306 | 2493 | 92.5% |
|
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| ov_SC03_014 | 2364 | 1763 | 0 | 2364 | 2685 | 88.0% |
|
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| ov_SC03_015 | 2364 | 1763 | 0 | 2364 | 2685 | 88.0% |
|
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| ov_SC03_023 | 2292 | 1738 | 0 | 2293 | 2435 | 94.2% |
|
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| ov_SC03_024 | 2352 | 1743 | 0 | 2359 | 2641 | 89.3% |
|
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| ov_SC03_028 | 2332 | 1738 | 0 | 2336 | 2664 | 87.7% |
|
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| ov_SC03_029 | 2334 | 1740 | 0 | 2344 | 2644 | 88.7% |
|
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| ov_SC03_030 | 2307 | 1743 | 0 | 2309 | 2495 | 92.5% |
|
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| ov_SC03_031 | 2303 | 1738 | 0 | 2306 | 2514 | 91.7% |
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| ov_SC03_089 | 2320 | 1738 | 0 | 2327 | 2581 | 90.2% |
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| ov_SC03_090 | 2321 | 1738 | 0 | 2329 | 2625 | 88.7% |
|
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| ov_SC03_091 | 2324 | 1738 | 0 | 2332 | 2640 | 88.3% |
|
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| ov_SC03_092 | 2334 | 1738 | 0 | 2346 | 2587 | 90.7% |
|
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| ov_SC03_093 | 2310 | 1738 | 0 | 2314 | 2563 | 90.3% |
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| ov_SC03_094 | 2305 | 1738 | 0 | 2311 | 2577 | 89.7% |
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| ov_SC03_095 | 2295 | 1738 | 0 | 2298 | 2474 | 92.9% |
|
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| ov_SC03_096 | 2295 | 1738 | 0 | 2298 | 2465 | 93.2% |
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| ov_SC03_097 | 2325 | 1738 | 0 | 2332 | 2603 | 89.6% |
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| ov_SC03_098 | 2303 | 1738 | 0 | 2306 | 2541 | 90.8% |
|
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| ov_SC03_099 | 2296 | 1738 | 0 | 2299 | 2504 | 91.8% |
|
||||
| ov_SC03_100 | 2306 | 1738 | 0 | 2310 | 2539 | 91.0% |
|
||||
| ov_SC03_101 | 2306 | 1738 | 0 | 2310 | 2528 | 91.4% |
|
||||
| ov_SC03_102 | 2299 | 1738 | 0 | 2302 | 2492 | 92.4% |
|
||||
| ov_SC03_103 | 2302 | 1740 | 0 | 2305 | 2510 | 91.8% |
|
||||
| ov_SC03_104 | 2328 | 1738 | 0 | 2335 | 2616 | 89.3% |
|
||||
| ov_SC03_105 | 2319 | 1738 | 0 | 2326 | 2597 | 89.6% |
|
||||
| ov_SC03_108 | 2286 | 1738 | 0 | 2286 | 2443 | 93.6% |
|
||||
| ov_SC03_109 | 2290 | 1738 | 0 | 2292 | 2424 | 94.6% |
|
||||
| ov_SC03_110 | 2294 | 1738 | 0 | 2294 | 2468 | 92.9% |
|
||||
| ov_SC03_111 | 2305 | 1738 | 0 | 2308 | 2510 | 92.0% |
|
||||
| ov_SC03_112 | 2301 | 1740 | 0 | 2303 | 2526 | 91.2% |
|
||||
| ov_SC03_113 | 2294 | 1740 | 0 | 2297 | 2468 | 93.1% |
|
||||
| ov_SC03_114 | 2283 | 1738 | 0 | 2285 | 2415 | 94.6% |
|
||||
| ov_SC03_115 | 2300 | 1738 | 0 | 2302 | 2472 | 93.1% |
|
||||
| ov_SC03_116 | 2291 | 1738 | 0 | 2294 | 2438 | 94.1% |
|
||||
| ov_SC03_117 | 2318 | 1738 | 0 | 2324 | 2557 | 90.9% |
|
||||
| ov_SC03_118 | 2364 | 1762 | 0 | 2365 | 2685 | 88.1% |
|
||||
| ov_SC03_119 | 2363 | 1762 | 0 | 2364 | 2685 | 88.0% |
|
||||
| ov_SC03_121 | 2298 | 1738 | 0 | 2301 | 2459 | 93.6% |
|
||||
| ov_SC03_124 | 2376 | 1734 | 0 | 2396 | 2741 | 87.4% |
|
||||
| ov_SC03_125 | 2332 | 1738 | 0 | 2344 | 2588 | 90.6% |
|
||||
| ov_SC03_126 | 2295 | 1740 | 0 | 2295 | 2423 | 94.7% |
|
||||
| ov_SC04_000 | 2311 | 1742 | 0 | 2320 | 2546 | 91.1% |
|
||||
| ov_SC04_002 | 2330 | 1738 | 0 | 2334 | 2636 | 88.5% |
|
||||
| ov_SC04_003 | 2306 | 1738 | 0 | 2310 | 2502 | 92.3% |
|
||||
| ov_SC04_004 | 2315 | 1738 | 0 | 2317 | 2558 | 90.6% |
|
||||
| ov_SC04_005 | 2325 | 1738 | 0 | 2331 | 2612 | 89.2% |
|
||||
| ov_SC04_006 | 2295 | 1738 | 0 | 2297 | 2454 | 93.6% |
|
||||
| ov_SC04_007 | 2319 | 1738 | 0 | 2323 | 2569 | 90.4% |
|
||||
| ov_SC04_008 | 2287 | 1738 | 0 | 2287 | 2415 | 94.7% |
|
||||
| ov_SC04_009 | 2302 | 1738 | 0 | 2305 | 2441 | 94.4% |
|
||||
| ov_SC04_010 | 2292 | 1738 | 0 | 2293 | 2419 | 94.8% |
|
||||
| ov_SC04_011 | 2350 | 1738 | 0 | 2356 | 2803 | 84.1% |
|
||||
| ov_SC04_012 | 2289 | 1738 | 0 | 2290 | 2420 | 94.6% |
|
||||
| ov_SC04_015 | 2354 | 1739 | 0 | 2365 | 2611 | 90.6% |
|
||||
| ov_SC04_016 | 2292 | 1738 | 0 | 2294 | 2440 | 94.0% |
|
||||
| ov_SC04_018 | 2402 | 1773 | 0 | 2402 | 2857 | 84.1% |
|
||||
| ov_SC04_019 | 2408 | 1773 | 0 | 2408 | 2857 | 84.3% |
|
||||
| ov_SC04_020 | 2319 | 1738 | 0 | 2331 | 2567 | 90.8% |
|
||||
| ov_SC04_021 | 2296 | 1740 | 0 | 2296 | 2423 | 94.8% |
|
||||
| ov_SC05_000 | 2293 | 1742 | 0 | 2296 | 2422 | 94.8% |
|
||||
| ov_SC05_001 | 2315 | 1738 | 0 | 2320 | 2574 | 90.1% |
|
||||
| ov_SC05_002 | 2298 | 1738 | 0 | 2301 | 2442 | 94.2% |
|
||||
| ov_SC05_003 | 2295 | 1738 | 0 | 2296 | 2481 | 92.5% |
|
||||
| ov_SC05_004 | 2291 | 1738 | 0 | 2293 | 2464 | 93.1% |
|
||||
| ov_SC05_005 | 2296 | 1738 | 0 | 2297 | 2491 | 92.2% |
|
||||
| ov_SC05_006 | 2289 | 1738 | 0 | 2289 | 2430 | 94.2% |
|
||||
| ov_SC05_007 | 2299 | 1738 | 0 | 2304 | 2482 | 92.8% |
|
||||
| ov_SC05_008 | 2316 | 1738 | 0 | 2318 | 2543 | 91.2% |
|
||||
| ov_SC05_009 | 2295 | 1738 | 0 | 2299 | 2438 | 94.3% |
|
||||
| ov_SC05_010 | 2322 | 1738 | 0 | 2326 | 2588 | 89.9% |
|
||||
| ov_SC05_011 | 2291 | 1738 | 0 | 2292 | 2409 | 95.1% |
|
||||
| ov_SC05_017 | 2398 | 1735 | 0 | 2409 | 2842 | 84.8% |
|
||||
| ov_SC05_018 | 2345 | 1738 | 0 | 2358 | 2673 | 88.2% |
|
||||
| ov_SC05_019 | 2296 | 1740 | 0 | 2296 | 2423 | 94.8% |
|
||||
| ov_SC06_000 | 2360 | 1747 | 0 | 2363 | 2691 | 87.8% |
|
||||
| ov_SC06_006 | 2312 | 1738 | 0 | 2313 | 2511 | 92.1% |
|
||||
| ov_SC06_008 | 2332 | 1740 | 0 | 2338 | 2542 | 92.0% |
|
||||
| ov_SC06_010 | 2312 | 1738 | 0 | 2317 | 2517 | 92.1% |
|
||||
| ov_SC06_011 | 2300 | 1738 | 0 | 2304 | 2468 | 93.4% |
|
||||
| ov_SC06_013 | 2294 | 1738 | 0 | 2295 | 2425 | 94.6% |
|
||||
| ov_SC06_014 | 2300 | 1738 | 0 | 2302 | 2453 | 93.8% |
|
||||
| ov_SC06_015 | 2297 | 1738 | 0 | 2297 | 2421 | 94.9% |
|
||||
| ov_SC06_016 | 2315 | 1738 | 0 | 2317 | 2549 | 90.9% |
|
||||
| ov_SC06_018 | 2324 | 1740 | 0 | 2331 | 2665 | 87.5% |
|
||||
| ov_SC06_020 | 2304 | 1740 | 0 | 2305 | 2518 | 91.5% |
|
||||
| ov_SC06_022 | 2323 | 1738 | 0 | 2331 | 2642 | 88.2% |
|
||||
| ov_SC06_024 | 2333 | 1738 | 0 | 2339 | 2667 | 87.7% |
|
||||
| ov_SC06_025 | 2317 | 1738 | 0 | 2322 | 2572 | 90.3% |
|
||||
| ov_SC06_027 | 2282 | 1738 | 0 | 2283 | 2408 | 94.8% |
|
||||
| ov_SC06_029 | 2343 | 1738 | 0 | 2355 | 2662 | 88.5% |
|
||||
| ov_SC06_030 | 2296 | 1738 | 0 | 2296 | 2456 | 93.5% |
|
||||
| ov_SC06_032 | 2318 | 1739 | 0 | 2325 | 2658 | 87.5% |
|
||||
| ov_SC06_033 | 2320 | 1739 | 0 | 2327 | 2631 | 88.4% |
|
||||
| ov_SC07_000 | 2311 | 1742 | 0 | 2313 | 2521 | 91.7% |
|
||||
| ov_SC07_001 | 2295 | 1738 | 0 | 2297 | 2454 | 93.6% |
|
||||
| ov_SC07_002 | 2323 | 1738 | 0 | 2327 | 2579 | 90.2% |
|
||||
| ov_SC07_006 | 2091 | 1555 | 0 | 2171 | 2456 | 88.4% |
|
||||
| ov_SC07_007 | 2086 | 1586 | 0 | 2170 | 2613 | 83.0% |
|
||||
| ov_SC07_008 | 2279 | 1738 | 0 | 2279 | 2386 | 95.5% |
|
||||
| ov_SC07_009 | 2288 | 1738 | 0 | 2290 | 2430 | 94.2% |
|
||||
| ov_SC07_010 | 2119 | 1608 | 0 | 2202 | 2524 | 87.2% |
|
||||
| ov_SC07_011 | 2086 | 1585 | 0 | 2166 | 2449 | 88.4% |
|
||||
| ov_SC07_007 | 2087 | 1586 | 0 | 2171 | 2613 | 83.1% |
|
||||
| ov_SC07_008 | 2280 | 1738 | 0 | 2280 | 2386 | 95.6% |
|
||||
| ov_SC07_009 | 2289 | 1738 | 0 | 2291 | 2430 | 94.3% |
|
||||
| ov_SC07_010 | 2120 | 1608 | 0 | 2203 | 2524 | 87.3% |
|
||||
| ov_SC07_011 | 2087 | 1585 | 0 | 2167 | 2449 | 88.5% |
|
||||
|
||||
@@ -7954,3 +7954,41 @@ not about the code.**
|
||||
**This sharpens the T56 anomaly rather than resolving it:** 132 banked here moved distinct-code
|
||||
**+125**, and T52's 132 also moved it **+125** — but T56's 136 moved it **+0**. Three PURE families,
|
||||
two behave one way and one the other. Still unexplained, still not guessed at.
|
||||
|
||||
## ✅/📌 T58 — 8-family batch: **1 of 6 banked** (`func_8012A1BC` 137/137, +10,686 ins). Yield is now per-family.
|
||||
|
||||
Ran the batch with the T57 recipe (`--band all --normalize-self-decls`, live stubs derived from
|
||||
`src/` not the stale map). **6 of 8 selected** (two still filtered — selection line read this time).
|
||||
|
||||
| | |
|
||||
|---|---|
|
||||
| candidate members | 821 across 6 families |
|
||||
| **banked** | **137** — `func_8012A1BC` (78 ins), **137/137** |
|
||||
| failed | 684 — the other **5 families banked 0 each** |
|
||||
|
||||
Attribution taken from `git diff` (`137 × func_8012A1BC`), not from the per-group log lines, whose
|
||||
split-name field my first aggregation mangled.
|
||||
|
||||
### THE SHAPE OF THE REMAINING FRONTIER — this is the finding
|
||||
Across T56→T58 the per-family outcome is **binary and near-total**: a family banks ~137/137 or
|
||||
~0/137. Nothing lands in between. Combined with T55/T57, each `0/N` so far has had its **own
|
||||
distinct** cause — DATA decl scope (T56), FUNCTION decl scope (T57), jtbl table-count drift
|
||||
(`func_8014032C`), and now five more undiagnosed. **The mechanical lever is done pulling by itself:
|
||||
from here each family costs one diagnosis.** That is a different economics from T52–T57 and should
|
||||
be planned as such — a batch is now a *diagnosis queue*, not a harvest.
|
||||
|
||||
### GATES
|
||||
**R22 clean-fleet 140 passed, 0 failed of 140** · `tools-health` **OK** (corpus 0 PHANTOM +
|
||||
0 TRUNCATED · cdecl · audit-binaries · dedup **1886 / 0**) · **0 NON_MATCHING** (G4).
|
||||
|
||||
### METRICS
|
||||
| | before | after | delta |
|
||||
|---|---|---|---|
|
||||
| instr-weighted | 86.0% | **86.0%** | 11,297,091 → 11,307,777 = **+10,686 ins** |
|
||||
| fn-count | 90.73% | **90.77%** | 320,924 → 321,061 = **+137** |
|
||||
| distinct-code | 76.7% | 76.7% | **+0** |
|
||||
|
||||
**The distinct-code anomaly now has four data points and still no explanation:** T52 (+125),
|
||||
T57 (+125), T56 (**+0**), T58 (**+0**). All four families are classed PURE; the exemplar overlay
|
||||
does not separate them either (T56 and T57 both templated from `ov_SC01_077` and disagree). Two
|
||||
behaviours, no identified variable. **Still not guessed at** — it stays the queued probe.
|
||||
|
||||
@@ -663,7 +663,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC01_000/nonmatchings/ov_SC01_000", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC01_001/nonmatchings/ov_SC01_001", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -666,7 +666,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC01_004/nonmatchings/ov_SC01_004", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -666,7 +666,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC01_005/nonmatchings/ov_SC01_005", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -666,7 +666,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC01_006/nonmatchings/ov_SC01_006", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -666,7 +666,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC01_008/nonmatchings/ov_SC01_008", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -666,7 +666,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC01_009/nonmatchings/ov_SC01_009", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -666,7 +666,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC01_074/nonmatchings/ov_SC01_074", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -752,7 +752,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC01_077/nonmatchings/ov_SC01_077_a", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -666,7 +666,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC01_080/nonmatchings/ov_SC01_080", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -666,7 +666,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC01_084/nonmatchings/ov_SC01_084", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC02_000/nonmatchings/ov_SC02_000", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC02_003/nonmatchings/ov_SC02_003", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -666,7 +666,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC02_004/nonmatchings/ov_SC02_004", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -666,7 +666,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC02_005/nonmatchings/ov_SC02_005", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -666,7 +666,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC02_011/nonmatchings/ov_SC02_011", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -666,7 +666,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC02_015/nonmatchings/ov_SC02_015", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -666,7 +666,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC02_016/nonmatchings/ov_SC02_016", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -666,7 +666,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC02_017/nonmatchings/ov_SC02_017", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -666,7 +666,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC02_021/nonmatchings/ov_SC02_021", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -666,7 +666,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC02_026/nonmatchings/ov_SC02_026", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -666,7 +666,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC02_027/nonmatchings/ov_SC02_027", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -666,7 +666,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC02_028/nonmatchings/ov_SC02_028", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -666,7 +666,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC02_031/nonmatchings/ov_SC02_031", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -666,7 +666,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC02_035/nonmatchings/ov_SC02_035", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC02_039/nonmatchings/ov_SC02_039", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC02_041/nonmatchings/ov_SC02_041", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_001/nonmatchings/ov_SC03_001", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_002/nonmatchings/ov_SC03_002", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_003/nonmatchings/ov_SC03_003", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_006/nonmatchings/ov_SC03_006", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_007/nonmatchings/ov_SC03_007", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_010/nonmatchings/ov_SC03_010", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_011/nonmatchings/ov_SC03_011", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_012/nonmatchings/ov_SC03_012", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_013/nonmatchings/ov_SC03_013", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_014/nonmatchings/ov_SC03_014", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_015/nonmatchings/ov_SC03_015", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_023/nonmatchings/ov_SC03_023", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_024/nonmatchings/ov_SC03_024", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_028/nonmatchings/ov_SC03_028", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_029/nonmatchings/ov_SC03_029", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_030/nonmatchings/ov_SC03_030", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_031/nonmatchings/ov_SC03_031", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_089/nonmatchings/ov_SC03_089", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_090/nonmatchings/ov_SC03_090", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_091/nonmatchings/ov_SC03_091", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_092/nonmatchings/ov_SC03_092", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_093/nonmatchings/ov_SC03_093", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_094/nonmatchings/ov_SC03_094", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_095/nonmatchings/ov_SC03_095", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_096/nonmatchings/ov_SC03_096", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_097/nonmatchings/ov_SC03_097", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_098/nonmatchings/ov_SC03_098", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_099/nonmatchings/ov_SC03_099", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_100/nonmatchings/ov_SC03_100", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_101/nonmatchings/ov_SC03_101", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_102/nonmatchings/ov_SC03_102", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_103/nonmatchings/ov_SC03_103", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_104/nonmatchings/ov_SC03_104", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_105/nonmatchings/ov_SC03_105", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_108/nonmatchings/ov_SC03_108", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_109/nonmatchings/ov_SC03_109", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_110/nonmatchings/ov_SC03_110", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_111/nonmatchings/ov_SC03_111", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_112/nonmatchings/ov_SC03_112", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_113/nonmatchings/ov_SC03_113", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_114/nonmatchings/ov_SC03_114", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_115/nonmatchings/ov_SC03_115", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_116/nonmatchings/ov_SC03_116", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_117/nonmatchings/ov_SC03_117", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_118/nonmatchings/ov_SC03_118", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_119/nonmatchings/ov_SC03_119", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_121/nonmatchings/ov_SC03_121", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_124/nonmatchings/ov_SC03_124", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_125/nonmatchings/ov_SC03_125", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_126/nonmatchings/ov_SC03_126", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC04_000/nonmatchings/ov_SC04_000", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC04_002/nonmatchings/ov_SC04_002", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC04_003/nonmatchings/ov_SC04_003", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC04_004/nonmatchings/ov_SC04_004", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC04_005/nonmatchings/ov_SC04_005", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC04_006/nonmatchings/ov_SC04_006", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC04_007/nonmatchings/ov_SC04_007", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC04_008/nonmatchings/ov_SC04_008", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC04_009/nonmatchings/ov_SC04_009", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC04_010/nonmatchings/ov_SC04_010", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC04_011/nonmatchings/ov_SC04_011", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC04_012/nonmatchings/ov_SC04_012", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC04_015/nonmatchings/ov_SC04_015", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC04_016/nonmatchings/ov_SC04_016", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC04_018/nonmatchings/ov_SC04_018", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC04_019/nonmatchings/ov_SC04_019", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC04_020/nonmatchings/ov_SC04_020", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC04_021/nonmatchings/ov_SC04_021", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC05_000/nonmatchings/ov_SC05_000", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
@@ -665,7 +665,54 @@ DEFINE_func_8012A100() /* dedup: shared engine-core @0x8012A100 (src/shared) */
|
||||
|
||||
DEFINE_func_8012A110() /* dedup: shared engine-core @0x8012A110 (src/shared) */
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC05_001/nonmatchings/ov_SC05_001", func_8012A1BC);
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (78 ins, relocation-masked). Register pins ($2-$5 reused for
|
||||
// the D_x200-x20C words then the D_x220-x226 halfwords; $6-$10 held across for the
|
||||
// D_x228/x22A/x294/x298/x29A tail) force the frameless 9-deep allocation the default
|
||||
// -O2 pre-reload scheduler otherwise blows to a 3-reg spill (all 720 stmt orders spill
|
||||
// without the pins). A single zero-byte scheduling/memory barrier after the 4 word
|
||||
// stores stops gcc hoisting the first 8-byte block copy above them.
|
||||
|
||||
|
||||
|
||||
|
||||
void func_8012A1BC(void) {
|
||||
|
||||
extern s16 D_80120218;
|
||||
extern s16 D_80120222;
|
||||
extern s16 D_80120224;
|
||||
extern s16 D_80120226;
|
||||
extern s16 D_80120228;
|
||||
extern s16 D_8012022A;
|
||||
extern s16 D_8012029A;
|
||||
extern s32 D_80120200, D_80120204, D_80120208, D_8012020C;
|
||||
extern s16 D_80120210;
|
||||
extern s16 D_80120220;
|
||||
extern s32 D_80120294;
|
||||
extern s16 D_80120298;
|
||||
extern s32 D_80126950, D_80126954, D_80126958, D_8012695C;
|
||||
extern Blk8 D_80126960, D_80126968;
|
||||
extern u16 D_80126970, D_80126972, D_80126974, D_80126976, D_80126978, D_8012697A;
|
||||
extern s32 D_801269E4;
|
||||
extern u16 D_801269E8, D_801269EA;
|
||||
register s32 r2 __asm__("$2"), r3 __asm__("$3"), r4 __asm__("$4"), r5 __asm__("$5");
|
||||
register u16 r6 __asm__("$6"), r7 __asm__("$7");
|
||||
register s32 r8 __asm__("$8");
|
||||
register u16 r9 __asm__("$9"), r10 __asm__("$10");
|
||||
|
||||
r2 = D_80120200; r3 = D_80120204; r4 = D_80120208; r5 = D_8012020C;
|
||||
r6 = (*(u16 *)&D_80120228); r7 = (*(u16 *)&D_8012022A); r8 = D_80120294; r9 = (*(u16 *)&D_80120298); r10 = (*(u16 *)&D_8012029A);
|
||||
D_80126950 = r2; D_80126954 = r3; D_80126958 = r4; D_8012695C = r5;
|
||||
__asm__ __volatile__("" ::: "memory");
|
||||
D_80126960 = (*(Blk8 *)&D_80120210);
|
||||
r2 = (*(u16 *)&D_80120220); r3 = (*(u16 *)&D_80120222); r4 = (*(u16 *)&D_80120224); r5 = (*(u16 *)&D_80120226);
|
||||
D_80126968 = (*(Blk8 *)&D_80120218);
|
||||
D_80126978 = r6; D_8012697A = r7; D_801269E4 = r8; D_801269E8 = r9; D_801269EA = r10;
|
||||
D_80126970 = r2; D_80126972 = r3; D_80126974 = r4; D_80126976 = r5;
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_8012A2F4() /* dedup: shared engine-core @0x8012A2F4 (src/shared) */
|
||||
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user