mirror of
https://github.com/Druthulu/BFM-decomp
synced 2026-10-02 07:59:52 -04:00
phase-36: S104 s104_e26 — func_8017F438 banked at 0 through the whole-object gate + propagated — 4 levers + pad → 0: bit 31 tested with & 0x80000000 (reorg.c:2799, :1335-1420; combine.c:10831-10845)
This commit is contained in:
Drew T
+183
-183
@@ -1,5 +1,5 @@
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},
|
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|
||||
"seconds": 2.9
|
||||
|
||||
@@ -29495,3 +29495,4 @@
|
||||
{"ts": "2026-09-11 03:53:50", "label": "s104_e22", "rung": "E", "calib": {"head": "4792daaae", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC06_029/ov_SC06_029_jr_8017C954.c", "fn": "func_80181708", "addr": 2149062408, "aliases": null, "header": false, "includers": 0, "nhash_before": "2dc0d8a94d47bd70427d3691f809b71d21f3af2d", "nhash_after": "a9c05827f4ea916c87d3e891198d780adeee94f6", "source": ".run/P36/agents/ov_SC06_029__func_80181708/body.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.214, "objects": ["build/src/ov_SC06_029/ov_SC06_029_jr_8017C954.o"], "before_text": "void func_80181708(int param_1) {\n s16 *psVar1;\n register s16 *psVar2 __asm__(\"$3\"); // !FAKE: pin $3 \u2014 NEEDED DIFFERS (P36 rung B tus10)\n s16 *psVar5;\n s16 sVar4;\n s32 t;\n s32 acc;\n\n psVar1 = (s16 *)D_801DFD8C;\n psVar2 = (s16 *)D_801DFD90;\n *(s32 *)(param_1 + 0x48) = psVar1[0];\n *(s32 *)(param_1 + 0x50) = psVar1[2];\n *(s32 *)(param_1 + 0x3C) = psVar2[0];\n *(s32 *)(param_1 + 0x44) = psVar2[2];\n sVar4 = func_80012CB8(D_801904C6, psVar1[1], 0xC0);\n acc = *(s32 *)(param_1 + 0x4C) + sVar4;\n __asm__(\"\"); // !FAKE: barrier \u2014 NEEDED DIFFERS (P36 rung B tus10)\n t = D_801DFD90;\n *(s32 *)(param_1 + 0x4C) = acc;\n sVar4 = func_80012CB8(D_801904CE, *(s16 *)(t + 2), 0xC0);\n psVar5 = (s16 *)D_801DFD8C;\n *(s32 *)(param_1 + 0x40) += sVar4;\n if (*(s32 *)(param_1 + 0x4C) < psVar5[1])\n *(s32 *)(param_1 + 0x4C) = psVar5[1];\n if (*(s32 *)(param_1 + 0x40) < *(s16 *)(D_801DFD90 + 2))\n *(s32 *)(param_1 + 0x40) = *(s16 *)(D_801DFD90 + 2);\n}\n", "after_text": "void func_80181708(int param_1) {\n typedef struct { s16 vx, vy, vz, pad; } SV;\n typedef struct { u8 pad[0x3C]; s32 x3C; s32 x40; s32 x44; s32 x48; s32 x4C; s32 x50; } OB;\n extern s16 D_801904C6_a[] __asm__(\"D_801904C6\");\n extern s16 D_801904CE_a[] __asm__(\"D_801904CE\");\n SV *p1 = (SV *)D_801DFD8C;\n SV *p2 = (SV *)D_801DFD90;\n\n ((OB *)param_1)->x48 = p1->vx;\n ((OB *)param_1)->x50 = p1->vz;\n ((OB *)param_1)->x3C = p2->vx;\n ((OB *)param_1)->x44 = p2->vz;\n ((OB *)param_1)->x4C += (s16)func_80012CB8(D_801904C6_a[0], p1->vy, 0xC0);\n ((OB *)param_1)->x40 += (s16)func_80012CB8(D_801904CE_a[0], ((SV *)D_801DFD90)->vy, 0xC0);\n if (((OB *)param_1)->x4C < ((SV *)D_801DFD8C)->vy)\n ((OB *)param_1)->x4C = ((SV *)D_801DFD8C)->vy;\n if (((OB *)param_1)->x40 < ((SV *)D_801DFD90)->vy)\n ((OB *)param_1)->x40 = ((SV *)D_801DFD90)->vy;\n}\n"}
|
||||
{"ts": "2026-09-11 03:54:08", "label": "s104_e22", "rung": "E", "calib": {"head": "777dc340f", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC06_029/ov_SC06_029_jr_8017C954.c", "fn": "func_80184EFC", "addr": 2149076732, "aliases": null, "header": false, "includers": 0, "nhash_before": "f4afb0143f5237907b8c9f4c5db580b5386f31fc", "nhash_after": "1e92f42abae93d221a149803fb231ede41e9967c", "source": ".run/P36/agents/ov_SC06_029__func_80184EFC/body.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.216, "objects": ["build/src/ov_SC06_029/ov_SC06_029_jr_8017C954.o"], "before_text": "void func_80184EFC(s32 a0) {\n extern s32 D_80190A08;\n extern u16 D_80190810[];\n register s32 s0 __asm__(\"$16\"); // !FAKE: pin $16 \u2014 NEEDED DIFFERS (P36 rung B tus10)\n register s32 tmp __asm__(\"$2\"); // !FAKE: pin $2 \u2014 NEEDED DIFFERS (P36 rung B tus10)\n s32 ret;\n s32 sub;\n u16 nib;\n s32 p20;\n s32 val;\n s32 sub2;\n\n s0 = a0;\n ret = ((s32 (*)(void))func_8012C1B8)();\n *(s32 *)(s0 + 0x20) = ret;\n if (ret == 0) {\n func_8012CAE4((void *)s0);\n return;\n }\n\n func_8001C214(ret, 0);\n\n /* \u00a7164-29: ONE shared pseudo for the flags temp and the tag accumulator.\n * The WAR edge from `sh tmp` to the tag chain's first def is what pins the\n * whole D_80190A08|0x70000000 build BELOW the flags store (target leaves the\n * `lw 0x20(s0)` load-delay slot a real nop). Split temps let sched1 hoist\n * the tag chain into that slot. The $2 pin fixes the resulting\n * $v0>$v1>$a0 local-alloc rotation. */\n sub = *(s32 *)(s0 + 0x20);\n tmp = *(u16 *)(sub + 0x2C);\n tmp = tmp | 0x10;\n *(u16 *)(sub + 0x2C) = tmp;\n\n tmp = (s32)&D_80190A08;\n tmp = tmp | 0x10000000;\n tmp = tmp | 0x20000000;\n tmp = tmp | 0x40000000;\n *(s32 *)(s0 + 0x58) = tmp;\n if (*(s16 *)(s0 + 0x70) & 0x8000) {\n *(s16 *)(s0 + 0x34) = 1;\n }\n\n nib = *(u16 *)(s0 + 0x70) & 0xF;\n p20 = *(s32 *)(*(s32 *)(s0 + 0x64) + 0x20);\n val = *(u16 *)(p20 + 0x12) + *(u16 *)((u8 *)D_80190810 + nib * 12);\n val = val + 0xE00;\n sub2 = *(s32 *)(s0 + 0x20);\n *(u16 *)(sub2 + 0x12) = val;\n func_8012B2CC(s0);\n\n func_8012B178(s0, (s32)0xFFFC0000);\n\n *(s32 *)(s0 + 0x1C) = 0x20;\n *(u16 *)(s0 + 0x2) = *(u16 *)(s0 + 0x2) + 1;\n}\n", "after_text": "void func_80184EFC(s32 a0) {\n extern s32 D_80190A08;\n extern u16 D_80190810[];\n s32 ret;\n s32 p20;\n\n ret = func_8012C1B8();\n *(s32 *)(a0 + 0x20) = ret;\n if (ret == 0) {\n func_8012CAE4((void *)a0);\n return;\n }\n\n func_8001C214(ret, 0);\n\n *(u16 *)(*(s32 *)(a0 + 0x20) + 0x2C) |= 0x10;\n /* P36 S104 e22: the tag is ONE expression (each `|` a fresh single-set pseudo, so sched1's birthing boost,\n * sched.c:2469-2544, keeps the chain after the flags store) and the flags update is a plain `|=` \u2014 the old\n * shared `tmp` (a two-death pseudo, refused by local-alloc.c:472) needed a $2 pin; the `s0 = a0` copy needed $16. */\n *(s32 *)(a0 + 0x58) = (s32)&D_80190A08 | 0x10000000 | 0x20000000 | 0x40000000;\n if (*(s16 *)(a0 + 0x70) & 0x8000) {\n *(s16 *)(a0 + 0x34) = 1;\n }\n\n p20 = *(s32 *)(*(s32 *)(a0 + 0x64) + 0x20);\n *(u16 *)(*(s32 *)(a0 + 0x20) + 0x12) =\n *(u16 *)(p20 + 0x12) + D_80190810[(*(u16 *)(a0 + 0x70) & 0xF) * 6] + 0xE00;\n func_8012B2CC(a0);\n\n func_8012B178(a0, (s32)0xFFFC0000);\n\n *(s32 *)(a0 + 0x1C) = 0x20;\n *(u16 *)(a0 + 0x2) += 1;\n}\n"}
|
||||
{"ts": "2026-09-11 03:58:27", "label": "s104_e26", "rung": "E", "calib": {"head": "2b9250a50", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC06_010/ov_SC06_010_jr_8017A4AC.c", "fn": "func_8017F024", "addr": 2149052452, "aliases": null, "header": false, "includers": 0, "nhash_before": "e340c91ad873a18326eefb51a3776cb29f8a3eb1", "nhash_after": "822b07f21db52edbd1d0af803423038e7b99d558", "source": ".run/P36/agents/ov_SC06_010__func_8017F024/body.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.323, "objects": ["build/src/ov_SC06_010/ov_SC06_010_jr_8017A4AC.o"], "before_text": "void func_8017F024(s32 a0) {\n register s32 *p __asm__(\"$2\"); // !FAKE: pin $2 \u2014 NEEDED DIFFERS (P36 rung B tus7)\n s32 self;\n\n D_8018AFBC[*(u16 *)(a0 + 2)]();\n if (*(u16 *)a0 != 0) {\n __asm__ __volatile__(\"\" : \"=r\"(self) : \"0\"(a0)); // !FAKE: launder \u2014 NEEDED DIFFERS (P36 rung B tus7)\n p = *(s32 **)(a0 + 0x20);\n p[1] |= 0x80000000;\n func_8012B2CC(self);\n }\n}\n", "after_text": "void func_8017F024(s32 a0) {\n s32 *p;\n\n /* The table's handlers take the actor (func_8017EE3C(s32 a0) is entry 1): passing it keeps a second set of $a0\n * in the RTL (cse deletes the copy \u2014 $a0 still holds the parameter), so the later argument copy is not a\n * \"birthing\" insn for sched1 (sched.c:2469-2545) and stays at the top of the block, where it keeps the mask\n * constant out of $a0 (P36 S104 e26). */\n ((void (*)(s32))D_8018AFBC[*(u16 *)(a0 + 2)])(a0);\n if (*(u16 *)a0 != 0) {\n p = *(s32 **)(a0 + 0x20);\n p[1] |= 0x80000000;\n func_8012B2CC(a0);\n }\n}\n"}
|
||||
{"ts": "2026-09-11 03:58:49", "label": "s104_e26", "rung": "E", "calib": {"head": "195dee8a0", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC06_010/ov_SC06_010_jr_8017A4AC.c", "fn": "func_8017F438", "addr": 2149053496, "aliases": null, "header": false, "includers": 0, "nhash_before": "05f1452bec16a536933fb31d6e32f21d7323884b", "nhash_after": "450e596bc714081bfdec0100740a98e904d40c17", "source": ".run/P36/agents/ov_SC06_010__func_8017F438/body.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.3, "objects": ["build/src/ov_SC06_010/ov_SC06_010_jr_8017A4AC.o"], "before_text": "void func_8017F438(s32 param_1) {\n u8 *s0 = (u8 *)param_1;\n s32 pad_[4];\n s32 t1;\n s32 t2;\n s32 p;\n s32 q;\n u32 uVar1;\n\n t1 = *(s16 *)(s0 + 6);\n t2 = *(s16 *)(s0 + 0xA);\n if (t1 * t1 + (t2 + 0x482) * (t2 + 0x482) > 0x1323F) {\n func_8012ADE4(param_1);\n *(s32 *)(s0 + 0x14) = 0;\n }\n\n func_8002D4C8(0xB32, 0);\n\n if (*(u16 *)s0 != 0) {\n p = *(s32 *)(s0 + 0xCC);\n *(u16 *)(p + 0x8) = *(u16 *)(s0 + 0x6);\n *(u16 *)(p + 0xA) = *(u16 *)(s0 + 0xA);\n *(u16 *)(p + 0xC) = *(u16 *)(s0 + 0xE);\n *(u16 *)(p + 0x10) = *(u16 *)(*(s32 *)(s0 + 0x20) + 0x10);\n *(u16 *)(p + 0x12) = *(u16 *)(*(s32 *)(s0 + 0x20) + 0x12) + *(u16 *)(s0 + 0xFC);\n *(u16 *)(p + 0x14) = *(u16 *)(*(s32 *)(s0 + 0x20) + 0x14);\n q = *(s32 *)(s0 + 0x20);\n if (*(s32 *)(q + 4) < 0) {\n register u32 val __asm__(\"$2\"); // !FAKE: pin $2 \u2014 NEEDED DIFFERS (P36 rung B tus7)\n val = *(u32 *)(p + 4);\n uVar1 = val | 0x80000000;\n } else {\n __asm__ __volatile__(\"\"); // !FAKE: barrier \u2014 NEEDED DIFFERS (P36 rung B tus7)\n uVar1 = *(u32 *)(p + 4) & 0x7FFFFFFF;\n }\n *(u32 *)(p + 4) = uVar1;\n\n p = *(s32 *)(s0 + 0xD0);\n *(u16 *)(p + 0x8) = *(u16 *)(s0 + 0x6);\n *(u16 *)(p + 0xA) = *(u16 *)(s0 + 0xA);\n *(u16 *)(p + 0xC) = *(u16 *)(s0 + 0xE);\n *(u16 *)(p + 0x10) = *(u16 *)(*(s32 *)(s0 + 0x20) + 0x10);\n *(u16 *)(p + 0x12) = *(u16 *)(*(s32 *)(s0 + 0x20) + 0x12) + *(u16 *)(s0 + 0xFE);\n *(u16 *)(p + 0x14) = *(u16 *)(*(s32 *)(s0 + 0x20) + 0x14);\n q = *(s32 *)(s0 + 0x20);\n if (*(s32 *)(q + 4) < 0) {\n register u32 val __asm__(\"$2\"); // !FAKE: pin $2 \u2014 NEEDED DIFFERS (P36 rung B tus7)\n val = *(u32 *)(p + 4);\n uVar1 = val | 0x80000000;\n } else {\n __asm__ __volatile__(\"\"); // !FAKE: barrier \u2014 NEEDED DIFFERS (P36 rung B tus7)\n uVar1 = *(u32 *)(p + 4) & 0x7FFFFFFF;\n }\n *(u32 *)(p + 4) = uVar1;\n }\n}\n", "after_text": "void func_8017F438(s32 param_1) {\n u8 *s0 = (u8 *)param_1;\n s32 t1;\n s32 t2;\n s32 p;\n\n t1 = *(s16 *)(s0 + 6);\n t2 = *(s16 *)(s0 + 0xA);\n if (t1 * t1 + (t2 + 0x482) * (t2 + 0x482) > 0x1323F) {\n func_8012ADE4(param_1);\n *(s32 *)(s0 + 0x14) = 0;\n }\n\n func_8002D4C8(0xB32, 0);\n\n if (*(u16 *)s0 != 0) {\n /* Copy the model's position/rotation into both attached objects and mirror the model's bit 31 into theirs.\n * The bit is TESTED with the mask (not `< 0`): the mask register is loaded before the branch, cse reuses it\n * for the `|=` (so the store's constant sits in the branch delay slot), and combine's sign test leaves a\n * `(use)` of the dead AND result that reload gives a stack slot \u2014 the frame's 16 bytes (P36 S104 e26). */\n p = *(s32 *)(s0 + 0xCC);\n *(u16 *)(p + 0x8) = *(u16 *)(s0 + 0x6);\n *(u16 *)(p + 0xA) = *(u16 *)(s0 + 0xA);\n *(u16 *)(p + 0xC) = *(u16 *)(s0 + 0xE);\n *(u16 *)(p + 0x10) = *(u16 *)(*(s32 *)(s0 + 0x20) + 0x10);\n *(u16 *)(p + 0x12) = *(u16 *)(*(s32 *)(s0 + 0x20) + 0x12) + *(u16 *)(s0 + 0xFC);\n *(u16 *)(p + 0x14) = *(u16 *)(*(s32 *)(s0 + 0x20) + 0x14);\n if (*(u32 *)(*(s32 *)(s0 + 0x20) + 4) & 0x80000000) {\n *(u32 *)(p + 4) |= 0x80000000;\n } else {\n *(u32 *)(p + 4) &= 0x7FFFFFFF;\n }\n\n p = *(s32 *)(s0 + 0xD0);\n *(u16 *)(p + 0x8) = *(u16 *)(s0 + 0x6);\n *(u16 *)(p + 0xA) = *(u16 *)(s0 + 0xA);\n *(u16 *)(p + 0xC) = *(u16 *)(s0 + 0xE);\n *(u16 *)(p + 0x10) = *(u16 *)(*(s32 *)(s0 + 0x20) + 0x10);\n *(u16 *)(p + 0x12) = *(u16 *)(*(s32 *)(s0 + 0x20) + 0x12) + *(u16 *)(s0 + 0xFE);\n *(u16 *)(p + 0x14) = *(u16 *)(*(s32 *)(s0 + 0x20) + 0x14);\n if (*(u32 *)(*(s32 *)(s0 + 0x20) + 4) & 0x80000000) {\n *(u32 *)(p + 4) |= 0x80000000;\n } else {\n *(u32 *)(p + 4) &= 0x7FFFFFFF;\n }\n }\n}\n"}
|
||||
|
||||
@@ -5506,12 +5506,9 @@ extern void func_8002D4C8(s32 a0, s32 a1);
|
||||
|
||||
void func_8017F438(s32 param_1) {
|
||||
u8 *s0 = (u8 *)param_1;
|
||||
s32 pad_[4];
|
||||
s32 t1;
|
||||
s32 t2;
|
||||
s32 p;
|
||||
s32 q;
|
||||
u32 uVar1;
|
||||
|
||||
t1 = *(s16 *)(s0 + 6);
|
||||
t2 = *(s16 *)(s0 + 0xA);
|
||||
@@ -5523,6 +5520,10 @@ void func_8017F438(s32 param_1) {
|
||||
func_8002D4C8(0xB32, 0);
|
||||
|
||||
if (*(u16 *)s0 != 0) {
|
||||
/* Copy the model's position/rotation into both attached objects and mirror the model's bit 31 into theirs.
|
||||
* The bit is TESTED with the mask (not `< 0`): the mask register is loaded before the branch, cse reuses it
|
||||
* for the `|=` (so the store's constant sits in the branch delay slot), and combine's sign test leaves a
|
||||
* `(use)` of the dead AND result that reload gives a stack slot — the frame's 16 bytes (P36 S104 e26). */
|
||||
p = *(s32 *)(s0 + 0xCC);
|
||||
*(u16 *)(p + 0x8) = *(u16 *)(s0 + 0x6);
|
||||
*(u16 *)(p + 0xA) = *(u16 *)(s0 + 0xA);
|
||||
@@ -5530,16 +5531,11 @@ void func_8017F438(s32 param_1) {
|
||||
*(u16 *)(p + 0x10) = *(u16 *)(*(s32 *)(s0 + 0x20) + 0x10);
|
||||
*(u16 *)(p + 0x12) = *(u16 *)(*(s32 *)(s0 + 0x20) + 0x12) + *(u16 *)(s0 + 0xFC);
|
||||
*(u16 *)(p + 0x14) = *(u16 *)(*(s32 *)(s0 + 0x20) + 0x14);
|
||||
q = *(s32 *)(s0 + 0x20);
|
||||
if (*(s32 *)(q + 4) < 0) {
|
||||
register u32 val __asm__("$2"); // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B tus7)
|
||||
val = *(u32 *)(p + 4);
|
||||
uVar1 = val | 0x80000000;
|
||||
if (*(u32 *)(*(s32 *)(s0 + 0x20) + 4) & 0x80000000) {
|
||||
*(u32 *)(p + 4) |= 0x80000000;
|
||||
} else {
|
||||
__asm__ __volatile__(""); // !FAKE: barrier — NEEDED DIFFERS (P36 rung B tus7)
|
||||
uVar1 = *(u32 *)(p + 4) & 0x7FFFFFFF;
|
||||
*(u32 *)(p + 4) &= 0x7FFFFFFF;
|
||||
}
|
||||
*(u32 *)(p + 4) = uVar1;
|
||||
|
||||
p = *(s32 *)(s0 + 0xD0);
|
||||
*(u16 *)(p + 0x8) = *(u16 *)(s0 + 0x6);
|
||||
@@ -5548,16 +5544,11 @@ void func_8017F438(s32 param_1) {
|
||||
*(u16 *)(p + 0x10) = *(u16 *)(*(s32 *)(s0 + 0x20) + 0x10);
|
||||
*(u16 *)(p + 0x12) = *(u16 *)(*(s32 *)(s0 + 0x20) + 0x12) + *(u16 *)(s0 + 0xFE);
|
||||
*(u16 *)(p + 0x14) = *(u16 *)(*(s32 *)(s0 + 0x20) + 0x14);
|
||||
q = *(s32 *)(s0 + 0x20);
|
||||
if (*(s32 *)(q + 4) < 0) {
|
||||
register u32 val __asm__("$2"); // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B tus7)
|
||||
val = *(u32 *)(p + 4);
|
||||
uVar1 = val | 0x80000000;
|
||||
if (*(u32 *)(*(s32 *)(s0 + 0x20) + 4) & 0x80000000) {
|
||||
*(u32 *)(p + 4) |= 0x80000000;
|
||||
} else {
|
||||
__asm__ __volatile__(""); // !FAKE: barrier — NEEDED DIFFERS (P36 rung B tus7)
|
||||
uVar1 = *(u32 *)(p + 4) & 0x7FFFFFFF;
|
||||
*(u32 *)(p + 4) &= 0x7FFFFFFF;
|
||||
}
|
||||
*(u32 *)(p + 4) = uVar1;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user