mirror of
https://github.com/Druthulu/BFM-decomp
synced 2026-10-03 00:05:11 -04:00
refactor(fleet): convert 11 self-contained verbatim units to stubs
The second tranche: every unit in config/verbatim_manifest.json whose disposition says decompile-it and whose unit is SELF-CONTAINED (one row, so the unit_entry is the function itself, not a fragment). 6 in main's src/800c.c plus func_80185810 (ov_SC03_105, 489 ins), func_8017DC80 (ov_SC07_002, 346), func_80181E04 (ov_SC01_001, 269), func_80181828 (ov_SC05_005) and func_8017D810 (ov_SC06_032). Byte-neutral, verified per binary: main 143dbb89, ov_SC03_105 d305ff6d, ov_SC07_002 fad71342, ov_SC01_001 a8e49bc0, ov_SC05_005 452897fc, ov_SC06_032 af117efb. Checked FIRST that none sits in a LINKED subseg — several carry SDK-shaped names and a draft written into a linked subseg gates GREEN while wrong. NOT converted: the 21 multi-row DECOMPILE-AS-PARENT units. Their rows are FRAGMENTS of a larger unit, and converting a fragment to its own stub would invite drafting something that is not an independent function. That needs a parent-unit tool, not a per-function one. Still skipped: ov_SC03_107:func_8017D878, a deliberate §265 bank per the cookbook addendum (address-taken use forces a void(void) declaration the real body contradicts).
This commit is contained in:
Drew T
+6
-213
@@ -1825,42 +1825,7 @@ __asm__(
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".end\tSYS_OBJ_18AC\n"
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);
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__asm__(
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".text\n"
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".align\t2\n"
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".globl\tfunc_8005AB00\n"
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".ent\tfunc_8005AB00\n"
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"func_8005AB00:\n"
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".frame\t$sp,0,$31\n"
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".mask\t0x00000000,0\n"
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".fmask\t0x00000000,0\n"
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".set\tnoreorder\n"
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"lui $v0, %hi(D_80072788)\n"
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"lbu $v0, %lo(D_80072788)($v0)\n"
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"nop\n"
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"addiu $v0, $v0, -1\n"
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"sltiu $v0, $v0, 2\n"
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"beqz $v0, .L8005AB38\n"
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"nop\n"
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"beqz $a1, .L8005AB28\n"
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"lui $v1, 57600\n"
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"ori $v1, $v1, 2048\n"
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".L8005AB28:\n"
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"beqz $a0, SYS_OBJ_191C\n"
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"andi $v0, $a2, 10239\n"
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"j SYS_OBJ_191C\n"
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"ori $v0, $v0, 4096\n"
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".L8005AB38:\n"
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"beqz $a1, .L8005AB44\n"
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"lui $v1, 57600\n"
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"ori $v1, $v1, 512\n"
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".L8005AB44:\n"
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"beqz $a0, SYS_OBJ_191C\n"
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"andi $v0, $a2, 2559\n"
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"ori $v0, $v0, 1024\n"
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".set\treorder\n"
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".end\tfunc_8005AB00\n"
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);
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INCLUDE_ASM("asm/nonmatchings/800c", func_8005AB00);
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s32 SYS_OBJ_191C(s32 a0, s32 a1, s32 a2, s32 a3) {
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register s32 v0 __asm__("$2");
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@@ -2071,33 +2036,7 @@ s32 SYS_OBJ_1AA4(s32 a0, s32 a1, s32 a2, s32 a3) {
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return v0;
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}
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__asm__(
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".text\n"
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".align\t2\n"
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".globl\tfunc_8005ACF0\n"
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".ent\tfunc_8005ACF0\n"
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"func_8005ACF0:\n"
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".frame\t$sp,0,$31\n"
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".mask\t0x00000000,0\n"
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".fmask\t0x00000000,0\n"
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".set\tnoreorder\n"
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"lui $2, %hi(D_80072788)\n"
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"lbu $2, %lo(D_80072788)($2)\n"
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"nop\n"
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"addiu $2, $2, -1\n"
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"sltiu $2, $2, 2\n"
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"bnez $2, 1f\n"
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" andi $3, $5, 0xfff\n"
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"andi $3, $5, 0x7ff\n"
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"sll $3, $3, 11\n"
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"j SYS_OBJ_1AF0\n"
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" andi $2, $4, 0x7ff\n"
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"1:\n"
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"sll $3, $3, 12\n"
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"andi $2, $4, 0xfff\n"
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".set\treorder\n"
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".end\tfunc_8005ACF0\n"
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);
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INCLUDE_ASM("asm/nonmatchings/800c", func_8005ACF0);
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s32 SYS_OBJ_1AF0(void) {
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register s32 r_v0 __asm__("v0");
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@@ -2106,47 +2045,7 @@ s32 SYS_OBJ_1AF0(void) {
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return r_v1 | r_v0;
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}
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__asm__(
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".text\n"
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".align\t2\n"
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".globl\tfunc_8005AD34\n"
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".ent\tfunc_8005AD34\n"
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"func_8005AD34:\n"
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" .set\tnoreorder\n"
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" bnez $a0, .L8005AD44\n"
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" addiu $sp, $sp, -16\n"
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" j SYS_OBJ_1B78\n"
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" addu $v0, $zero, $zero\n"
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".L8005AD44:\n"
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" lbu $a1, 0($a0)\n"
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" nop\n"
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" srl $a1, $a1, 3\n"
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" sw $a1, 0($sp)\n"
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" lh $a2, 4($a0)\n"
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" nop\n"
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" negu $a2, $a2\n"
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" andi $a2, $a2, 0xFF\n"
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" sra $a2, $a2, 3\n"
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" sw $a2, 8($sp)\n"
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" lbu $v0, 2($a0)\n"
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" sll $a1, $a1, 10\n"
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" srl $v0, $v0, 3\n"
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" sw $v0, 4($sp)\n"
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" sll $v0, $v0, 15\n"
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" lh $v1, 6($a0)\n"
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" lui $a0, 0xe200\n"
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" or $a1, $a1, $a0\n"
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" or $v0, $v0, $a1\n"
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" negu $v1, $v1\n"
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" andi $v1, $v1, 0xFF\n"
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" sra $v1, $v1, 3\n"
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" sll $a0, $v1, 5\n"
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" or $v0, $v0, $a0\n"
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" or $v0, $v0, $a2\n"
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" sw $v1, 12($sp)\n"
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".set\treorder\n"
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".end\tfunc_8005AD34\n"
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);
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INCLUDE_ASM("asm/nonmatchings/800c", func_8005AD34);
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void SYS_OBJ_1B78(void) {
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__asm__ __volatile__("addiu\t$sp, $sp, 0x10");
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@@ -3485,46 +3384,9 @@ __asm__(
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".end\tSYS_OBJ_2C6C\n"
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);
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__asm__(
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".text\n"
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".align\t2\n"
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".globl\tfunc_8005BED8\n"
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".ent\tfunc_8005BED8\n"
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".frame\t$sp,24,$31\n"
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".mask\t0x80010000,-4\n"
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".fmask\t0x00000000,0\n"
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".set\tnoreorder\n"
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"func_8005BED8:\n"
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"addiu $sp, $sp, -24\n"
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"sw $ra, 20($sp)\n"
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"bnez $a0, .L8005BF8C\n"
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" sw $s0, 16($sp)\n"
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"jal func_8005C020\n"
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" nop\n"
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"j SYS_OBJ_2CDC\n"
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" nop\n"
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".set\treorder\n"
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".end\tfunc_8005BED8\n"
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);
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INCLUDE_ASM("asm/nonmatchings/800c", func_8005BED8);
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__asm__(
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".text\n"
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".align\t2\n"
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".globl\tSYS_OBJ_2CC4\n"
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".type\tSYS_OBJ_2CC4, @function\n"
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".ent\tSYS_OBJ_2CC4\n"
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"SYS_OBJ_2CC4:\n"
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".set\tnoreorder\n"
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" jal func_8005BA90\n"
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" nop\n"
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" jal func_8005C054\n"
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" nop\n"
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" bnez $v0, SYS_OBJ_2DD8\n"
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" addiu $v0, $zero, -1\n"
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".set\treorder\n"
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".size\tSYS_OBJ_2CC4, . - SYS_OBJ_2CC4\n"
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".end\tSYS_OBJ_2CC4\n"
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);
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INCLUDE_ASM("asm/nonmatchings/800c", SYS_OBJ_2CC4);
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/* SYS_OBJ_2CDC: no epilogue (falls into the shared SYS_OBJ_2DD8 tail), and its two "exit"
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* points are raw `j` jumps into SYS_OBJ_2CC4 / SYS_OBJ_2DD8 with live values in $v0/$s0 and
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@@ -3819,76 +3681,7 @@ __asm__(
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* is unchanged: func_8005C1C0 @0x8005C1C0 (0xD4 bytes) -> SYS_OBJ_3060 @0x8005C294 ->
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* func_8005C29C @0x8005C29C.
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*/
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__asm__(
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".text\n"
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".align\t2\n"
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".globl\tfunc_8005C1C0\n"
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".ent\tfunc_8005C1C0\n"
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"func_8005C1C0:\n"
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".frame\t$sp,0,$31\n"
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".mask\t0x00000000,0\n"
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".fmask\t0x00000000,0\n"
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".set\tnoreorder\n"
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"lui $3, 0x1000\n"
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"lui $2, %hi(D_8007285C)\n"
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"lw $2, %lo(D_8007285C)($2)\n"
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"ori $3, $3, 7\n"
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"sw $3, 0($2)\n"
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"lui $5, %hi(D_80072858)\n"
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"lw $5, %lo(D_80072858)($5)\n"
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"lui $3, 0xff\n"
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"lw $2, 0($5)\n"
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"ori $3, $3, 0xffff\n"
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"and $2, $2, $3\n"
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"addiu $3, $0, 2\n"
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"beq $2, $3, .L8005C268\n"
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" lui $3, 0xe100\n"
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"lui $2, %hi(D_8007285C)\n"
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"lw $2, %lo(D_8007285C)($2)\n"
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"nop\n"
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"lw $2, 0($2)\n"
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"ori $3, $3, 0x1000\n"
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"andi $2, $2, 0x3fff\n"
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"or $2, $2, $3\n"
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"sw $2, 0($5)\n"
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"lui $2, %hi(D_80072858)\n"
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"lw $2, %lo(D_80072858)($2)\n"
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"lui $3, %hi(D_8007285C)\n"
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"lw $3, %lo(D_8007285C)($3)\n"
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"lw $2, 0($2)\n"
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"lw $2, 0($3)\n"
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"nop\n"
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"andi $2, $2, 0x1000\n"
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"bnez $2, .L8005C248\n"
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" andi $2, $4, 8\n"
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"j SYS_OBJ_3060\n"
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" addu $2, $0, $0\n"
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".L8005C248:\n"
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"bnez $2, .L8005C258\n"
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" lui $2, 0x2000\n"
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"j SYS_OBJ_3060\n"
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" addiu $2, $0, 1\n"
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".L8005C258:\n"
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"ori $2, $2, 0x504\n"
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"sw $2, 0($3)\n"
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"j SYS_OBJ_3060\n"
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" addiu $2, $0, 2\n"
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".L8005C268:\n"
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"andi $2, $4, 8\n"
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"beqz $2, .L8005C290\n"
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" lui $4, 0x900\n"
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"ori $4, $4, 1\n"
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"lui $3, %hi(D_8007285C)\n"
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"lw $3, %lo(D_8007285C)($3)\n"
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"addiu $2, $0, 4\n"
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"sw $4, 0($3)\n"
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"j SYS_OBJ_3060\n"
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"nop\n"
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".L8005C290:\n"
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"addiu $2, $0, 3\n"
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".set\treorder\n"
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".end\tfunc_8005C1C0\n"
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);
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INCLUDE_ASM("asm/nonmatchings/800c", func_8005C1C0);
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void SYS_OBJ_3060(void) {
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}
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@@ -5999,290 +5999,7 @@ void func_80181A4C(void)
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}
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__asm__(".text\n.align 2\n.globl func_80181E04\n.ent\tfunc_80181E04\n"
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"func_80181E04:\n.frame $sp,88,$31\n.mask 0x80000000,-8\n.fmask 0,0\n"
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".set\tnoreorder\n"
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".set noat\n"
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"addiu $sp, $sp, -88\n"
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"lui $a0, %hi(D_801F3168)\n"
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"addiu $a0, $a0, %lo(D_801F3168)\n"
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"sw $ra, 80($sp)\n"
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"jal func_800547D8\n"
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"addiu $a1, $sp, 16\n"
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"jal func_80052E38\n"
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"addiu $a0, $sp, 16\n"
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"addiu $t8, $sp, 48\n"
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"addiu $t3, $sp, 56\n"
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"addiu $t7, $sp, 68\n"
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"lui $t2, 255\n"
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"ori $t2, $t2, 65535\n"
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"lui $t5, 65280\n"
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"lui $t1, %hi(D_801EDA44)\n"
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"addiu $t1, $t1, %lo(D_801EDA44)\n"
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"addu $a2, $zero, $zero\n"
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"lui $v1, %hi(D_800A6610)\n"
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"addiu $v1, $v1, %lo(D_800A6610)\n"
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"lui $v0, %hi(D_800B9A02)\n"
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"lhu $v0, %lo(D_800B9A02)($v0)\n"
|
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"lui $t0, %hi(D_800A5E60)\n"
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"lw $t0, %lo(D_800A5E60)($t0)\n"
|
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"sll $v0, $v0, 14\n"
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"addu $t6, $v0, $v1\n"
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"addiu $a3, $t0, 18\n"
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".L80181E6C:\n"
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"lw $v0, 0($t1)\n"
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"nop\n"
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"beqz $v0, .L80182208\n"
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"nop\n"
|
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"lui $at, %hi(D_801EDA4E)\n"
|
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"addu $at, $at, $a2\n"
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"lhu $v0, %lo(D_801EDA4E)($at)\n"
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"nop\n"
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"sh $v0, 48($sp)\n"
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"lui $at, %hi(D_801EDA52)\n"
|
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"addu $at, $at, $a2\n"
|
||||
"lhu $v0, %lo(D_801EDA52)($at)\n"
|
||||
"nop\n"
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"sh $v0, 50($sp)\n"
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"lui $at, %hi(D_801EDA56)\n"
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"addu $at, $at, $a2\n"
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"lhu $v0, %lo(D_801EDA56)($at)\n"
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"nop\n"
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"sh $v0, 52($sp)\n"
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"lui $at, %hi(D_801EDA72)\n"
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"addu $at, $at, $a2\n"
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"lhu $v0, %lo(D_801EDA72)($at)\n"
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"nop\n"
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||||
"sh $v0, 56($sp)\n"
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"lui $at, %hi(D_801EDA76)\n"
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"addu $at, $at, $a2\n"
|
||||
"lhu $v0, %lo(D_801EDA76)($at)\n"
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||||
"nop\n"
|
||||
"sh $v0, 58($sp)\n"
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||||
"lui $at, %hi(D_801EDA7A)\n"
|
||||
"addu $at, $at, $a2\n"
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||||
"lhu $v0, %lo(D_801EDA7A)($at)\n"
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||||
"nop\n"
|
||||
"sh $v0, 60($sp)\n"
|
||||
"lui $at, %hi(D_801EDA4C)\n"
|
||||
"addu $at, $at, $a2\n"
|
||||
"lw $v0, %lo(D_801EDA4C)($at)\n"
|
||||
"lui $at, %hi(D_801EDA7C)\n"
|
||||
"addu $at, $at, $a2\n"
|
||||
"lw $a0, %lo(D_801EDA7C)($at)\n"
|
||||
"lui $at, %hi(D_801EDA50)\n"
|
||||
"addu $at, $at, $a2\n"
|
||||
"lw $v1, %lo(D_801EDA50)($at)\n"
|
||||
"lui $at, %hi(D_801EDA80)\n"
|
||||
"addu $at, $at, $a2\n"
|
||||
"lw $a1, %lo(D_801EDA80)($at)\n"
|
||||
"addu $v0, $v0, $a0\n"
|
||||
"lui $at, %hi(D_801EDA4C)\n"
|
||||
"addu $at, $at, $a2\n"
|
||||
"sw $v0, %lo(D_801EDA4C)($at)\n"
|
||||
"lui $at, %hi(D_801EDA54)\n"
|
||||
"addu $at, $at, $a2\n"
|
||||
"lw $v0, %lo(D_801EDA54)($at)\n"
|
||||
"addu $v1, $v1, $a1\n"
|
||||
"lui $at, %hi(D_801EDA50)\n"
|
||||
"addu $at, $at, $a2\n"
|
||||
"sw $v1, %lo(D_801EDA50)($at)\n"
|
||||
"lui $at, %hi(D_801EDA84)\n"
|
||||
"addu $at, $at, $a2\n"
|
||||
"lw $v1, %lo(D_801EDA84)($at)\n"
|
||||
"lui $at, %hi(D_801EDA48)\n"
|
||||
"addu $at, $at, $a2\n"
|
||||
"lw $a0, %lo(D_801EDA48)($at)\n"
|
||||
"addu $v0, $v0, $v1\n"
|
||||
"lui $at, %hi(D_801EDA54)\n"
|
||||
"addu $at, $at, $a2\n"
|
||||
"sw $v0, %lo(D_801EDA54)($at)\n"
|
||||
"bnez $a0, .L80182000\n"
|
||||
"addiu $v0, $a0, -1\n"
|
||||
"lui $at, %hi(D_801EDA70)\n"
|
||||
"addu $at, $at, $a2\n"
|
||||
"lw $v0, %lo(D_801EDA70)($at)\n"
|
||||
"lui $at, %hi(D_801EDA7C)\n"
|
||||
"addu $at, $at, $a2\n"
|
||||
"lw $v1, %lo(D_801EDA7C)($at)\n"
|
||||
"lui $at, %hi(D_801EDA80)\n"
|
||||
"addu $at, $at, $a2\n"
|
||||
"lw $a0, %lo(D_801EDA80)($at)\n"
|
||||
"lui $at, %hi(D_801EDA84)\n"
|
||||
"addu $at, $at, $a2\n"
|
||||
"lw $a1, %lo(D_801EDA84)($at)\n"
|
||||
"addu $v0, $v0, $v1\n"
|
||||
"lui $at, %hi(D_801EDA70)\n"
|
||||
"addu $at, $at, $a2\n"
|
||||
"sw $v0, %lo(D_801EDA70)($at)\n"
|
||||
"lui $at, %hi(D_801EDA74)\n"
|
||||
"addu $at, $at, $a2\n"
|
||||
"lw $v0, %lo(D_801EDA74)($at)\n"
|
||||
"lui $at, %hi(D_801EDA78)\n"
|
||||
"addu $at, $at, $a2\n"
|
||||
"lw $v1, %lo(D_801EDA78)($at)\n"
|
||||
"addu $v0, $v0, $a0\n"
|
||||
"addu $v1, $v1, $a1\n"
|
||||
"lui $at, %hi(D_801EDA74)\n"
|
||||
"addu $at, $at, $a2\n"
|
||||
"sw $v0, %lo(D_801EDA74)($at)\n"
|
||||
"lui $at, %hi(D_801EDA78)\n"
|
||||
"addu $at, $at, $a2\n"
|
||||
"sw $v1, %lo(D_801EDA78)($at)\n"
|
||||
"j .L8018200C\n"
|
||||
"nop\n"
|
||||
".L80182000:\n"
|
||||
"lui $at, %hi(D_801EDA48)\n"
|
||||
"addu $at, $at, $a2\n"
|
||||
"sw $v0, %lo(D_801EDA48)($at)\n"
|
||||
".L8018200C:\n"
|
||||
"lui $at, %hi(D_801EDA7C)\n"
|
||||
"addu $at, $at, $a2\n"
|
||||
"lw $v0, %lo(D_801EDA7C)($at)\n"
|
||||
"lui $at, %hi(D_801EDA88)\n"
|
||||
"addu $at, $at, $a2\n"
|
||||
"lw $a0, %lo(D_801EDA88)($at)\n"
|
||||
"lui $at, %hi(D_801EDA80)\n"
|
||||
"addu $at, $at, $a2\n"
|
||||
"lw $v1, %lo(D_801EDA80)($at)\n"
|
||||
"lui $at, %hi(D_801EDA8C)\n"
|
||||
"addu $at, $at, $a2\n"
|
||||
"lw $a1, %lo(D_801EDA8C)($at)\n"
|
||||
"addu $v0, $v0, $a0\n"
|
||||
"lui $at, %hi(D_801EDA7C)\n"
|
||||
"addu $at, $at, $a2\n"
|
||||
"sw $v0, %lo(D_801EDA7C)($at)\n"
|
||||
"lui $at, %hi(D_801EDA84)\n"
|
||||
"addu $at, $at, $a2\n"
|
||||
"lw $v0, %lo(D_801EDA84)($at)\n"
|
||||
"addu $v1, $v1, $a1\n"
|
||||
"lui $at, %hi(D_801EDA80)\n"
|
||||
"addu $at, $at, $a2\n"
|
||||
"sw $v1, %lo(D_801EDA80)($at)\n"
|
||||
"lui $at, %hi(D_801EDA90)\n"
|
||||
"addu $at, $at, $a2\n"
|
||||
"lw $v1, %lo(D_801EDA90)($at)\n"
|
||||
"lui $at, %hi(D_801EDA7C)\n"
|
||||
"addu $at, $at, $a2\n"
|
||||
"lw $a0, %lo(D_801EDA7C)($at)\n"
|
||||
"addu $v0, $v0, $v1\n"
|
||||
"lui $at, %hi(D_801EDA84)\n"
|
||||
"addu $at, $at, $a2\n"
|
||||
"sw $v0, %lo(D_801EDA84)($at)\n"
|
||||
"blez $a0, .L801820B8\n"
|
||||
"nop\n"
|
||||
"lui $at, %hi(D_801EDA4C)\n"
|
||||
"addu $at, $at, $a2\n"
|
||||
"lw $v1, %lo(D_801EDA4C)($at)\n"
|
||||
"lui $at, %hi(D_801EDA58)\n"
|
||||
"addu $at, $at, $a2\n"
|
||||
"lw $v0, %lo(D_801EDA58)($at)\n"
|
||||
"j .L801820D8\n"
|
||||
"slt $v0, $v0, $v1\n"
|
||||
".L801820B8:\n"
|
||||
"lui $at, %hi(D_801EDA4C)\n"
|
||||
"addu $at, $at, $a2\n"
|
||||
"lw $v0, %lo(D_801EDA4C)($at)\n"
|
||||
"lui $at, %hi(D_801EDA58)\n"
|
||||
"addu $at, $at, $a2\n"
|
||||
"lw $v1, %lo(D_801EDA58)($at)\n"
|
||||
"nop\n"
|
||||
"slt $v0, $v0, $v1\n"
|
||||
".L801820D8:\n"
|
||||
"beqz $v0, .L801820EC\n"
|
||||
"nop\n"
|
||||
"lui $at, %hi(D_801EDA44)\n"
|
||||
"addu $at, $at, $a2\n"
|
||||
"sw $zero, %lo(D_801EDA44)($at)\n"
|
||||
".L801820EC:\n"
|
||||
"lw $v0, 0($t1)\n"
|
||||
"nop\n"
|
||||
"beqz $v0, .L80182208\n"
|
||||
"nop\n"
|
||||
"lwc2 $0, 0($t8)\n"
|
||||
"lwc2 $1, 4($t8)\n"
|
||||
"lwc2 $2, 0($t3)\n"
|
||||
"lwc2 $3, 4($t3)\n"
|
||||
"lwc2 $4, 0($t3)\n"
|
||||
"lwc2 $5, 4($t3)\n"
|
||||
"nop\n"
|
||||
"nop\n"
|
||||
"rtpt\n"
|
||||
"addiu $v0, $sp, 64\n"
|
||||
".word 0x484cf800\n"
|
||||
"nop\n"
|
||||
"sw $t4, 0($v0)\n"
|
||||
"lui $v1, 32645\n"
|
||||
"lw $v0, 64($sp)\n"
|
||||
"ori $v1, $v1, 57344\n"
|
||||
"and $v0, $v0, $v1\n"
|
||||
"bnez $v0, .L80182208\n"
|
||||
"addiu $v1, $t0, 12\n"
|
||||
"addiu $v0, $t0, 20\n"
|
||||
"swc2 $12, 0($v1)\n"
|
||||
"swc2 $13, 0($v0)\n"
|
||||
"addiu $v1, $sp, 72\n"
|
||||
"addiu $v0, $sp, 76\n"
|
||||
"swc2 $17, 0($t7)\n"
|
||||
"swc2 $18, 0($v1)\n"
|
||||
"swc2 $19, 0($v0)\n"
|
||||
"lw $v1, 68($sp)\n"
|
||||
"lw $v0, 72($sp)\n"
|
||||
"nop\n"
|
||||
"addu $a1, $v1, $v0\n"
|
||||
"bgez $a1, .L80182184\n"
|
||||
"lui $v1, 57600\n"
|
||||
"addiu $a1, $a1, 7\n"
|
||||
".L80182184:\n"
|
||||
"ori $v1, $v1, 32\n"
|
||||
"addiu $v0, $zero, 5\n"
|
||||
"sb $v0, -15($a3)\n"
|
||||
"addiu $v0, $zero, 82\n"
|
||||
"sb $v0, -7($a3)\n"
|
||||
"addiu $v0, $zero, 224\n"
|
||||
"sb $v0, -9($a3)\n"
|
||||
"addiu $v0, $zero, 136\n"
|
||||
"sb $v0, -8($a3)\n"
|
||||
"addiu $v0, $zero, 64\n"
|
||||
"sb $v0, -2($a3)\n"
|
||||
"addiu $v0, $zero, 96\n"
|
||||
"sb $v0, -1($a3)\n"
|
||||
"addiu $v0, $zero, 16\n"
|
||||
"sw $v1, -14($a3)\n"
|
||||
"sb $zero, -10($a3)\n"
|
||||
"sb $v0, 0($a3)\n"
|
||||
"addiu $a3, $a3, 24\n"
|
||||
"sra $v1, $a1, 3\n"
|
||||
"sll $v1, $v1, 2\n"
|
||||
"addu $v1, $v1, $t6\n"
|
||||
"lw $a0, 0($t0)\n"
|
||||
"lw $v0, 0($v1)\n"
|
||||
"and $a0, $a0, $t5\n"
|
||||
"and $v0, $v0, $t2\n"
|
||||
"or $a0, $a0, $v0\n"
|
||||
"sw $a0, 0($t0)\n"
|
||||
"and $a0, $t0, $t2\n"
|
||||
"lw $v0, 0($v1)\n"
|
||||
"addiu $t0, $t0, 24\n"
|
||||
"and $v0, $v0, $t5\n"
|
||||
"or $v0, $v0, $a0\n"
|
||||
"sw $v0, 0($v1)\n"
|
||||
".L80182208:\n"
|
||||
"addiu $t1, $t1, 80\n"
|
||||
"lui $v0, %hi(D_801F2A44)\n"
|
||||
"addiu $v0, $v0, %lo(D_801F2A44)\n"
|
||||
"slt $v0, $t1, $v0\n"
|
||||
"bnez $v0, .L80181E6C\n"
|
||||
"addiu $a2, $a2, 80\n"
|
||||
"lui $at, %hi(D_800A5E60)\n"
|
||||
"sw $t0, %lo(D_800A5E60)($at)\n"
|
||||
"lw $ra, 80($sp)\n"
|
||||
"addiu $sp, $sp, 88\n"
|
||||
"jr $ra\n"
|
||||
"nop\n"
|
||||
".set at\n"
|
||||
".set reorder\n"
|
||||
".end\tfunc_80181E04\n");
|
||||
INCLUDE_ASM("asm/ov_SC01_001/nonmatchings/ov_SC01_001_jr_8017D2DC", func_80181E04);
|
||||
|
||||
|
||||
extern u8 D_801F2A44[];
|
||||
|
||||
@@ -5243,511 +5243,7 @@ extern u8 D_801BA6B0;
|
||||
extern void func_80185FB4(s32 a0, s32 a1, s32 a2);
|
||||
extern void func_8001F730(s32 a0, void *a1, void *a2);
|
||||
|
||||
__asm__(".text\n.align 2\n.globl func_80185810\n.ent\tfunc_80185810\n"
|
||||
"func_80185810:\n.frame $sp,128,$31\n.mask 0x500F0000,-8\n.fmask 0,0\n"
|
||||
".set\tnoreorder\n"
|
||||
"addiu $sp, $sp, -128\n"
|
||||
"sw $s1, 108($sp)\n"
|
||||
"addu $s1, $a0, $zero\n"
|
||||
"sw $s4, 120($sp)\n"
|
||||
"lui $s4, %hi(D_800AF630)\n"
|
||||
"addiu $s4, $s4, %lo(D_800AF630)\n"
|
||||
"sw $ra, 124($sp)\n"
|
||||
"sw $s3, 116($sp)\n"
|
||||
"sw $s2, 112($sp)\n"
|
||||
"sw $s0, 104($sp)\n"
|
||||
"lw $s3, 0($s1)\n"
|
||||
"lw $a0, 32($s1)\n"
|
||||
"lw $s2, 36($s1)\n"
|
||||
"beqz $a0, .L80185B7C\n"
|
||||
"lui $v0, 128\n"
|
||||
"and $v0, $s3, $v0\n"
|
||||
"beqz $v0, .L801859DC\n"
|
||||
"addiu $v1, $s4, 24\n"
|
||||
"lw $t4, 0($v1)\n"
|
||||
"lw $t5, 4($v1)\n"
|
||||
"ctc2 $t4, $0\n"
|
||||
"ctc2 $t5, $1\n"
|
||||
"lw $t4, 8($v1)\n"
|
||||
"lw $t5, 12($v1)\n"
|
||||
"lw $t6, 16($v1)\n"
|
||||
"ctc2 $t4, $2\n"
|
||||
"ctc2 $t5, $3\n"
|
||||
"ctc2 $t6, $4\n"
|
||||
"lw $v0, 32($a0)\n"
|
||||
"nop\n"
|
||||
"addiu $v0, $v0, 52\n"
|
||||
"lhu $t4, 0($v0)\n"
|
||||
"lhu $t5, 6($v0)\n"
|
||||
"lhu $t6, 12($v0)\n"
|
||||
"mtc2 $t4, $9\n"
|
||||
"mtc2 $t5, $10\n"
|
||||
"mtc2 $t6, $11\n"
|
||||
"nop\n"
|
||||
"nop\n"
|
||||
"mvmva 1, 0, 3, 3, 0\n"
|
||||
"addiu $v0, $sp, 56\n"
|
||||
"mfc2 $t4, $9\n"
|
||||
"mfc2 $t5, $10\n"
|
||||
"mfc2 $t6, $11\n"
|
||||
"sh $t4, 0($v0)\n"
|
||||
"sh $t5, 6($v0)\n"
|
||||
"sh $t6, 12($v0)\n"
|
||||
"lw $v0, 32($s1)\n"
|
||||
"nop\n"
|
||||
"lw $v0, 32($v0)\n"
|
||||
"nop\n"
|
||||
"addiu $v0, $v0, 54\n"
|
||||
"lhu $t4, 0($v0)\n"
|
||||
"lhu $t5, 6($v0)\n"
|
||||
"lhu $t6, 12($v0)\n"
|
||||
"mtc2 $t4, $9\n"
|
||||
"mtc2 $t5, $10\n"
|
||||
"mtc2 $t6, $11\n"
|
||||
"nop\n"
|
||||
"nop\n"
|
||||
"mvmva 1, 0, 3, 3, 0\n"
|
||||
"addiu $v0, $sp, 58\n"
|
||||
"mfc2 $t4, $9\n"
|
||||
"mfc2 $t5, $10\n"
|
||||
"mfc2 $t6, $11\n"
|
||||
"sh $t4, 0($v0)\n"
|
||||
"sh $t5, 6($v0)\n"
|
||||
"sh $t6, 12($v0)\n"
|
||||
"lw $v0, 32($s1)\n"
|
||||
"nop\n"
|
||||
"lw $v0, 32($v0)\n"
|
||||
"nop\n"
|
||||
"addiu $v0, $v0, 56\n"
|
||||
"lhu $t4, 0($v0)\n"
|
||||
"lhu $t5, 6($v0)\n"
|
||||
"lhu $t6, 12($v0)\n"
|
||||
"mtc2 $t4, $9\n"
|
||||
"mtc2 $t5, $10\n"
|
||||
"mtc2 $t6, $11\n"
|
||||
"nop\n"
|
||||
"nop\n"
|
||||
"mvmva 1, 0, 3, 3, 0\n"
|
||||
"addiu $v0, $sp, 60\n"
|
||||
"mfc2 $t4, $9\n"
|
||||
"mfc2 $t5, $10\n"
|
||||
"mfc2 $t6, $11\n"
|
||||
"sh $t4, 0($v0)\n"
|
||||
"sh $t5, 6($v0)\n"
|
||||
"sh $t6, 12($v0)\n"
|
||||
"lw $t4, 20($v1)\n"
|
||||
"lw $t5, 24($v1)\n"
|
||||
"ctc2 $t4, $5\n"
|
||||
"lw $t6, 28($v1)\n"
|
||||
"ctc2 $t5, $6\n"
|
||||
"ctc2 $t6, $7\n"
|
||||
"lw $v0, 32($s1)\n"
|
||||
"nop\n"
|
||||
"lw $v0, 32($v0)\n"
|
||||
"nop\n"
|
||||
"addiu $v0, $v0, 72\n"
|
||||
"lhu $t5, 4($v0)\n"
|
||||
"lhu $t4, 0($v0)\n"
|
||||
"sll $t5, $t5, 16\n"
|
||||
"or $t4, $t4, $t5\n"
|
||||
"mtc2 $t4, $0\n"
|
||||
"lwc2 $1, 8($v0)\n"
|
||||
"nop\n"
|
||||
"nop\n"
|
||||
"mvmva 1, 0, 0, 0, 0\n"
|
||||
"addiu $v0, $sp, 76\n"
|
||||
"swc2 $25, 0($v0)\n"
|
||||
"swc2 $26, 4($v0)\n"
|
||||
"swc2 $27, 8($v0)\n"
|
||||
"j .L80185B28\n"
|
||||
"addiu $v0, $sp, 56\n"
|
||||
".L801859DC:\n"
|
||||
"lw $a0, 32($a0)\n"
|
||||
"addu $a1, $s3, $zero\n"
|
||||
"addiu $s0, $sp, 56\n"
|
||||
"jal func_80185FB4\n"
|
||||
"addu $a2, $s0, $zero\n"
|
||||
"addiu $v1, $s4, 24\n"
|
||||
"lw $t4, 0($v1)\n"
|
||||
"lw $t5, 4($v1)\n"
|
||||
"ctc2 $t4, $0\n"
|
||||
"ctc2 $t5, $1\n"
|
||||
"lw $t4, 8($v1)\n"
|
||||
"lw $t5, 12($v1)\n"
|
||||
"lw $t6, 16($v1)\n"
|
||||
"ctc2 $t4, $2\n"
|
||||
"ctc2 $t5, $3\n"
|
||||
"ctc2 $t6, $4\n"
|
||||
"lhu $t4, 0($s0)\n"
|
||||
"lhu $t5, 6($s0)\n"
|
||||
"lhu $t6, 12($s0)\n"
|
||||
"mtc2 $t4, $9\n"
|
||||
"mtc2 $t5, $10\n"
|
||||
"mtc2 $t6, $11\n"
|
||||
"nop\n"
|
||||
"nop\n"
|
||||
"mvmva 1, 0, 3, 3, 0\n"
|
||||
"mfc2 $t4, $9\n"
|
||||
"mfc2 $t5, $10\n"
|
||||
"mfc2 $t6, $11\n"
|
||||
"sh $t4, 0($s0)\n"
|
||||
"sh $t5, 6($s0)\n"
|
||||
"sh $t6, 12($s0)\n"
|
||||
"addiu $v0, $sp, 58\n"
|
||||
"lhu $t4, 0($v0)\n"
|
||||
"lhu $t5, 6($v0)\n"
|
||||
"lhu $t6, 12($v0)\n"
|
||||
"mtc2 $t4, $9\n"
|
||||
"mtc2 $t5, $10\n"
|
||||
"mtc2 $t6, $11\n"
|
||||
"nop\n"
|
||||
"nop\n"
|
||||
"mvmva 1, 0, 3, 3, 0\n"
|
||||
"mfc2 $t4, $9\n"
|
||||
"mfc2 $t5, $10\n"
|
||||
"mfc2 $t6, $11\n"
|
||||
"sh $t4, 0($v0)\n"
|
||||
"sh $t5, 6($v0)\n"
|
||||
"sh $t6, 12($v0)\n"
|
||||
"addiu $v0, $sp, 60\n"
|
||||
"lhu $t4, 0($v0)\n"
|
||||
"lhu $t5, 6($v0)\n"
|
||||
"lhu $t6, 12($v0)\n"
|
||||
"mtc2 $t4, $9\n"
|
||||
"mtc2 $t5, $10\n"
|
||||
"mtc2 $t6, $11\n"
|
||||
"nop\n"
|
||||
"nop\n"
|
||||
"mvmva 1, 0, 3, 3, 0\n"
|
||||
"mfc2 $t4, $9\n"
|
||||
"mfc2 $t5, $10\n"
|
||||
"mfc2 $t6, $11\n"
|
||||
"sh $t4, 0($v0)\n"
|
||||
"sh $t5, 6($v0)\n"
|
||||
"sh $t6, 12($v0)\n"
|
||||
"lw $t4, 20($v1)\n"
|
||||
"lw $t5, 24($v1)\n"
|
||||
"ctc2 $t4, $5\n"
|
||||
"lw $t6, 28($v1)\n"
|
||||
"ctc2 $t5, $6\n"
|
||||
"ctc2 $t6, $7\n"
|
||||
"addiu $v0, $sp, 76\n"
|
||||
"lhu $t5, 4($v0)\n"
|
||||
"lhu $t4, 0($v0)\n"
|
||||
"sll $t5, $t5, 16\n"
|
||||
"or $t4, $t4, $t5\n"
|
||||
"mtc2 $t4, $0\n"
|
||||
"lwc2 $1, 8($v0)\n"
|
||||
"nop\n"
|
||||
"nop\n"
|
||||
"mvmva 1, 0, 0, 0, 0\n"
|
||||
"swc2 $25, 0($v0)\n"
|
||||
"swc2 $26, 4($v0)\n"
|
||||
"swc2 $27, 8($v0)\n"
|
||||
"addiu $v0, $sp, 56\n"
|
||||
".L80185B28:\n"
|
||||
"lw $t4, 0($v0)\n"
|
||||
"lw $t5, 4($v0)\n"
|
||||
"ctc2 $t4, $0\n"
|
||||
"ctc2 $t5, $1\n"
|
||||
"lw $t4, 8($v0)\n"
|
||||
"lw $t5, 12($v0)\n"
|
||||
"lw $t6, 16($v0)\n"
|
||||
"ctc2 $t4, $2\n"
|
||||
"ctc2 $t5, $3\n"
|
||||
"ctc2 $t6, $4\n"
|
||||
"lw $t4, 20($v0)\n"
|
||||
"lw $t5, 24($v0)\n"
|
||||
"ctc2 $t4, $5\n"
|
||||
"lw $t6, 28($v0)\n"
|
||||
"ctc2 $t5, $6\n"
|
||||
"ctc2 $t6, $7\n"
|
||||
"lw $v0, 32($s1)\n"
|
||||
"nop\n"
|
||||
"lw $v0, 32($v0)\n"
|
||||
"j .L80185BC4\n"
|
||||
"addiu $t0, $v0, 16\n"
|
||||
".L80185B7C:\n"
|
||||
"addiu $v0, $s4, 24\n"
|
||||
"lw $t4, 0($v0)\n"
|
||||
"lw $t5, 4($v0)\n"
|
||||
"ctc2 $t4, $0\n"
|
||||
"ctc2 $t5, $1\n"
|
||||
"lw $t4, 8($v0)\n"
|
||||
"lw $t5, 12($v0)\n"
|
||||
"lw $t6, 16($v0)\n"
|
||||
"ctc2 $t4, $2\n"
|
||||
"ctc2 $t5, $3\n"
|
||||
"ctc2 $t6, $4\n"
|
||||
"lw $t4, 20($v0)\n"
|
||||
"lw $t5, 24($v0)\n"
|
||||
"ctc2 $t4, $5\n"
|
||||
"lw $t6, 28($v0)\n"
|
||||
"ctc2 $t5, $6\n"
|
||||
"ctc2 $t6, $7\n"
|
||||
"addiu $t0, $s1, 4\n"
|
||||
".L80185BC4:\n"
|
||||
"addiu $v0, $s1, 20\n"
|
||||
"lwc2 $0, 0($v0)\n"
|
||||
"lwc2 $1, 4($v0)\n"
|
||||
"nop\n"
|
||||
"nop\n"
|
||||
"rtps\n"
|
||||
"addiu $v0, $sp, 16\n"
|
||||
"swc2 $14, 0($v0)\n"
|
||||
"addiu $v0, $sp, 88\n"
|
||||
"swc2 $19, 0($v0)\n"
|
||||
"lh $v0, 16($sp)\n"
|
||||
"nop\n"
|
||||
"bgez $v0, .L80185C00\n"
|
||||
"nop\n"
|
||||
"negu $v0, $v0\n"
|
||||
".L80185C00:\n"
|
||||
"slti $v0, $v0, 201\n"
|
||||
"beqz $v0, .L80185F90\n"
|
||||
"nop\n"
|
||||
"lh $v0, 18($sp)\n"
|
||||
"nop\n"
|
||||
"bgez $v0, .L80185C20\n"
|
||||
"nop\n"
|
||||
"negu $v0, $v0\n"
|
||||
".L80185C20:\n"
|
||||
"slti $v0, $v0, 161\n"
|
||||
"beqz $v0, .L80185F90\n"
|
||||
"nop\n"
|
||||
"lhu $v0, 12($s1)\n"
|
||||
"lui $at, %hi(D_801BC9B4)\n"
|
||||
"sh $v0, %lo(D_801BC9B4)($at)\n"
|
||||
"lhu $v0, 14($s1)\n"
|
||||
"lui $t1, %hi(D_801BC9B4)\n"
|
||||
"addiu $t1, $t1, %lo(D_801BC9B4)\n"
|
||||
"lui $at, %hi(D_801BC9BC)\n"
|
||||
"sh $v0, %lo(D_801BC9BC)($at)\n"
|
||||
"lw $t4, 0($t1)\n"
|
||||
"lw $t5, 4($t1)\n"
|
||||
"ctc2 $t4, $0\n"
|
||||
"ctc2 $t5, $1\n"
|
||||
"lw $t4, 8($t1)\n"
|
||||
"lw $t5, 12($t1)\n"
|
||||
"lw $t6, 16($t1)\n"
|
||||
"ctc2 $t4, $2\n"
|
||||
"ctc2 $t5, $3\n"
|
||||
"ctc2 $t6, $4\n"
|
||||
"lw $t4, 20($t1)\n"
|
||||
"lw $t5, 24($t1)\n"
|
||||
"ctc2 $t4, $5\n"
|
||||
"lw $t6, 28($t1)\n"
|
||||
"ctc2 $t5, $6\n"
|
||||
"ctc2 $t6, $7\n"
|
||||
"lhu $v0, 8($s2)\n"
|
||||
"lhu $v1, 28($s1)\n"
|
||||
"lw $a0, 88($sp)\n"
|
||||
"addu $v0, $v0, $v1\n"
|
||||
"sh $v0, 40($sp)\n"
|
||||
"lhu $v0, 10($s2)\n"
|
||||
"lhu $v1, 30($s1)\n"
|
||||
"sh $a0, 44($sp)\n"
|
||||
"addu $v0, $v0, $v1\n"
|
||||
"sh $v0, 42($sp)\n"
|
||||
"lbu $v0, 2($s2)\n"
|
||||
"nop\n"
|
||||
"sh $v0, 48($sp)\n"
|
||||
"lbu $v0, 3($s2)\n"
|
||||
"addiu $v1, $sp, 40\n"
|
||||
"sh $a0, 52($sp)\n"
|
||||
"sh $v0, 50($sp)\n"
|
||||
"addiu $v0, $sp, 48\n"
|
||||
"lwc2 $0, 0($v1)\n"
|
||||
"lwc2 $1, 4($v1)\n"
|
||||
"lwc2 $2, 0($v0)\n"
|
||||
"lwc2 $3, 4($v0)\n"
|
||||
"lwc2 $4, 0($v0)\n"
|
||||
"lwc2 $5, 4($v0)\n"
|
||||
"nop\n"
|
||||
"nop\n"
|
||||
"rtpt\n"
|
||||
"addiu $v0, $sp, 24\n"
|
||||
"swc2 $12, 0($v0)\n"
|
||||
"addiu $v0, $sp, 32\n"
|
||||
"swc2 $13, 0($v0)\n"
|
||||
"addiu $v0, $sp, 92\n"
|
||||
"cfc2 $t4, $31\n"
|
||||
"nop\n"
|
||||
"sw $t4, 0($v0)\n"
|
||||
"addiu $v0, $sp, 96\n"
|
||||
"mfc2 $t4, $19\n"
|
||||
"nop\n"
|
||||
"sra $t4, $t4, 2\n"
|
||||
"sw $t4, 0($v0)\n"
|
||||
"lw $v0, 92($sp)\n"
|
||||
"addiu $v1, $zero, -4097\n"
|
||||
"and $v0, $v0, $v1\n"
|
||||
"bnez $v0, .L80185F90\n"
|
||||
"srl $a1, $s3, 24\n"
|
||||
"andi $a1, $a1, 3\n"
|
||||
"lui $s0, %hi(D_800A5E60)\n"
|
||||
"lw $s0, %lo(D_800A5E60)($s0)\n"
|
||||
"sll $v1, $a1, 7\n"
|
||||
"addiu $v0, $s0, 40\n"
|
||||
"lui $at, %hi(D_800A5E60)\n"
|
||||
"sw $v0, %lo(D_800A5E60)($at)\n"
|
||||
"addiu $v0, $zero, 9\n"
|
||||
"sb $v0, 3($s0)\n"
|
||||
"addiu $v0, $zero, 44\n"
|
||||
"sb $v0, 7($s0)\n"
|
||||
"lui $at, 1\n"
|
||||
"addu $at, $s4, $at\n"
|
||||
"lhu $a2, -23598($at)\n"
|
||||
"lhu $a0, 4($s2)\n"
|
||||
"lhu $a3, 6($s2)\n"
|
||||
"addiu $v0, $zero, 46\n"
|
||||
"sb $v0, 7($s0)\n"
|
||||
"srl $v0, $s3, 23\n"
|
||||
"andi $v0, $v0, 96\n"
|
||||
"or $v1, $v1, $v0\n"
|
||||
"andi $v0, $a3, 256\n"
|
||||
"srl $v0, $v0, 4\n"
|
||||
"or $v1, $v1, $v0\n"
|
||||
"andi $v0, $a0, 960\n"
|
||||
"srl $v0, $v0, 6\n"
|
||||
"or $v1, $v1, $v0\n"
|
||||
"andi $v0, $a3, 512\n"
|
||||
"sll $v0, $v0, 2\n"
|
||||
"or $v1, $v1, $v0\n"
|
||||
"andi $v0, $s3, 64\n"
|
||||
"srl $v0, $v0, 6\n"
|
||||
"sll $a2, $a2, 14\n"
|
||||
"sh $v1, 22($s0)\n"
|
||||
"lbu $v1, 7($s0)\n"
|
||||
"andi $a3, $a3, 65535\n"
|
||||
"or $v1, $v1, $v0\n"
|
||||
"sb $v1, 7($s0)\n"
|
||||
"addiu $v1, $zero, 2\n"
|
||||
"lhu $v0, 22($s0)\n"
|
||||
"subu $v1, $v1, $a1\n"
|
||||
"andi $v0, $v0, 15\n"
|
||||
"sll $v0, $v0, 6\n"
|
||||
"subu $a0, $a0, $v0\n"
|
||||
"lui $v0, %hi(D_800A6610)\n"
|
||||
"addiu $v0, $v0, %lo(D_800A6610)\n"
|
||||
"addu $s1, $a2, $v0\n"
|
||||
"lhu $v0, 22($s0)\n"
|
||||
"sllv $a0, $a0, $v1\n"
|
||||
"andi $v0, $v0, 16\n"
|
||||
"beqz $v0, .L80185E14\n"
|
||||
"sb $a0, 12($s0)\n"
|
||||
"addiu $a3, $a3, -256\n"
|
||||
".L80185E14:\n"
|
||||
"lbu $v0, 12($s0)\n"
|
||||
"sb $a3, 13($s0)\n"
|
||||
"lbu $v1, 2($s2)\n"
|
||||
"lbu $a0, 12($s0)\n"
|
||||
"addu $v0, $v0, $v1\n"
|
||||
"lbu $v1, 13($s0)\n"
|
||||
"addiu $v0, $v0, -1\n"
|
||||
"sb $v0, 20($s0)\n"
|
||||
"lbu $v0, 13($s0)\n"
|
||||
"sb $a0, 28($s0)\n"
|
||||
"sb $v1, 21($s0)\n"
|
||||
"lbu $v1, 3($s2)\n"
|
||||
"nop\n"
|
||||
"addu $v0, $v0, $v1\n"
|
||||
"lbu $v1, 20($s0)\n"
|
||||
"addiu $v0, $v0, -1\n"
|
||||
"sb $v0, 29($s0)\n"
|
||||
"lbu $a0, 29($s0)\n"
|
||||
"addiu $v0, $zero, 128\n"
|
||||
"sb $v0, 6($s0)\n"
|
||||
"sb $v0, 5($s0)\n"
|
||||
"sb $v0, 4($s0)\n"
|
||||
"sb $v1, 36($s0)\n"
|
||||
"sb $a0, 37($s0)\n"
|
||||
"lhu $v0, 16($sp)\n"
|
||||
"lhu $v1, 24($sp)\n"
|
||||
"nop\n"
|
||||
"addu $v0, $v0, $v1\n"
|
||||
"sh $v0, 8($s0)\n"
|
||||
"lhu $v0, 18($sp)\n"
|
||||
"lhu $v1, 26($sp)\n"
|
||||
"nop\n"
|
||||
"addu $v0, $v0, $v1\n"
|
||||
"sh $v0, 10($s0)\n"
|
||||
"lhu $v0, 8($s0)\n"
|
||||
"lhu $v1, 32($sp)\n"
|
||||
"nop\n"
|
||||
"addu $v0, $v0, $v1\n"
|
||||
"sh $v0, 16($s0)\n"
|
||||
"lhu $v0, 10($s0)\n"
|
||||
"lhu $a0, 34($sp)\n"
|
||||
"sh $v0, 18($s0)\n"
|
||||
"lhu $v0, 10($s0)\n"
|
||||
"lhu $v1, 8($s0)\n"
|
||||
"addu $v0, $v0, $a0\n"
|
||||
"sh $v0, 26($s0)\n"
|
||||
"sh $v1, 24($s0)\n"
|
||||
"lhu $v0, 16($s0)\n"
|
||||
"lhu $v1, 26($s0)\n"
|
||||
"lui $a0, %hi(D_801BA6B0)\n"
|
||||
"lbu $a0, %lo(D_801BA6B0)($a0)\n"
|
||||
"sh $v0, 32($s0)\n"
|
||||
"bnez $a0, .L80185F0C\n"
|
||||
"sh $v1, 34($s0)\n"
|
||||
"lbu $v0, 1($s2)\n"
|
||||
"nop\n"
|
||||
"addiu $v1, $v0, 256\n"
|
||||
"sltiu $v0, $v0, 224\n"
|
||||
"bnez $v0, .L80185F20\n"
|
||||
"sll $v1, $v1, 6\n"
|
||||
"j .L80185F24\n"
|
||||
"ori $v0, $v1, 16\n"
|
||||
".L80185F0C:\n"
|
||||
"addiu $v0, $a0, 256\n"
|
||||
"sll $v1, $v0, 6\n"
|
||||
"sltiu $v0, $a0, 224\n"
|
||||
"beqz $v0, .L80185F24\n"
|
||||
"ori $v0, $v1, 16\n"
|
||||
".L80185F20:\n"
|
||||
"ori $v0, $v1, 22\n"
|
||||
".L80185F24:\n"
|
||||
"sh $v0, 14($s0)\n"
|
||||
"lui $v0, 48\n"
|
||||
"and $v0, $s3, $v0\n"
|
||||
"lui $v1, 32\n"
|
||||
"bne $v0, $v1, .L80185F50\n"
|
||||
"lui $a1, 255\n"
|
||||
"addu $a0, $t0, $zero\n"
|
||||
"addiu $a1, $sp, 16\n"
|
||||
"jal func_8001F730\n"
|
||||
"addu $a2, $s0, $zero\n"
|
||||
"lui $a1, 255\n"
|
||||
".L80185F50:\n"
|
||||
"ori $a1, $a1, 65535\n"
|
||||
"lui $a2, 65280\n"
|
||||
"lw $v1, 96($sp)\n"
|
||||
"lw $a0, 0($s0)\n"
|
||||
"sll $v1, $v1, 2\n"
|
||||
"addu $v1, $v1, $s1\n"
|
||||
"lw $v0, 4($v1)\n"
|
||||
"and $a0, $a0, $a2\n"
|
||||
"and $v0, $v0, $a1\n"
|
||||
"or $a0, $a0, $v0\n"
|
||||
"sw $a0, 0($s0)\n"
|
||||
"lw $v0, 4($v1)\n"
|
||||
"and $a1, $s0, $a1\n"
|
||||
"and $v0, $v0, $a2\n"
|
||||
"or $v0, $v0, $a1\n"
|
||||
"sw $v0, 4($v1)\n"
|
||||
".L80185F90:\n"
|
||||
"lw $ra, 124($sp)\n"
|
||||
"lw $s4, 120($sp)\n"
|
||||
"lw $s3, 116($sp)\n"
|
||||
"lw $s2, 112($sp)\n"
|
||||
"lw $s1, 108($sp)\n"
|
||||
"lw $s0, 104($sp)\n"
|
||||
"addiu $sp, $sp, 128\n"
|
||||
"jr $ra\n"
|
||||
"nop\n"
|
||||
".set\treorder\n.end\tfunc_80185810\n");
|
||||
INCLUDE_ASM("asm/ov_SC03_105/nonmatchings/ov_SC03_105_jr_80181C84", func_80185810);
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -5276,108 +5276,7 @@ u8 *a0;
|
||||
* normalizes the XZ/0/Z-ish diff vector via VectorNormal and fires func_8012F568(1,0x4014,0,
|
||||
* 0x18,&xy,&diff16) (an effect/sound-ish call), returning 1; otherwise returns 0.
|
||||
*/
|
||||
__asm__(
|
||||
".text\n"
|
||||
".align\t2\n"
|
||||
".globl\tfunc_80181828\n"
|
||||
".ent\tfunc_80181828\n"
|
||||
"func_80181828:\n"
|
||||
".frame\t$sp,64,$31\n"
|
||||
".mask\t0x80000000,-8\n"
|
||||
".fmask\t0,0\n"
|
||||
".set\tnoreorder\n"
|
||||
"addiu $29, $29, -64\n"
|
||||
"addu $6, $4, $0\n"
|
||||
"lui $3, %hi(D_801270C0)\n"
|
||||
"lh $3, %lo(D_801270C0)($3)\n"
|
||||
"addiu $2, $0, 2\n"
|
||||
"beq $3, $2, .L80181970\n"
|
||||
" sw $31, 56($29)\n"
|
||||
"lw $2, 32($6)\n"
|
||||
"lhu $4, 6($6)\n"
|
||||
"lh $5, 24($2)\n"
|
||||
"sh $4, 40($29)\n"
|
||||
"sll $4, $4, 16\n"
|
||||
"lhu $2, 10($6)\n"
|
||||
"sra $4, $4, 16\n"
|
||||
"sh $2, 42($29)\n"
|
||||
"lui $2, %hi(D_80126B5E)\n"
|
||||
"lh $2, %lo(D_80126B5E)($2)\n"
|
||||
"lhu $3, 14($6)\n"
|
||||
"sra $5, $5, 7\n"
|
||||
"sw $0, 28($29)\n"
|
||||
"subu $2, $2, $4\n"
|
||||
"sh $3, 44($29)\n"
|
||||
"sll $3, $3, 16\n"
|
||||
"sw $2, 24($29)\n"
|
||||
"lui $2, %hi(D_80126B66)\n"
|
||||
"lh $2, %lo(D_80126B66)($2)\n"
|
||||
"sra $3, $3, 16\n"
|
||||
"subu $2, $2, $3\n"
|
||||
"sw $2, 32($29)\n"
|
||||
"addiu $2, $29, 24\n"
|
||||
"lwc2 $9, 0($2)\n"
|
||||
"lwc2 $10, 4($2)\n"
|
||||
"lwc2 $11, 8($2)\n"
|
||||
"nop\n"
|
||||
"nop\n"
|
||||
"sqr 0\n"
|
||||
"swc2 $25, 0($2)\n"
|
||||
"swc2 $26, 4($2)\n"
|
||||
"swc2 $27, 8($2)\n"
|
||||
"mult $5, $5\n"
|
||||
"lw $2, 24($29)\n"
|
||||
"lw $3, 32($29)\n"
|
||||
"addu $2, $2, $3\n"
|
||||
"mflo $8\n"
|
||||
"slt $2, $2, $8\n"
|
||||
"beqz $2, .L80181974\n"
|
||||
" addu $2, $0, $0\n"
|
||||
"lui $3, %hi(D_80126B62)\n"
|
||||
"lh $3, %lo(D_80126B62)($3)\n"
|
||||
"lh $4, 10($6)\n"
|
||||
"subu $2, $3, $4\n"
|
||||
"bltz $2, .L80181914\n"
|
||||
" slti $2, $2, 10\n"
|
||||
"bnez $2, .L80181924\n"
|
||||
" addiu $4, $29, 24\n"
|
||||
"j .L80181974\n"
|
||||
" addu $2, $0, $0\n"
|
||||
".L80181914:\n"
|
||||
"subu $2, $4, $3\n"
|
||||
"slti $2, $2, 10\n"
|
||||
"beqz $2, .L80181970\n"
|
||||
" addiu $4, $29, 24\n"
|
||||
".L80181924:\n"
|
||||
"jal VectorNormal\n"
|
||||
" addu $5, $4, $0\n"
|
||||
"addiu $4, $0, 1\n"
|
||||
"addiu $5, $0, 16404\n"
|
||||
"lw $2, 24($29)\n"
|
||||
"lw $3, 28($29)\n"
|
||||
"lw $6, 32($29)\n"
|
||||
"addiu $7, $0, 24\n"
|
||||
"sh $2, 48($29)\n"
|
||||
"addiu $2, $29, 40\n"
|
||||
"sh $3, 50($29)\n"
|
||||
"sh $6, 52($29)\n"
|
||||
"sw $2, 16($29)\n"
|
||||
"addiu $2, $29, 48\n"
|
||||
"addu $6, $0, $0\n"
|
||||
"jal func_8012F568\n"
|
||||
" sw $2, 20($29)\n"
|
||||
"j .L80181974\n"
|
||||
" addiu $2, $0, 1\n"
|
||||
".L80181970:\n"
|
||||
"addu $2, $0, $0\n"
|
||||
".L80181974:\n"
|
||||
"lw $31, 56($29)\n"
|
||||
"addiu $29, $29, 64\n"
|
||||
"jr $31\n"
|
||||
" nop\n"
|
||||
".set\treorder\n"
|
||||
".end\tfunc_80181828\n"
|
||||
);
|
||||
INCLUDE_ASM("asm/ov_SC05_005/nonmatchings/ov_SC05_005_jr_8017D898", func_80181828);
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -3450,43 +3450,7 @@ int func_8017D77C(short *a0) {
|
||||
/* Handwritten GTE squared-distance check (§265 verbatim-asm lane, file-scope form).
|
||||
* Recovered C semantics: dx=D_80126CAC-a0[3]; dz=D_80126CB0-a0[7];
|
||||
* GTE SQR of {dx,0,dz}; return 0xC3FFF < (MAC1+MAC2+MAC3). */
|
||||
__asm__(".text\n.align 2\n.globl func_8017D810\n.ent\tfunc_8017D810\n"
|
||||
"func_8017D810:\n.frame $sp,16,$31\n.mask 0,0\n.fmask 0,0\n"
|
||||
".set\tnoreorder\n"
|
||||
"lui $2, %hi(D_80126CAC)\n"
|
||||
"lh $2, %lo(D_80126CAC)($2)\n"
|
||||
"lh $3, 6($4)\n"
|
||||
"addiu $29, $29, -16\n"
|
||||
"sw $0, 4($29)\n"
|
||||
"subu $2, $2, $3\n"
|
||||
"sw $2, 0($29)\n"
|
||||
"lui $2, %hi(D_80126CB0)\n"
|
||||
"lh $2, %lo(D_80126CB0)($2)\n"
|
||||
"lh $3, 14($4)\n"
|
||||
"nop\n"
|
||||
"subu $2, $2, $3\n"
|
||||
"sw $2, 8($29)\n"
|
||||
"lwc2 $9, 0($29)\n"
|
||||
"lwc2 $10, 4($29)\n"
|
||||
"lwc2 $11, 8($29)\n"
|
||||
"nop\n"
|
||||
"nop\n"
|
||||
"sqr 0\n"
|
||||
"swc2 $25, 0($29)\n"
|
||||
"swc2 $26, 4($29)\n"
|
||||
"swc2 $27, 8($29)\n"
|
||||
"lui $5, 12\n"
|
||||
"ori $5, $5, 16383\n"
|
||||
"lw $2, 0($29)\n"
|
||||
"lw $3, 4($29)\n"
|
||||
"lw $4, 8($29)\n"
|
||||
"addu $2, $2, $3\n"
|
||||
"addu $2, $2, $4\n"
|
||||
"slt $2, $5, $2\n"
|
||||
"addiu $29, $29, 16\n"
|
||||
"jr $31\n"
|
||||
"nop\n"
|
||||
".set\treorder\n.end\tfunc_8017D810\n");
|
||||
INCLUDE_ASM("asm/ov_SC06_032/nonmatchings/ov_SC06_032_jr_8017C24C", func_8017D810);
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -3350,370 +3350,7 @@ void func_8017DAEC(void)
|
||||
* D_800A6610[D_800B9A02<<14] + n*4, and chain a DR_TPAGE ((n<<5)&0x9FF)|0xE1000000 when
|
||||
* n<4. Immediates are DECIMAL throughout (maspsx rejects hex in __asm__ strings, §265). */
|
||||
|
||||
__asm__(".text\n.align 2\n.globl func_8017DC80\n.ent\tfunc_8017DC80\n"
|
||||
"func_8017DC80:\n.frame $sp,112,$31\n.mask 3238002688,-16\n.fmask 0,0\n"
|
||||
".set\tnoreorder\n"
|
||||
"addiu $sp, $sp, -112\n"
|
||||
"lui $a0, %hi(D_800AF648)\n"
|
||||
"addiu $a0, $a0, %lo(D_800AF648)\n"
|
||||
"sw $s4, 88($sp)\n"
|
||||
"lui $s4, %hi(D_8019B7B8)\n"
|
||||
"addiu $s4, $s4, %lo(D_8019B7B8)\n"
|
||||
"sw $s3, 84($sp)\n"
|
||||
"lui $s3, 255\n"
|
||||
"ori $s3, $s3, 65535\n"
|
||||
"sw $s7, 100($sp)\n"
|
||||
"lui $s7, 65280\n"
|
||||
"sw $s2, 80($sp)\n"
|
||||
"addiu $s2, $s4, 41\n"
|
||||
"sw $s5, 92($sp)\n"
|
||||
"addiu $s5, $s4, 20\n"
|
||||
"sw $s6, 96($sp)\n"
|
||||
"addiu $s6, $s4, 4\n"
|
||||
"lui $v0, %hi(D_800B9A02)\n"
|
||||
"lhu $v0, %lo(D_800B9A02)($v0)\n"
|
||||
"lui $v1, %hi(D_800A6610)\n"
|
||||
"addiu $v1, $v1, %lo(D_800A6610)\n"
|
||||
"sw $ra, 108($sp)\n"
|
||||
"sw $fp, 104($sp)\n"
|
||||
"sw $s1, 76($sp)\n"
|
||||
"sw $s0, 72($sp)\n"
|
||||
"sw $zero, 48($sp)\n"
|
||||
"sll $v0, $v0, 14\n"
|
||||
"jal func_80052E38\n"
|
||||
"addu $fp, $v0, $v1\n"
|
||||
".L8017DCF4:\n"
|
||||
"lhu $v1, 0($s4)\n"
|
||||
"nop\n"
|
||||
"andi $v0, $v1, 255\n"
|
||||
"slti $v0, $v0, 2\n"
|
||||
"bnez $v0, .L8017E190\n"
|
||||
"nop\n"
|
||||
"lhu $v0, -31($s2)\n"
|
||||
"nop\n"
|
||||
"andi $v0, $v0, 4096\n"
|
||||
"bnez $v0, .L8017DF50\n"
|
||||
"srl $s0, $v1, 8\n"
|
||||
"jal func_80010A08\n"
|
||||
"addiu $a0, $zero, 36\n"
|
||||
"addu $a1, $v0, $zero\n"
|
||||
"addiu $v0, $zero, 8\n"
|
||||
"sb $v0, 3($a1)\n"
|
||||
"addiu $v0, $zero, 56\n"
|
||||
"sb $v0, 7($a1)\n"
|
||||
"addiu $v0, $s4, 12\n"
|
||||
"lwc2 $0, 0($s6)\n"
|
||||
"lwc2 $1, 4($s6)\n"
|
||||
"lwc2 $2, 0($v0)\n"
|
||||
"lwc2 $3, 4($v0)\n"
|
||||
"lwc2 $4, 0($s5)\n"
|
||||
"lwc2 $5, 4($s5)\n"
|
||||
"nop\n"
|
||||
"nop\n"
|
||||
"rtpt\n"
|
||||
"addiu $v0, $sp, 16\n"
|
||||
"cfc2 $12, $31\n"
|
||||
"nop\n"
|
||||
"sw $12, 0($v0)\n"
|
||||
"addiu $4, $sp, 20\n"
|
||||
"addiu $3, $sp, 24\n"
|
||||
"addiu $2, $sp, 28\n"
|
||||
"swc2 $12, 0($4)\n"
|
||||
"swc2 $13, 0($3)\n"
|
||||
"swc2 $14, 0($2)\n"
|
||||
"addiu $2, $s4, 28\n"
|
||||
"lwc2 $0, 0($2)\n"
|
||||
"lwc2 $1, 4($2)\n"
|
||||
"nop\n"
|
||||
"nop\n"
|
||||
"rtps\n"
|
||||
"addiu $2, $sp, 32\n"
|
||||
"cfc2 $12, $31\n"
|
||||
"nop\n"
|
||||
"sw $12, 0($2)\n"
|
||||
"lw $2, 16($sp)\n"
|
||||
"lw $3, 32($sp)\n"
|
||||
"nop\n"
|
||||
"or $2, $2, $3\n"
|
||||
"sw $2, 16($sp)\n"
|
||||
"addiu $2, $sp, 36\n"
|
||||
"swc2 $14, 0($2)\n"
|
||||
"nop\n"
|
||||
"nop\n"
|
||||
"avsz4\n"
|
||||
"addiu $2, $sp, 40\n"
|
||||
"swc2 $7, 0($2)\n"
|
||||
"lw $2, 16($sp)\n"
|
||||
"addiu $3, $zero, -4097\n"
|
||||
"and $2, $2, $3\n"
|
||||
"bnez $2, .L8017E190\n"
|
||||
"nop\n"
|
||||
"lh $2, -31($s2)\n"
|
||||
"lw $17, 40($sp)\n"
|
||||
"andi $4, $2, 49152\n"
|
||||
"beqz $4, .L8017DE30\n"
|
||||
"addu $3, $2, $zero\n"
|
||||
"ori $2, $zero, 49152\n"
|
||||
"bne $4, $2, .L8017DE2C\n"
|
||||
"andi $2, $3, 4095\n"
|
||||
"subu $17, $17, $2\n"
|
||||
"bgez $17, .L8017DE34\n"
|
||||
"sltiu $2, $17, 4096\n"
|
||||
"j .L8017DE30\n"
|
||||
"addu $17, $zero, $zero\n"
|
||||
".L8017DE2C:\n"
|
||||
"addu $17, $17, $2\n"
|
||||
".L8017DE30:\n"
|
||||
"sltiu $2, $17, 4096\n"
|
||||
".L8017DE34:\n"
|
||||
"beqz $2, .L8017E190\n"
|
||||
"nop\n"
|
||||
"lw $2, 20($sp)\n"
|
||||
"nop\n"
|
||||
"sh $2, 8($5)\n"
|
||||
"lw $3, 24($sp)\n"
|
||||
"sra $2, $2, 16\n"
|
||||
"sh $2, 10($5)\n"
|
||||
"sh $3, 16($5)\n"
|
||||
"lw $4, 28($sp)\n"
|
||||
"sra $3, $3, 16\n"
|
||||
"sh $3, 18($5)\n"
|
||||
"sh $4, 24($5)\n"
|
||||
"lw $2, 36($sp)\n"
|
||||
"sra $4, $4, 16\n"
|
||||
"sh $4, 26($5)\n"
|
||||
"sh $2, 32($5)\n"
|
||||
"sra $2, $2, 16\n"
|
||||
"sh $2, 34($5)\n"
|
||||
"lw $2, 11($s2)\n"
|
||||
"nop\n"
|
||||
"beqz $2, .L8017DF0C\n"
|
||||
"nop\n"
|
||||
"lbu $2, -4($s2)\n"
|
||||
"nop\n"
|
||||
"sb $2, 12($5)\n"
|
||||
"sb $2, 4($5)\n"
|
||||
"lbu $2, -2($s2)\n"
|
||||
"nop\n"
|
||||
"sb $2, 13($5)\n"
|
||||
"sb $2, 5($5)\n"
|
||||
"lbu $2, 0($s2)\n"
|
||||
"nop\n"
|
||||
"sb $2, 14($5)\n"
|
||||
"sb $2, 6($5)\n"
|
||||
"lw $2, 11($s2)\n"
|
||||
"nop\n"
|
||||
"lbu $2, 37($2)\n"
|
||||
"nop\n"
|
||||
"sb $2, 28($5)\n"
|
||||
"sb $2, 20($5)\n"
|
||||
"lw $2, 11($s2)\n"
|
||||
"nop\n"
|
||||
"lbu $2, 39($2)\n"
|
||||
"nop\n"
|
||||
"sb $2, 29($5)\n"
|
||||
"sb $2, 21($5)\n"
|
||||
"lw $2, 11($s2)\n"
|
||||
"nop\n"
|
||||
"lbu $2, 41($2)\n"
|
||||
"nop\n"
|
||||
"sb $2, 30($5)\n"
|
||||
"j .L8017E0E0\n"
|
||||
"sb $2, 22($5)\n"
|
||||
".L8017DF0C:\n"
|
||||
"lbu $2, -4($s2)\n"
|
||||
"nop\n"
|
||||
"sb $2, 28($5)\n"
|
||||
"sb $2, 20($5)\n"
|
||||
"sb $2, 12($5)\n"
|
||||
"sb $2, 4($5)\n"
|
||||
"lbu $2, -2($s2)\n"
|
||||
"nop\n"
|
||||
"sb $2, 29($5)\n"
|
||||
"sb $2, 21($5)\n"
|
||||
"sb $2, 13($5)\n"
|
||||
"sb $2, 5($5)\n"
|
||||
"lbu $2, 0($s2)\n"
|
||||
"nop\n"
|
||||
"sb $2, 30($5)\n"
|
||||
"j .L8017E0D4\n"
|
||||
"sb $2, 22($5)\n"
|
||||
".L8017DF50:\n"
|
||||
"jal func_80010A08\n"
|
||||
"addiu $4, $zero, 20\n"
|
||||
"addu $5, $2, $zero\n"
|
||||
"addiu $2, $zero, 4\n"
|
||||
"sb $2, 3($5)\n"
|
||||
"addiu $2, $zero, 80\n"
|
||||
"sb $2, 7($5)\n"
|
||||
"lwc2 $0, 0($s6)\n"
|
||||
"lwc2 $1, 4($s6)\n"
|
||||
"lwc2 $2, 0($s5)\n"
|
||||
"lwc2 $3, 4($s5)\n"
|
||||
"lwc2 $4, 0($s5)\n"
|
||||
"lwc2 $5, 4($s5)\n"
|
||||
"nop\n"
|
||||
"nop\n"
|
||||
"rtpt\n"
|
||||
"addiu $2, $sp, 20\n"
|
||||
"swc2 $12, 0($2)\n"
|
||||
"addiu $2, $sp, 24\n"
|
||||
"swc2 $13, 0($2)\n"
|
||||
"addiu $2, $sp, 16\n"
|
||||
"cfc2 $12, $31\n"
|
||||
"nop\n"
|
||||
"sw $12, 0($2)\n"
|
||||
"addiu $2, $sp, 40\n"
|
||||
"mfc2 $12, $19\n"
|
||||
"nop\n"
|
||||
"sra $12, $12, 2\n"
|
||||
"sw $12, 0($2)\n"
|
||||
"lw $2, 16($sp)\n"
|
||||
"addiu $3, $zero, -4097\n"
|
||||
"and $2, $2, $3\n"
|
||||
"bnez $2, .L8017E190\n"
|
||||
"nop\n"
|
||||
"lh $2, -31($s2)\n"
|
||||
"lw $17, 40($sp)\n"
|
||||
"andi $4, $2, 49152\n"
|
||||
"beqz $4, .L8017E010\n"
|
||||
"addu $3, $2, $zero\n"
|
||||
"ori $2, $zero, 49152\n"
|
||||
"bne $4, $2, .L8017E00C\n"
|
||||
"andi $2, $3, 4095\n"
|
||||
"subu $17, $17, $2\n"
|
||||
"bgez $17, .L8017E014\n"
|
||||
"sltiu $2, $17, 4096\n"
|
||||
"j .L8017E010\n"
|
||||
"addu $17, $zero, $zero\n"
|
||||
".L8017E00C:\n"
|
||||
"addu $17, $17, $2\n"
|
||||
".L8017E010:\n"
|
||||
"sltiu $2, $17, 4096\n"
|
||||
".L8017E014:\n"
|
||||
"beqz $2, .L8017E190\n"
|
||||
"nop\n"
|
||||
"lw $2, 20($sp)\n"
|
||||
"nop\n"
|
||||
"sh $2, 8($5)\n"
|
||||
"lw $3, 24($sp)\n"
|
||||
"sra $2, $2, 16\n"
|
||||
"sh $2, 10($5)\n"
|
||||
"sh $3, 16($5)\n"
|
||||
"sra $3, $3, 16\n"
|
||||
"sh $3, 18($5)\n"
|
||||
"lw $2, 11($s2)\n"
|
||||
"nop\n"
|
||||
"beqz $2, .L8017E0B0\n"
|
||||
"nop\n"
|
||||
"lbu $2, -4($s2)\n"
|
||||
"nop\n"
|
||||
"sb $2, 4($5)\n"
|
||||
"lbu $2, -2($s2)\n"
|
||||
"nop\n"
|
||||
"sb $2, 5($5)\n"
|
||||
"lbu $2, 0($s2)\n"
|
||||
"nop\n"
|
||||
"sb $2, 6($5)\n"
|
||||
"lw $2, 11($s2)\n"
|
||||
"nop\n"
|
||||
"lbu $2, 37($2)\n"
|
||||
"nop\n"
|
||||
"sb $2, 12($5)\n"
|
||||
"lw $2, 11($s2)\n"
|
||||
"nop\n"
|
||||
"lbu $2, 39($2)\n"
|
||||
"nop\n"
|
||||
"sb $2, 13($5)\n"
|
||||
"lw $2, 11($s2)\n"
|
||||
"nop\n"
|
||||
"lbu $2, 41($2)\n"
|
||||
"j .L8017E0E0\n"
|
||||
"sb $2, 14($5)\n"
|
||||
".L8017E0B0:\n"
|
||||
"lbu $2, -4($s2)\n"
|
||||
"nop\n"
|
||||
"sb $2, 12($5)\n"
|
||||
"sb $2, 4($5)\n"
|
||||
"lbu $2, -2($s2)\n"
|
||||
"nop\n"
|
||||
"sb $2, 13($5)\n"
|
||||
"sb $2, 5($5)\n"
|
||||
"lbu $2, 0($s2)\n"
|
||||
".L8017E0D4:\n"
|
||||
"nop\n"
|
||||
"sb $2, 14($5)\n"
|
||||
"sb $2, 6($5)\n"
|
||||
".L8017E0E0:\n"
|
||||
"slti $2, $16, 4\n"
|
||||
"beqz $2, .L8017E0FC\n"
|
||||
"sll $4, $17, 2\n"
|
||||
"lbu $2, 7($5)\n"
|
||||
"nop\n"
|
||||
"ori $2, $2, 2\n"
|
||||
"sb $2, 7($5)\n"
|
||||
".L8017E0FC:\n"
|
||||
"addu $4, $4, $30\n"
|
||||
"lw $3, 0($5)\n"
|
||||
"lw $2, 0($4)\n"
|
||||
"and $3, $3, $23\n"
|
||||
"and $2, $2, $19\n"
|
||||
"or $3, $3, $2\n"
|
||||
"sw $3, 0($5)\n"
|
||||
"lw $2, 0($4)\n"
|
||||
"and $3, $5, $19\n"
|
||||
"and $2, $2, $23\n"
|
||||
"or $2, $2, $3\n"
|
||||
"sw $2, 0($4)\n"
|
||||
"slti $2, $16, 4\n"
|
||||
"beqz $2, .L8017E190\n"
|
||||
"nop\n"
|
||||
"jal func_80010A08\n"
|
||||
"addiu $4, $zero, 8\n"
|
||||
"addiu $3, $zero, 1\n"
|
||||
"sb $3, 3($2)\n"
|
||||
"sll $3, $16, 5\n"
|
||||
"andi $3, $3, 2559\n"
|
||||
"lui $4, 57600\n"
|
||||
"or $3, $3, $4\n"
|
||||
"sll $4, $17, 2\n"
|
||||
"lw $5, 0($2)\n"
|
||||
"addu $4, $4, $30\n"
|
||||
"sw $3, 4($2)\n"
|
||||
"lw $3, 0($4)\n"
|
||||
"and $5, $5, $23\n"
|
||||
"and $3, $3, $19\n"
|
||||
"or $5, $5, $3\n"
|
||||
"sw $5, 0($2)\n"
|
||||
"lw $3, 0($4)\n"
|
||||
"and $2, $2, $19\n"
|
||||
"and $3, $3, $23\n"
|
||||
"or $3, $3, $2\n"
|
||||
"sw $3, 0($4)\n"
|
||||
".L8017E190:\n"
|
||||
"addiu $18, $18, 56\n"
|
||||
"addiu $21, $21, 56\n"
|
||||
"addiu $22, $22, 56\n"
|
||||
"lw $6, 48($sp)\n"
|
||||
"addiu $20, $20, 56\n"
|
||||
"addiu $6, $6, 1\n"
|
||||
"slti $2, $6, 192\n"
|
||||
"bnez $2, .L8017DCF4\n"
|
||||
"sw $6, 48($sp)\n"
|
||||
"lw $ra, 108($sp)\n"
|
||||
"lw $fp, 104($sp)\n"
|
||||
"lw $23, 100($sp)\n"
|
||||
"lw $22, 96($sp)\n"
|
||||
"lw $21, 92($sp)\n"
|
||||
"lw $20, 88($sp)\n"
|
||||
"lw $19, 84($sp)\n"
|
||||
"lw $18, 80($sp)\n"
|
||||
"lw $17, 76($sp)\n"
|
||||
"lw $16, 72($sp)\n"
|
||||
"addiu $sp, $sp, 112\n"
|
||||
"jr $ra\n"
|
||||
"nop\n"
|
||||
".set\treorder\n.end\tfunc_8017DC80\n");
|
||||
INCLUDE_ASM("asm/ov_SC07_002/nonmatchings/ov_SC07_002_jr_8017C8D0", func_8017DC80);
|
||||
|
||||
|
||||
extern s32 D_8019B7B8;
|
||||
|
||||
Reference in New Issue
Block a user