mirror of
https://github.com/Druthulu/BFM-decomp
synced 2026-10-01 23:52:03 -04:00
phase-36: S105 s105_f8 — func_8018622C banked at 0 through the whole-object gate + propagated — f8 plain C (the lever-free OR-sibling's spelling ported; 3 pins → 0)
This commit is contained in:
Drew T
+174
-174
@@ -1,5 +1,5 @@
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|
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|
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|
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|
||||
},
|
||||
"ok": true,
|
||||
"seconds": 2.2
|
||||
|
||||
@@ -29624,3 +29624,4 @@
|
||||
{"ts": "2026-09-11 17:51:46", "label": "s105_f6_minlever", "rung": "E", "calib": {"head": "eb0d076a0", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC07_007/ov_SC07_007_jr_8017BEBC.c", "fn": "func_8017DFB8", "addr": 2149048248, "aliases": null, "header": false, "includers": 0, "nhash_before": "0c5a88a795b6539baa290a7504edbd01abf86610", "nhash_after": "8153324184388ceabb11312598c8874aaf81b4c6", "source": ".run/P36/agents/ov_SC07_007__func_8017DFB8/body.c", "verdict": "LEVER-FREE", "sites": [{"ord": 0, "kind": "pin", "cls": "A", "detail": "$4", "via": "", "line": 4044, "verdict": "NEEDED", "why": "left by the author", "oracle": ""}, {"ord": 1, "kind": "instruction", "cls": "B", "detail": "la", "via": "", "line": 4066, "verdict": "NEEDED", "why": "left by the author", "oracle": ""}, {"ord": 2, "kind": "instruction", "cls": "B", "detail": "addiu", "via": "", "line": 4083, "verdict": "NEEDED", "why": "left by the author", "oracle": ""}], "compiles": 1, "seconds": 0.169, "objects": ["build/src/ov_SC07_007/ov_SC07_007_jr_8017BEBC.o"], "before_text": "void func_8017DFB8(void *a0) {\n register u8 *p __asm__(\"$16\"); // !FAKE: pin $16 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n u8 *tbl;\n register s32 aa __asm__(\"$4\"); // !FAKE: pin $4 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n u8 *ab;\n s32 idx;\n s16 v[3];\n s32 x0, y0, z0;\n s32 x1, y1, z1;\n s32 x2, y2, z2;\n\n p = (u8 *)a0;\n if ((u8)func_80029178(0x123) != 0 && (s16)func_8002AE60() == 0 &&\n ((s16)func_80014C54(0, 0, 0x800) != 0 || (s16)func_80014C54(0, 0, 0x40) != 0) &&\n func_800CF8B4() != 0) {\n D_801C79CC = 1;\n func_800D1724((s32)D_80186964);\n return;\n }\n D_801882B8[*(u16 *)(p + 2)](p);\n idx = func_8012A758();\n tbl = D_80187C60;\n func_800139C8(idx, tbl, v);\n aa = idx;\n ab = tbl + 8;\n x0 = v[0]; y0 = v[1]; z0 = v[2];\n __asm__(\"la %0, D_800A5E88\" : \"=r\"(p) : \"r\"(x0), \"r\"(y0), \"r\"(z0), \"r\"(ab)); // !FAKE: instruction la \u2014 NEEDED DIFFERS (P36 rung B tus9)\n *(s32 *)p = x0;\n D_800A5E8C = y0;\n D_800A5E90 = z0;\n func_800139C8(aa, ab, v);\n x1 = v[0]; y1 = v[1]; z1 = v[2];\n *(s32 *)(p + 0x10) = x1;\n D_800A5E9C = y1;\n D_800A5EA0 = z1;\n func_800139C8(idx, tbl + 0x10, v);\n x2 = v[0]; y2 = v[1]; z2 = v[2];\n *(s32 *)(p + 0x20) = x2;\n D_800A5EAC = y2;\n D_800A5EB0 = z2;\n func_80028620(0, p);\n func_80028620(1, p + 0x10);\n aa = 2;\n __asm__(\"addiu %0,%1,0x20\" : \"=r\"(p) : \"0\"(p), \"r\"(aa)); // !FAKE: instruction addiu \u2014 NEEDED DIFFERS (P36 rung B tus9)\n func_80028620(aa, p);\n}\n", "after_text": "void func_8017DFB8(void *a0) {\n u8 *p;\n u8 *tbl;\n register s32 aa __asm__(\"$4\"); // !FAKE: pin $4 \u2014 gives `aa = idx` (the second call's a0 copy) an early LUID that cse would otherwise fold away, and makes `aa = 2` the asm input in $a0 (P36 S105 f6 minimum-lever)\n u8 *ab;\n s32 idx;\n s16 v[3];\n s32 x0, y0, z0;\n s32 x1, y1, z1;\n s32 x2, y2, z2;\n\n if ((u8)func_80029178(0x123) != 0 && (s16)func_8002AE60() == 0 &&\n ((s16)func_80014C54(0, 0, 0x800) != 0 || (s16)func_80014C54(0, 0, 0x40) != 0) &&\n func_800CF8B4() != 0) {\n D_801C79CC = 1;\n func_800D1724((s32)D_80186964);\n return;\n }\n D_801882B8[*(u16 *)((u8 *)a0 + 2)](a0);\n idx = func_8012A758();\n tbl = D_80187C60;\n func_800139C8(idx, tbl, v);\n aa = idx;\n ab = tbl + 8;\n x0 = v[0]; y0 = v[1]; z0 = v[2];\n __asm__(\"la %0, D_800A5E88\" : \"=r\"(p) : \"r\"(x0), \"r\"(y0), \"r\"(z0), \"r\"(ab)); // !FAKE: instruction la \u2014 cse find_best_addr (cse.c:2622) folds (plus p K) to the absolute symbol whenever p is a known constant; the dead inputs place it after the lh loads (sched1 LUID) (P36 S105 f6 minimum-lever)\n *(s32 *)p = x0;\n D_800A5E8C = y0;\n D_800A5E90 = z0;\n func_800139C8(aa, ab, v);\n x1 = v[0]; y1 = v[1]; z1 = v[2];\n *(s32 *)(p + 0x10) = x1;\n D_800A5E9C = y1;\n D_800A5EA0 = z1;\n func_800139C8(idx, tbl + 0x10, v);\n x2 = v[0]; y2 = v[1]; z2 = v[2];\n *(s32 *)(p + 0x20) = x2;\n D_800A5EAC = y2;\n D_800A5EB0 = z2;\n func_80028620(0, p);\n func_80028620(1, p + 0x10);\n aa = 2;\n __asm__(\"addiu %0,%1,0x20\" : \"=r\"(p) : \"0\"(p), \"r\"(aa)); // !FAKE: instruction addiu \u2014 combine folds `p += 0x20; f(2, p)` into `addiu a1,s0,32` unless a CALL_INSN separates add and copy (combine.c:929); the \"r\"(aa) input orders it after `li a0,2` (P36 S105 f6 minimum-lever)\n func_80028620(aa, p);\n}\n"}
|
||||
{"ts": "2026-09-11 18:17:56", "label": "s105_f8", "rung": "E", "calib": {"head": "f3e65cc42", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC02_005/ov_SC02_005_jr_80185E80.c", "fn": "func_8018A6A0", "addr": 2149099168, "aliases": null, "header": false, "includers": 0, "nhash_before": "ea7280e9f72b86eee0391e9696f8dc390d83fe8f", "nhash_after": "38aec2da5400a739d2bff8fde6b4be611b983488", "source": ".run/P36/agents/ov_SC02_005__func_8018A6A0/body.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.188, "objects": ["build/src/ov_SC02_005/ov_SC02_005_jr_80185E80.o"], "before_text": "void func_8018A6A0(s32 a0, u16 *a1)\n{\n u8 *s0 = (u8 *)a0;\n u16 *s1 = a1;\n u16 vec0[4];\n u16 counter;\n s32 res[3];\n s32 flags;\n u8 *puVar;\n\n func_8012B2CC(a0);\n\n gte_SetRotTransMatrix((u8 *)*(s32 *)(s0 + 0x20) + 0x34);\n\n vec0[2] = 0;\n vec0[0] = 0;\n vec0[1] = counter = *s1;\n\n goto test;\nbody:\n puVar = func_8012913C(0xC);\n if (puVar != 0) {\n __asm__ __volatile__( // !FAKE: gte direct \u2014 clobbers beyond Sony's macro (a scheduling steer; P36 T5 t5_remark3)\n \"lwc2 $0, 0(%0)\\n\"\n \"lwc2 $1, 4(%0)\\n\"\n \"nop\\n\"\n \"nop\\n\"\n \"mvmva 1, 0, 0, 0, 0\\n\"\n : : \"r\"(vec0) : \"memory\");\n gte_stlvnl(res);\n gte_stflg(&flags);\n *(u16 *)(puVar + 6) = (u16)res[0];\n *(u16 *)(puVar + 0xA) = (u16)res[1];\n *(u16 *)(puVar + 0xE) = (u16)(res[2] - 8);\n }\n {\n register u16 tmp __asm__(\"$3\"); // !FAKE: pin $3 \u2014 NEEDED DIFFERS (P36 rung B tus10)\n counter = vec0[1];\n tmp = *(u16 *)(s1 + 2);\n counter += tmp;\n vec0[1] = counter;\n }\ntest:\n if ((s16)counter < *(s16 *)(s1 + 1)) goto body;\n}\n", "after_text": "void func_8018A6A0(s32 a0, u16 *a1)\n{\n u8 *s0 = (u8 *)a0;\n u16 *s1 = a1;\n u16 vec0[4];\n u16 counter;\n s32 res[3];\n s32 flags;\n u8 *puVar;\n\n func_8012B2CC(a0);\n\n gte_SetRotTransMatrix((u8 *)*(s32 *)(s0 + 0x20) + 0x34);\n\n vec0[2] = 0;\n vec0[0] = 0;\n vec0[1] = counter = *s1;\n while ((s16)counter < *(s16 *)(s1 + 1)) {\n puVar = func_8012913C(0xC);\n if (puVar != 0) {\n gte_ldv0(vec0);\n gte_rtv0tr();\n gte_stlvnl(res);\n gte_stflg(&flags);\n *(u16 *)(puVar + 6) = (u16)res[0];\n *(u16 *)(puVar + 0xA) = (u16)res[1];\n *(u16 *)(puVar + 0xE) = (u16)(res[2] - 8);\n }\n counter = vec0[1] + s1[2]; vec0[1] = counter; }\n}\n"}
|
||||
{"ts": "2026-09-11 18:18:14", "label": "s105_f8", "rung": "E", "calib": {"head": "7069f8c3d", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC02_005/ov_SC02_005_jr_80185E80.c", "fn": "func_80186424", "addr": 2149082148, "aliases": null, "header": false, "includers": 0, "nhash_before": "5653916b57bfa254ee44e38a2b3dd2a5f8ca90fb", "nhash_after": "c363e38222fd4dd72c0fa7ed1c7b8b9e2a110e17", "source": ".run/P36/agents/ov_SC02_005__func_80186424/body.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.183, "objects": ["build/src/ov_SC02_005/ov_SC02_005_jr_80185E80.o"], "before_text": "void func_80186424(s32 arg0)\n{\n if (*(u8 *)(arg0 + 0x74) != 0) {\n extern s32 gVecX __asm__(\"D_80126B5C\");\n s32 in[4];\n s32 out[4];\n s32 tmp[4];\n u16 h;\n\n in[0] = gVecX;\n in[1] = D_80126B60;\n in[2] = D_80126B64;\n func_8012F0BC((s32 *)(*(s32 *)(arg0 + 0x20) + 0x34), in, tmp);\n func_80132784(arg0, *(s32 *)(arg0 + 0x64), *(u16 *)(arg0 + 0xFC));\n func_8012F1A4((s32 *)(*(s32 *)(arg0 + 0x20) + 0x34), (s32)tmp, out);\n gVecX = out[0];\n D_80126B60 = out[1];\n D_80126B64 = out[2];\n h = *((u16 *)&gVecX + 1);\n *(u16 *)((s32)D_80126B78 + 8) = h;\n *(s32 *)((s32)D_80126B78 + 0x48) = (s32)(s16)h;\n __asm__ __volatile__(\"\" ::: \"memory\"); // !FAKE: barrier memory \u2014 NEEDED DIFFERS (P36 rung B tus10)\n *(u16 *)((s32)D_80126B78 + 0xA) = D_80126B62;\n *(s32 *)((s32)D_80126B78 + 0x4C) = (s32)(s16)D_80126B62;\n __asm__ __volatile__(\"\" ::: \"memory\"); // !FAKE: barrier memory \u2014 NEEDED DIFFERS (P36 rung B tus10)\n *(u16 *)((s32)D_80126B78 + 0xC) = D_80126B66;\n *(s32 *)((s32)D_80126B78 + 0x50) = (s32)(s16)D_80126B66;\n } else {\n func_80132784(arg0, *(s32 *)(arg0 + 0x64), *(u16 *)(arg0 + 0xFC));\n }\n}\n", "after_text": "void func_80186424(s32 arg0)\n{\n if (*(u8 *)(arg0 + 0x74) != 0) {\n extern s32 gVecX __asm__(\"D_80126B5C\");\n extern s32 *aCam[] __asm__(\"D_80126B78\");\n s32 in[4];\n s32 out[4];\n s32 tmp[4];\n\n in[0] = gVecX;\n in[1] = D_80126B60;\n in[2] = D_80126B64;\n func_8012F0BC((s32 *)(*(s32 *)(arg0 + 0x20) + 0x34), in, tmp);\n func_80132784(arg0, *(s32 *)(arg0 + 0x64), *(u16 *)(arg0 + 0xFC));\n func_8012F1A4((s32 *)(*(s32 *)(arg0 + 0x20) + 0x34), (s32)tmp, out);\n gVecX = out[0];\n D_80126B60 = out[1];\n D_80126B64 = out[2];\n *(s32 *)((s32)aCam[0] + 0x48) = *(s16 *)((s32)aCam[0] + 8) = *((u16 *)&gVecX + 1);\n *(s32 *)((s32)aCam[0] + 0x4C) = *(s16 *)((s32)aCam[0] + 0xA) = D_80126B62;\n *(s32 *)((s32)aCam[0] + 0x50) = *(s16 *)((s32)aCam[0] + 0xC) = D_80126B66;\n } else {\n func_80132784(arg0, *(s32 *)(arg0 + 0x64), *(u16 *)(arg0 + 0xFC));\n }\n}\n"}
|
||||
{"ts": "2026-09-11 18:18:31", "label": "s105_f8", "rung": "E", "calib": {"head": "21f2fd8e4", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC02_005/ov_SC02_005_jr_80185E80.c", "fn": "func_8018622C", "addr": 2149081644, "aliases": null, "header": false, "includers": 0, "nhash_before": "3273b305758c8bd2a33b7b916a2ca19fda10a321", "nhash_after": "661cbcef9e85fb64f7bdd4c69ef35db07e9c91c0", "source": ".run/P36/agents/ov_SC02_005__func_8018622C/body.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.185, "objects": ["build/src/ov_SC02_005/ov_SC02_005_jr_80185E80.o"], "before_text": "void func_8018622C(MainStruct *a0) {\n register MainStruct *a1 __asm__(\"$5\"); // !FAKE: pin $5 \u2014 NEEDED DIFFERS (P36 rung B tus10)\n register SubStruct *v1 __asm__(\"$3\"); // !FAKE: pin $3 \u2014 NEEDED DIFFERS (P36 rung B tus10)\n register s32 v0 __asm__(\"$2\"); // !FAKE: pin $2 \u2014 NEEDED DIFFERS (P36 rung B tus10)\n s32 a2;\n\n a1 = a0;\n a2 = 0x7FFFFFFF;\n\n v1 = a1->f_20;\n v0 = v1->field_4;\n v0 &= a2;\n v1->field_4 = v0;\n\n v0 = (s32)a1->f_CC;\n v1 = ((MainStruct *)v0)->f_20;\n v0 = v1->field_4;\n v0 &= a2;\n v1->field_4 = v0;\n\n v0 = (s32)a1->f_D0;\n v1 = ((MainStruct *)v0)->f_20;\n v0 = v1->field_4;\n\n a0 = D_801E43A4;\n v0 &= a2;\n v1->field_4 = v0;\n\n v1 = (SubStruct *)a0->f_CC;\n v0 = v1->field_4;\n v0 &= a2;\n v1->field_4 = v0;\n\n v0 = a1->f_E8;\n if ((v0 & 0x2) == 0) {\n v0 = (s32)a1->f_D4;\n v1 = ((MainStruct *)v0)->f_20;\n v0 = v1->field_4;\n v0 &= a2;\n v1->field_4 = v0;\n }\n}\n", "after_text": "void func_8018622C(MainStruct *a0) {\n MainStruct *a1 = a0;\n s32 a2 = 0x7FFFFFFF;\n MainStruct *a0_reg;\n MainStruct *v0;\n SubStruct *v1;\n s32 v2;\n\n v1 = a1->f_20;\n v1->field_4 &= a2;\n\n v0 = (MainStruct *)a1->f_CC;\n v1 = v0->f_20;\n v1->field_4 &= a2;\n\n a0_reg = D_801E43A4;\n\n v0 = (MainStruct *)a1->f_D0;\n v0->f_20->field_4 &= a2;\n\n v1 = (SubStruct *)a0_reg->f_CC;\n v1->field_4 &= a2;\n\n v2 = a1->f_E8;\n if ((v2 & 0x2) == 0) {\n v0 = (MainStruct *)a1->f_D4;\n v0->f_20->field_4 &= a2;\n }\n}\n"}
|
||||
|
||||
@@ -224,45 +224,32 @@ void func_80186178(s32 *a0)
|
||||
extern MainStruct *D_801E43A4;
|
||||
|
||||
void func_8018622C(MainStruct *a0) {
|
||||
register MainStruct *a1 __asm__("$5"); // !FAKE: pin $5 — NEEDED DIFFERS (P36 rung B tus10)
|
||||
register SubStruct *v1 __asm__("$3"); // !FAKE: pin $3 — NEEDED DIFFERS (P36 rung B tus10)
|
||||
register s32 v0 __asm__("$2"); // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B tus10)
|
||||
s32 a2;
|
||||
|
||||
a1 = a0;
|
||||
a2 = 0x7FFFFFFF;
|
||||
MainStruct *a1 = a0;
|
||||
s32 a2 = 0x7FFFFFFF;
|
||||
MainStruct *a0_reg;
|
||||
MainStruct *v0;
|
||||
SubStruct *v1;
|
||||
s32 v2;
|
||||
|
||||
v1 = a1->f_20;
|
||||
v0 = v1->field_4;
|
||||
v0 &= a2;
|
||||
v1->field_4 = v0;
|
||||
v1->field_4 &= a2;
|
||||
|
||||
v0 = (s32)a1->f_CC;
|
||||
v1 = ((MainStruct *)v0)->f_20;
|
||||
v0 = v1->field_4;
|
||||
v0 &= a2;
|
||||
v1->field_4 = v0;
|
||||
v0 = (MainStruct *)a1->f_CC;
|
||||
v1 = v0->f_20;
|
||||
v1->field_4 &= a2;
|
||||
|
||||
v0 = (s32)a1->f_D0;
|
||||
v1 = ((MainStruct *)v0)->f_20;
|
||||
v0 = v1->field_4;
|
||||
a0_reg = D_801E43A4;
|
||||
|
||||
a0 = D_801E43A4;
|
||||
v0 &= a2;
|
||||
v1->field_4 = v0;
|
||||
v0 = (MainStruct *)a1->f_D0;
|
||||
v0->f_20->field_4 &= a2;
|
||||
|
||||
v1 = (SubStruct *)a0->f_CC;
|
||||
v0 = v1->field_4;
|
||||
v0 &= a2;
|
||||
v1->field_4 = v0;
|
||||
v1 = (SubStruct *)a0_reg->f_CC;
|
||||
v1->field_4 &= a2;
|
||||
|
||||
v0 = a1->f_E8;
|
||||
if ((v0 & 0x2) == 0) {
|
||||
v0 = (s32)a1->f_D4;
|
||||
v1 = ((MainStruct *)v0)->f_20;
|
||||
v0 = v1->field_4;
|
||||
v0 &= a2;
|
||||
v1->field_4 = v0;
|
||||
v2 = a1->f_E8;
|
||||
if ((v2 & 0x2) == 0) {
|
||||
v0 = (MainStruct *)a1->f_D4;
|
||||
v0->f_20->field_4 &= a2;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user