mirror of
https://github.com/Druthulu/BFM-decomp
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feat(phase-29): ov_SC06_018 non-jtbl wave batch-1 (8 x1 + 30 swept = 38 instances) + fix gate_stage arity-undo revert bug
- batch-1 wave: 25 non-jtbl ov_SC06_018 targets (reach 3-14 modal), 13/25 match_one MATCH; whole-binary banked 8 (4 plain + 4 via gate_stage --src-file), swept 4 families -> 30 members across 13 overlays. 5 matches deferred (missing-sym/s58/deeper plumbing); 12 nears are permuter fuel (several close=2/3/4). - KEY: non-jtbl fns in a jr-split file need gate_stage --src-file <the jr TU> (the default- TU reconcile misses them -- same class as the jtbl --src-file fix). - BUG FIX (R33): gate_stage's arity-undo snapshotted src/<bin>/*.c BEFORE _gate1 splices the banks there, so an unbanked draft in the batch triggered a snapshot-restore that SILENTLY REVERTED the banks (measured: a 9-draft run banked 4, the 5 unbanked reverted all 4 to INCLUDE_ASM). Fix: restore ONLY src/shared/ (the fleet hazard the snapshot exists for); the binary's own TU arity edits are local + byte-neutral. GATE_NO_ARITY=1 was the interim workaround. s61's law from below (undo scope must not EXCEED write scope). - incremental check-all 140/140 (concurrent with batch-2 drafting; full R22 after batch 2). fleet distinct 67.5->67.6% (+38 unique fns), instr 78.6% steady.
This commit is contained in:
Drew T
@@ -6708,3 +6708,13 @@
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{"ts": "2026-07-22 14:08:23", "addr": null, "name": "func_80165CA0", "reach": null, "klass": "regalloc-order", "nins": null, "status": "near", "closeness": 0, "where_stuck": "none \u2014 MATCH (99 ins, match_one masked)", "best_draft": ".run/backlog_drafts/func_80165CA0.c", "binary": "ov_SC06_018", "source": "worker", "residual": null, "passes_tried": null}
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{"ts": "2026-07-22 14:09:43", "addr": null, "name": "func_80191C50", "reach": null, "klass": "schedule", "nins": null, "status": "near", "closeness": 9, "where_stuck": "close=9 \u2014 only the case-7 sp20[] setup window (0x80192380..0x801923A4): gcc's list scheduler picks the D_80126B62 lui 2nd (its extra `addiu -0x38` gives that chain +1 priority) where the target picks D_80126B66 2nd (LUID/program order); everything else (710/710 ins, frame 0x40, $s0/$s1, jtbl, 3 entity loops, 8 sync blocks, cross-jumped L4AC tail) is byte-identical.", "best_draft": ".run/backlog_drafts/func_80191C50.c", "binary": "ov_SC06_018", "source": "worker", "residual": [[460, "3c030000 lui\tv1,0x0", "3c028012 lui $v0, %hi(D_80126B5E)"], [461, "94630000 lhu\tv1,0(v1)", "94426b5e lhu $v0, %lo(D_80126B5E)($v0)"], [462, "3c020000 lui\tv0,0x0", "3c038012 lui $v1, %hi(D_80126B66)"], [463, "94420000 lhu\tv0,0(v0)", "94636b66 lhu $v1, %lo(D_80126B66)($v1)"], [464, "3c040000 lui\ta0,0x0", "a7a20020 sh $v0, 0x20($sp)"], [465, "94840000 lhu\ta0,0(a0)", "3c028012 lui $v0, %hi(D_80126B62)"], [466, "2442ffc8 addiu\tv0,v0,-56", "94426b62 lhu $v0, %lo(D_80126B62)($v0)"], [467, "a7a30020 sh\tv1,32(sp)", "a7a30024 sh $v1, 0x24($sp)"], [468, "a7a40024 sh\ta0,36(sp)", "2442ffc8 addiu $v0, $v0, -0x38"]], "passes_tried": null}
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{"ts": "2026-07-22 17:25:00", "addr": null, "name": "func_80133AB0", "reach": null, "klass": "plumbing", "nins": null, "status": "near", "closeness": 0, "where_stuck": "none \u2014 MATCH (per-location family member; ov_SC01_077 sibling adapted with this overlay's D_* symbols)", "best_draft": ".run/backlog_drafts/func_80133AB0.c", "binary": "ov_SC06_018", "source": "worker", "residual": null, "passes_tried": null}
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{"ts": "2026-07-22 21:32:38", "addr": null, "name": "func_8018457C", "reach": null, "klass": "regalloc-order", "nins": null, "status": "failed", "closeness": null, "where_stuck": "none \u2014 MATCH (160 ins). case1-tail needed a $a0 pin on the state temp", "best_draft": ".run/backlog_drafts/func_8018457C.c", "binary": "ov_SC06_018", "source": "worker", "residual": null, "passes_tried": null}
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{"ts": "2026-07-22 21:32:39", "addr": null, "name": "func_8018598C", "reach": null, "klass": "regalloc-order", "nins": null, "status": "near", "closeness": 0, "where_stuck": "none \u2014 MATCH (168/168). $s4/$s5 pins for base+&local28; s32 sVar1 for single lh;", "best_draft": ".run/backlog_drafts/func_8018598C.c", "binary": "ov_SC06_018", "source": "worker", "residual": null, "passes_tried": null}
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{"ts": "2026-07-22 21:32:39", "addr": null, "name": "func_80187DD0", "reach": null, "klass": "regalloc-order", "nins": null, "status": "near", "closeness": 0, "where_stuck": "none \u2014 MATCH (174 ins). Levers: obj = *(*(b+0x20)+0x20) reads via b not a (store side uses a);", "best_draft": ".run/backlog_drafts/func_80187DD0.c", "binary": "ov_SC06_018", "source": "worker", "residual": null, "passes_tried": null}
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{"ts": "2026-07-22 21:32:39", "addr": null, "name": "func_801886B0", "reach": null, "klass": "struct", "nins": null, "status": "near", "closeness": 0, "where_stuck": "none \u2014 MATCH (276 ins, relocation-masked)", "best_draft": ".run/backlog_drafts/func_801886B0.c", "binary": "ov_SC06_018", "source": "worker", "residual": null, "passes_tried": null}
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{"ts": "2026-07-22 21:32:39", "addr": null, "name": "func_8018D870", "reach": null, "klass": "regalloc-order", "nins": null, "status": "failed", "closeness": null, "where_stuck": "none \u2014 MATCH (match_one 380/380, relocation-masked). Levers: &&-DeMorgan for the mult block layout; lhu-corrected reads; split temps (t=func_8012C658 ret->v1, d8p=d8 load-temp->a0, s60/amt pinned $v1/$a1 for the mult chain); accumulate-in-place for the 0xe add; unsigned-short store for ori 0x8800; d8-load-via-temp to force the addu s3,a0 copy (fixes -1 length drift).", "best_draft": ".run/backlog_drafts/func_8018D870.c", "binary": "ov_SC06_018", "source": "worker", "residual": null, "passes_tried": null}
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{"ts": "2026-07-22 21:43:49", "addr": null, "name": "func_8018457C", "reach": null, "klass": "regalloc-order", "nins": null, "status": "failed", "closeness": null, "where_stuck": "none \u2014 MATCH (160 ins). case1-tail needed a $a0 pin on the state temp", "best_draft": ".run/backlog_drafts/func_8018457C.c", "binary": "ov_SC06_018", "source": "worker", "residual": null, "passes_tried": null}
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{"ts": "2026-07-22 21:43:49", "addr": null, "name": "func_8018598C", "reach": null, "klass": "regalloc-order", "nins": null, "status": "near", "closeness": 0, "where_stuck": "none \u2014 MATCH (168/168). $s4/$s5 pins for base+&local28; s32 sVar1 for single lh;", "best_draft": ".run/backlog_drafts/func_8018598C.c", "binary": "ov_SC06_018", "source": "worker", "residual": null, "passes_tried": null}
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{"ts": "2026-07-22 21:43:49", "addr": null, "name": "func_80187DD0", "reach": null, "klass": "regalloc-order", "nins": null, "status": "near", "closeness": 0, "where_stuck": "none \u2014 MATCH (174 ins). Levers: obj = *(*(b+0x20)+0x20) reads via b not a (store side uses a);", "best_draft": ".run/backlog_drafts/func_80187DD0.c", "binary": "ov_SC06_018", "source": "worker", "residual": null, "passes_tried": null}
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{"ts": "2026-07-22 21:43:49", "addr": null, "name": "func_801886B0", "reach": null, "klass": "struct", "nins": null, "status": "near", "closeness": 0, "where_stuck": "none \u2014 MATCH (276 ins, relocation-masked)", "best_draft": ".run/backlog_drafts/func_801886B0.c", "binary": "ov_SC06_018", "source": "worker", "residual": null, "passes_tried": null}
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{"ts": "2026-07-22 21:43:49", "addr": null, "name": "func_8018D870", "reach": null, "klass": "regalloc-order", "nins": null, "status": "failed", "closeness": null, "where_stuck": "none \u2014 MATCH (match_one 380/380, relocation-masked). Levers: &&-DeMorgan for the mult block layout; lhu-corrected reads; split temps (t=func_8012C658 ret->v1, d8p=d8 load-temp->a0, s60/amt pinned $v1/$a1 for the mult chain); accumulate-in-place for the 0xe add; unsigned-short store for ori 0x8800; d8-load-via-temp to force the addu s3,a0 copy (fixes -1 length drift).", "best_draft": ".run/backlog_drafts/func_8018D870.c", "binary": "ov_SC06_018", "source": "worker", "residual": null, "passes_tried": null}
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+1199
-1197
File diff suppressed because it is too large
Load Diff
+3
-3
@@ -2,11 +2,11 @@
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> Generated by `tools/family_hseq.py` from the 134 overlay sigs + per-overlay src stubs. Ranked by TEMPLATABLE byte-weight (PURE+IMM members × nins × 4). The byte-gate is the arbiter.
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**Fleet (overlays):** 88.4% fn / 78.9% instr / 68.2% distinct-code matched. Unmatched: 40,763 instances / 2,760,013 ins (22,685 distinct classes).
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**Fleet (overlays):** 88.4% fn / 79.0% instr / 68.2% distinct-code matched. Unmatched: 40,689 instances / 2,752,359 ins (22,681 distinct classes).
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**Tail cross-check (Phase-25 close):** 27,547 tail fns / 1,106,070 ins → 577 h_seq families ≥2, **161 substantial (nins≥80) / 619,407 ins**.
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**Tail cross-check (Phase-25 close):** 27,544 tail fns / 1,105,717 ins → 577 h_seq families ≥2, **161 substantial (nins≥80) / 619,054 ins**.
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**Full frontier (all unmatched by h_seq):** 2730 target families (≥2 members or a matched sibling) + 3780 singletons (Step-D residue). Substantial: **567 families / 1,465,622 templatable ins**, 70 with a matched sibling (zero-crack). Substantial member classes: 9,253 PURE · 40 IMM · 6 STRUCT-excluded.
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**Full frontier (all unmatched by h_seq):** 2730 target families (≥2 members or a matched sibling) + 3780 singletons (Step-D residue). Substantial: **567 families / 1,457,968 templatable ins**, 74 with a matched sibling (zero-crack). Substantial member classes: 9,179 PURE · 40 IMM · 6 STRUCT-excluded.
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## Top substantial families (by templatable byte-weight)
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+20
-20
@@ -4,16 +4,16 @@
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# cross-binary collapsible-byte leverage: docs/duplicates.cross.md.
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# THREE progress metrics (all matter — see the labels):
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FLEET fn-count byte-ident: 311974 / 353722 = 88.20% (REAL+LINKED+empties; FUNCTION-count, ×134-inflated — one crack counts per overlay)
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FLEET instr-weighted : 10327487 / 13141652 = 78.6% (shipped .text across main + resident + 138 overlays; the decomp.dev-DISPLAY number)
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FLEET distinct-code(uniq): 3802604 / 5634875 = 67.5% (64760/87459 unique fns; the DISTINCT-RE number)
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FLEET fn-count byte-ident: 312012 / 353722 = 88.21% (REAL+LINKED+empties; FUNCTION-count, ×134-inflated — one crack counts per overlay)
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FLEET instr-weighted : 10332238 / 13141652 = 78.6% (shipped .text across main + resident + 138 overlays; the decomp.dev-DISPLAY number)
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FLEET distinct-code(uniq): 3807355 / 5634875 = 67.6% (64798/87459 unique fns; the DISTINCT-RE number)
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MAIN game-code weighted : 436 / 60201 = 0.7% (INCLUDED in the fleet numbers above since 2026-07-22 — roadmap §1 metrics contract; LINKED-excluding Ghidra sig dated 2026-06-14; caveat is R34: no independent second oracle for a PS-X EXE, NOT drift)
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(fleet EXCLUDING main, for continuity with pre-2026-07-22 readings: 10327051 / 13081451 = 78.9%)
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(fleet EXCLUDING main, for continuity with pre-2026-07-22 readings: 10331802 / 13081451 = 79.0%)
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FLEET REAL substantive : 310119 (of which dedup-shared 234571 via 1849 groups / 234615 instances)
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FLEET REAL substantive : 310157 (of which dedup-shared 234571 via 1849 groups / 234615 instances)
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FLEET LINKED PsyQ objs : 959
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FLEET NON_MATCHING : 7 (0 in any default build — G4)
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FLEET INCLUDE_ASM stubs : 41741
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FLEET INCLUDE_ASM stubs : 41703
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FLEET matchable : 353722
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| binary | REAL | shared | LINKED | byte-ident | matchable | byte-ident % |
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@@ -37,7 +37,7 @@ FLEET matchable : 353722
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| ov_SC02_005 | 2333 | 1698 | 0 | 2343 | 2927 | 80.0% |
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| ov_SC02_011 | 2344 | 1705 | 0 | 2355 | 2893 | 81.4% |
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| ov_SC02_015 | 2227 | 1704 | 0 | 2227 | 2414 | 92.3% |
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| ov_SC02_016 | 2259 | 1704 | 0 | 2262 | 2545 | 88.9% |
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| ov_SC02_016 | 2260 | 1704 | 0 | 2263 | 2545 | 88.9% |
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| ov_SC02_017 | 2304 | 1704 | 0 | 2312 | 2732 | 84.6% |
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| ov_SC02_021 | 2233 | 1704 | 0 | 2233 | 2437 | 91.6% |
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| ov_SC02_026 | 2249 | 1702 | 0 | 2255 | 2572 | 87.7% |
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@@ -46,7 +46,7 @@ FLEET matchable : 353722
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| ov_SC02_031 | 2258 | 1703 | 0 | 2263 | 2562 | 88.3% |
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| ov_SC02_035 | 2235 | 1702 | 0 | 2238 | 2520 | 88.8% |
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| ov_SC02_039 | 2219 | 1702 | 0 | 2219 | 2416 | 91.8% |
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| ov_SC02_041 | 2255 | 1702 | 0 | 2258 | 2561 | 88.2% |
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| ov_SC02_041 | 2256 | 1702 | 0 | 2259 | 2561 | 88.2% |
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| ov_SC03_001 | 2355 | 1703 | 0 | 2372 | 2869 | 82.7% |
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| ov_SC03_002 | 2281 | 1707 | 0 | 2296 | 2631 | 87.3% |
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| ov_SC03_003 | 2229 | 1702 | 0 | 2230 | 2423 | 92.0% |
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@@ -98,12 +98,12 @@ FLEET matchable : 353722
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| ov_SC03_125 | 2268 | 1702 | 0 | 2280 | 2588 | 88.1% |
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| ov_SC03_126 | 2230 | 1704 | 0 | 2230 | 2423 | 92.0% |
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| ov_SC04_000 | 2246 | 1706 | 0 | 2255 | 2546 | 88.6% |
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| ov_SC04_002 | 2263 | 1702 | 0 | 2267 | 2636 | 86.0% |
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| ov_SC04_002 | 2264 | 1702 | 0 | 2268 | 2636 | 86.0% |
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| ov_SC04_003 | 2241 | 1702 | 0 | 2245 | 2502 | 89.7% |
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| ov_SC04_004 | 2250 | 1702 | 0 | 2252 | 2558 | 88.0% |
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| ov_SC04_005 | 2258 | 1702 | 0 | 2264 | 2612 | 86.7% |
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| ov_SC04_005 | 2259 | 1702 | 0 | 2265 | 2612 | 86.7% |
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| ov_SC04_006 | 2230 | 1702 | 0 | 2232 | 2454 | 91.0% |
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| ov_SC04_007 | 2251 | 1702 | 0 | 2255 | 2569 | 87.8% |
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| ov_SC04_007 | 2252 | 1702 | 0 | 2256 | 2569 | 87.8% |
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| ov_SC04_008 | 2221 | 1702 | 0 | 2221 | 2415 | 92.0% |
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| ov_SC04_009 | 2237 | 1702 | 0 | 2240 | 2441 | 91.8% |
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| ov_SC04_010 | 2227 | 1702 | 0 | 2228 | 2419 | 92.1% |
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@@ -132,23 +132,23 @@ FLEET matchable : 353722
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| ov_SC05_019 | 2231 | 1704 | 0 | 2231 | 2423 | 92.1% |
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| ov_SC06_000 | 2293 | 1711 | 0 | 2296 | 2691 | 85.3% |
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| ov_SC06_006 | 2246 | 1702 | 0 | 2247 | 2511 | 89.5% |
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| ov_SC06_008 | 2257 | 1704 | 0 | 2263 | 2542 | 89.0% |
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| ov_SC06_010 | 2240 | 1702 | 0 | 2245 | 2517 | 89.2% |
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| ov_SC06_008 | 2261 | 1704 | 0 | 2267 | 2542 | 89.2% |
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| ov_SC06_010 | 2244 | 1702 | 0 | 2249 | 2517 | 89.4% |
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| ov_SC06_011 | 2236 | 1702 | 0 | 2240 | 2468 | 90.8% |
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| ov_SC06_013 | 2229 | 1702 | 0 | 2230 | 2425 | 92.0% |
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| ov_SC06_014 | 2235 | 1702 | 0 | 2237 | 2453 | 91.2% |
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| ov_SC06_015 | 2232 | 1702 | 0 | 2232 | 2421 | 92.2% |
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| ov_SC06_016 | 2250 | 1702 | 0 | 2252 | 2549 | 88.3% |
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| ov_SC06_018 | 2250 | 1705 | 0 | 2257 | 2665 | 84.7% |
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| ov_SC06_018 | 2258 | 1705 | 0 | 2265 | 2665 | 85.0% |
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| ov_SC06_020 | 2239 | 1704 | 0 | 2240 | 2518 | 89.0% |
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| ov_SC06_022 | 2253 | 1702 | 0 | 2261 | 2642 | 85.6% |
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| ov_SC06_024 | 2259 | 1702 | 0 | 2265 | 2667 | 84.9% |
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| ov_SC06_025 | 2250 | 1702 | 0 | 2255 | 2572 | 87.7% |
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| ov_SC06_022 | 2256 | 1702 | 0 | 2264 | 2642 | 85.7% |
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| ov_SC06_024 | 2263 | 1702 | 0 | 2269 | 2667 | 85.1% |
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| ov_SC06_025 | 2251 | 1702 | 0 | 2256 | 2572 | 87.7% |
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| ov_SC06_027 | 2217 | 1702 | 0 | 2218 | 2408 | 92.1% |
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| ov_SC06_029 | 2275 | 1702 | 0 | 2287 | 2662 | 85.9% |
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| ov_SC06_029 | 2276 | 1702 | 0 | 2288 | 2662 | 86.0% |
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| ov_SC06_030 | 2231 | 1702 | 0 | 2231 | 2456 | 90.8% |
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| ov_SC06_032 | 2243 | 1703 | 0 | 2250 | 2658 | 84.7% |
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| ov_SC06_033 | 2246 | 1703 | 0 | 2253 | 2631 | 85.6% |
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| ov_SC06_032 | 2247 | 1703 | 0 | 2254 | 2658 | 84.8% |
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| ov_SC06_033 | 2250 | 1703 | 0 | 2257 | 2631 | 85.8% |
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| ov_SC07_000 | 2246 | 1706 | 0 | 2248 | 2521 | 89.2% |
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| ov_SC07_001 | 2230 | 1702 | 0 | 2232 | 2454 | 91.0% |
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| ov_SC07_002 | 2257 | 1702 | 0 | 2261 | 2579 | 87.7% |
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@@ -3778,7 +3778,42 @@ INCLUDE_ASM("asm/ov_SC02_016/nonmatchings/ov_SC02_016_jr_8017DC70", func_8018282
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void func_8018286C(void) {
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}
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INCLUDE_ASM("asm/ov_SC02_016/nonmatchings/ov_SC02_016_jr_8017DC70", func_80182874);
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extern void func_80015978(s32 a0, s32 *a1);
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extern void func_801829D8();
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void func_80182874(s32 param_1) {
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extern u32 *D_80188720[];
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extern Blk8 D_8018873C[];
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s32 buf[2];
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Blk8 A;
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Blk8 B;
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Blk8 C;
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Blk8 D;
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u32 *basep;
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s32 i;
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s32 j;
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basep = D_80188720[*(s32 *)(param_1 + 0x30)];
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*(s16 *)(param_1 + 0x10) = *(s32 *)(param_1 + 0x2c);
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func_80015978(param_1 + 4, buf);
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for (j = 0; j < 4; j++) {
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*(s16 *)&A = 0;
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*((s16 *)&A + 1) = 0;
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*((s16 *)&A + 2) = 0;
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B = A;
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C = A;
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for (i = 0; i < 4; i++) {
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D = D_8018873C[i];
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*(s16 *)(param_1 + 0x12) = i + j;
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func_801829D8(param_1, buf, &A, &B, &C, &D, param_1 + 0x10, basep + i);
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}
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}
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}
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INCLUDE_ASM("asm/ov_SC02_016/nonmatchings/ov_SC02_016_jr_8017DC70", func_801829D8);
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@@ -3700,7 +3700,42 @@ INCLUDE_ASM("asm/ov_SC02_041/nonmatchings/ov_SC02_041_jr_8017BEBC", func_8017F16
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void func_8017F1A8(void) {
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}
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INCLUDE_ASM("asm/ov_SC02_041/nonmatchings/ov_SC02_041_jr_8017BEBC", func_8017F1B0);
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extern void func_80015978(s32 a0, s32 *a1);
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extern void func_8017F314();
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void func_8017F1B0(s32 param_1) {
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|
||||
extern u32 *D_8019ABEC[];
|
||||
extern Blk8 D_8019AC08[];
|
||||
s32 buf[2];
|
||||
Blk8 A;
|
||||
Blk8 B;
|
||||
Blk8 C;
|
||||
Blk8 D;
|
||||
u32 *basep;
|
||||
s32 i;
|
||||
s32 j;
|
||||
|
||||
basep = D_8019ABEC[*(s32 *)(param_1 + 0x30)];
|
||||
*(s16 *)(param_1 + 0x10) = *(s32 *)(param_1 + 0x2c);
|
||||
func_80015978(param_1 + 4, buf);
|
||||
for (j = 0; j < 4; j++) {
|
||||
*(s16 *)&A = 0;
|
||||
*((s16 *)&A + 1) = 0;
|
||||
*((s16 *)&A + 2) = 0;
|
||||
B = A;
|
||||
C = A;
|
||||
for (i = 0; i < 4; i++) {
|
||||
D = D_8019AC08[i];
|
||||
*(s16 *)(param_1 + 0x12) = i + j;
|
||||
func_8017F314(param_1, buf, &A, &B, &C, &D, param_1 + 0x10, basep + i);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC02_041/nonmatchings/ov_SC02_041_jr_8017BEBC", func_8017F314);
|
||||
|
||||
|
||||
@@ -3799,7 +3799,42 @@ INCLUDE_ASM("asm/ov_SC04_002/nonmatchings/ov_SC04_002_jr_8017BEBC", func_80180E3
|
||||
void func_80180E80(void) {
|
||||
}
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC04_002/nonmatchings/ov_SC04_002_jr_8017BEBC", func_80180E88);
|
||||
|
||||
|
||||
|
||||
extern void func_80015978(s32 a0, s32 *a1);
|
||||
extern void func_80180FEC();
|
||||
|
||||
void func_80180E88(s32 param_1) {
|
||||
|
||||
extern u32 *D_80198D50[];
|
||||
extern Blk8 D_80198D6C[];
|
||||
s32 buf[2];
|
||||
Blk8 A;
|
||||
Blk8 B;
|
||||
Blk8 C;
|
||||
Blk8 D;
|
||||
u32 *basep;
|
||||
s32 i;
|
||||
s32 j;
|
||||
|
||||
basep = D_80198D50[*(s32 *)(param_1 + 0x30)];
|
||||
*(s16 *)(param_1 + 0x10) = *(s32 *)(param_1 + 0x2c);
|
||||
func_80015978(param_1 + 4, buf);
|
||||
for (j = 0; j < 4; j++) {
|
||||
*(s16 *)&A = 0;
|
||||
*((s16 *)&A + 1) = 0;
|
||||
*((s16 *)&A + 2) = 0;
|
||||
B = A;
|
||||
C = A;
|
||||
for (i = 0; i < 4; i++) {
|
||||
D = D_80198D6C[i];
|
||||
*(s16 *)(param_1 + 0x12) = i + j;
|
||||
func_80180FEC(param_1, buf, &A, &B, &C, &D, param_1 + 0x10, basep + i);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC04_002/nonmatchings/ov_SC04_002_jr_8017BEBC", func_80180FEC);
|
||||
|
||||
|
||||
@@ -3752,7 +3752,42 @@ INCLUDE_ASM("asm/ov_SC04_005/nonmatchings/ov_SC04_005_jr_8017BEBC", func_8018025
|
||||
void func_80180298(void) {
|
||||
}
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC04_005/nonmatchings/ov_SC04_005_jr_8017BEBC", func_801802A0);
|
||||
|
||||
|
||||
|
||||
extern void func_80015978(s32 a0, s32 *a1);
|
||||
extern void func_80180404();
|
||||
|
||||
void func_801802A0(s32 param_1) {
|
||||
|
||||
extern u32 *D_801999E4[];
|
||||
extern Blk8 D_80199A00[];
|
||||
s32 buf[2];
|
||||
Blk8 A;
|
||||
Blk8 B;
|
||||
Blk8 C;
|
||||
Blk8 D;
|
||||
u32 *basep;
|
||||
s32 i;
|
||||
s32 j;
|
||||
|
||||
basep = D_801999E4[*(s32 *)(param_1 + 0x30)];
|
||||
*(s16 *)(param_1 + 0x10) = *(s32 *)(param_1 + 0x2c);
|
||||
func_80015978(param_1 + 4, buf);
|
||||
for (j = 0; j < 4; j++) {
|
||||
*(s16 *)&A = 0;
|
||||
*((s16 *)&A + 1) = 0;
|
||||
*((s16 *)&A + 2) = 0;
|
||||
B = A;
|
||||
C = A;
|
||||
for (i = 0; i < 4; i++) {
|
||||
D = D_80199A00[i];
|
||||
*(s16 *)(param_1 + 0x12) = i + j;
|
||||
func_80180404(param_1, buf, &A, &B, &C, &D, param_1 + 0x10, basep + i);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC04_005/nonmatchings/ov_SC04_005_jr_8017BEBC", func_80180404);
|
||||
|
||||
|
||||
@@ -4044,7 +4044,42 @@ INCLUDE_ASM("asm/ov_SC04_007/nonmatchings/ov_SC04_007_jr_8017BEBC", func_8018561
|
||||
void func_80185658(void) {
|
||||
}
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC04_007/nonmatchings/ov_SC04_007_jr_8017BEBC", func_80185660);
|
||||
|
||||
|
||||
|
||||
extern void func_80015978(s32 a0, s32 *a1);
|
||||
extern void func_801857C4();
|
||||
|
||||
void func_80185660(s32 param_1) {
|
||||
|
||||
extern u32 *D_801B26C4[];
|
||||
extern Blk8 D_801B26E0[];
|
||||
s32 buf[2];
|
||||
Blk8 A;
|
||||
Blk8 B;
|
||||
Blk8 C;
|
||||
Blk8 D;
|
||||
u32 *basep;
|
||||
s32 i;
|
||||
s32 j;
|
||||
|
||||
basep = D_801B26C4[*(s32 *)(param_1 + 0x30)];
|
||||
*(s16 *)(param_1 + 0x10) = *(s32 *)(param_1 + 0x2c);
|
||||
func_80015978(param_1 + 4, buf);
|
||||
for (j = 0; j < 4; j++) {
|
||||
*(s16 *)&A = 0;
|
||||
*((s16 *)&A + 1) = 0;
|
||||
*((s16 *)&A + 2) = 0;
|
||||
B = A;
|
||||
C = A;
|
||||
for (i = 0; i < 4; i++) {
|
||||
D = D_801B26E0[i];
|
||||
*(s16 *)(param_1 + 0x12) = i + j;
|
||||
func_801857C4(param_1, buf, &A, &B, &C, &D, param_1 + 0x10, basep + i);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC04_007/nonmatchings/ov_SC04_007_jr_8017BEBC", func_801857C4);
|
||||
|
||||
|
||||
@@ -3934,13 +3934,213 @@ INCLUDE_ASM("asm/ov_SC06_008/nonmatchings/ov_SC06_008_jr_8017C294", func_801821F
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_008/nonmatchings/ov_SC06_008_jr_8017C294", func_801823F0);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_008/nonmatchings/ov_SC06_008_jr_8017C294", func_80182838);
|
||||
|
||||
// @class: struct
|
||||
// @stuck: none — MATCH
|
||||
|
||||
extern int rand(void);
|
||||
extern int func_80143C74(short *, int);
|
||||
extern int func_80047948(int);
|
||||
extern int func_8004787C(int);
|
||||
|
||||
void func_80182838(short *param_1)
|
||||
{
|
||||
|
||||
extern void (*D_8019EF48[])(short *);
|
||||
int iVar3;
|
||||
unsigned int uVar2;
|
||||
short v;
|
||||
|
||||
v = param_1[0x81];
|
||||
if (v != 0) {
|
||||
v = v - 1;
|
||||
param_1[0x81] = v;
|
||||
if (v == 0) {
|
||||
*(unsigned short *)(param_1 + 0x2e) &= 0xbfff;
|
||||
}
|
||||
}
|
||||
D_8019EF48[*(unsigned short *)(param_1 + 1)](param_1);
|
||||
if (*(unsigned short *)param_1 != 0) {
|
||||
if (param_1[0x7e] == 0) {
|
||||
*(int *)(param_1 + 2) = *(int *)(*(int *)(param_1 + 0x32) + 4);
|
||||
*(int *)(param_1 + 4) = *(int *)(*(int *)(param_1 + 0x32) + 8);
|
||||
*(int *)(param_1 + 6) = *(int *)(*(int *)(param_1 + 0x32) + 0xc);
|
||||
*(unsigned short *)(*(int *)(param_1 + 0x10) + 0x10) =
|
||||
*(unsigned short *)(*(int *)(*(int *)(param_1 + 0x32) + 0x20) + 0x10);
|
||||
*(unsigned short *)(*(int *)(param_1 + 0x10) + 0x12) =
|
||||
*(unsigned short *)(*(int *)(*(int *)(param_1 + 0x32) + 0x20) + 0x12);
|
||||
*(unsigned short *)(*(int *)(param_1 + 0x10) + 0x14) =
|
||||
*(unsigned short *)(*(int *)(*(int *)(param_1 + 0x32) + 0x20) + 0x14);
|
||||
}
|
||||
if ((param_1[0x3b] < 5) && ((rand() & 3) == 0) &&
|
||||
((iVar3 = func_80143C74(param_1, 0)) != 0)) {
|
||||
uVar2 = rand();
|
||||
*(int *)(iVar3 + 0x10) = ((uVar2 & 0x7ff) - 0x400) * 0x100;
|
||||
*(unsigned int *)(iVar3 + 0x14) = 0xfff00000;
|
||||
uVar2 = rand();
|
||||
*(int *)(iVar3 + 0x18) = ((uVar2 & 0x7ff) - 0x400) * 0x100;
|
||||
*(int *)(iVar3 + 4) +=
|
||||
func_80047948((int)*(short *)(*(int *)(param_1 + 0x10) + 0x12)) * 0x400;
|
||||
*(int *)(iVar3 + 0xc) -=
|
||||
func_8004787C((int)*(short *)(*(int *)(param_1 + 0x10) + 0x12)) * 0x400;
|
||||
uVar2 = rand();
|
||||
*(short *)(iVar3 + 6) -= 0x20;
|
||||
*(short *)(iVar3 + 6) += (uVar2 & 0x3f);
|
||||
*(short *)(iVar3 + 0xa) -= 0x40;
|
||||
uVar2 = rand();
|
||||
*(short *)(iVar3 + 0xe) -= 0x20;
|
||||
*(short *)(iVar3 + 0xe) += (uVar2 & 0x3f);
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_008/nonmatchings/ov_SC06_008_jr_8017C294", func_80182A48);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_008/nonmatchings/ov_SC06_008_jr_8017C294", func_80182E8C);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_008/nonmatchings/ov_SC06_008_jr_8017C294", func_8018309C);
|
||||
extern s32 rand(void);
|
||||
extern s32 func_80143C74();
|
||||
extern s32 func_80047948(s32 a0);
|
||||
extern s32 func_8004787C(s32 a0);
|
||||
|
||||
void func_80182E8C(s32 a0) {
|
||||
|
||||
extern void (*D_8019EFC0[])(s32);
|
||||
s32 iVar3;
|
||||
s32 iVar4;
|
||||
s32 r;
|
||||
|
||||
{
|
||||
s16 t = *(s16 *)(a0 + 0x102);
|
||||
if (t != 0) {
|
||||
t--;
|
||||
*(s16 *)(a0 + 0x102) = t;
|
||||
if (t == 0) {
|
||||
*(u16 *)(a0 + 0x5C) &= 0xBFFF;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
D_8019EFC0[*(u16 *)(a0 + 2)](a0);
|
||||
|
||||
if (*(u16 *)(a0 + 0) != 0) {
|
||||
if (*(s16 *)(a0 + 0xFC) == 0) {
|
||||
*(s32 *)(a0 + 4) = *(s32 *)(*(s32 *)(a0 + 0x64) + 4);
|
||||
*(s32 *)(a0 + 8) = *(s32 *)(*(s32 *)(a0 + 0x64) + 8);
|
||||
*(s32 *)(a0 + 0xC) = *(s32 *)(*(s32 *)(a0 + 0x64) + 0xC);
|
||||
*(s16 *)(*(s32 *)(a0 + 0x20) + 0x10) =
|
||||
*(s16 *)(*(s32 *)(*(s32 *)(a0 + 0x64) + 0x20) + 0x10);
|
||||
*(s16 *)(*(s32 *)(a0 + 0x20) + 0x12) =
|
||||
*(s16 *)(*(s32 *)(*(s32 *)(a0 + 0x64) + 0x20) + 0x12);
|
||||
*(s16 *)(*(s32 *)(a0 + 0x20) + 0x14) =
|
||||
*(s16 *)(*(s32 *)(*(s32 *)(a0 + 0x64) + 0x20) + 0x14);
|
||||
}
|
||||
if (*(s16 *)(a0 + 0x76) < 5 && (rand() & 3) == 0 &&
|
||||
(iVar3 = func_80143C74(a0, 0)) != 0) {
|
||||
*(s32 *)(iVar3 + 0x10) = ((rand() & 0x7FF) - 0x400) << 8;
|
||||
*(s32 *)(iVar3 + 0x14) = 0xFFF00000;
|
||||
*(s32 *)(iVar3 + 0x18) = ((rand() & 0x7FF) - 0x400) << 8;
|
||||
iVar4 = func_80047948((s32) * (s16 *)(*(s32 *)(a0 + 0x20) + 0x12));
|
||||
*(s32 *)(iVar3 + 4) = *(s32 *)(iVar3 + 4) - iVar4 * 0x400;
|
||||
iVar4 = func_8004787C((s32) * (s16 *)(*(s32 *)(a0 + 0x20) + 0x12));
|
||||
*(s32 *)(iVar3 + 0xC) = *(s32 *)(iVar3 + 0xC) + iVar4 * 0x400;
|
||||
r = rand();
|
||||
{
|
||||
s32 m6 = *(u16 *)(iVar3 + 6) - 0x20;
|
||||
*(u16 *)(iVar3 + 6) = m6 + (r & 0x3F);
|
||||
}
|
||||
*(u16 *)(iVar3 + 0xA) = *(u16 *)(iVar3 + 0xA) - 0x40;
|
||||
r = rand();
|
||||
{
|
||||
s32 mE = *(u16 *)(iVar3 + 0xE) - 0x20;
|
||||
*(u16 *)(iVar3 + 0xE) = mE + (r & 0x3F);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
// @class: schedule
|
||||
// @stuck: none — MATCH. Two levers: (1) split rand()-result into its own var (shared iVar1 forced an extra move a0,v0); (2) reorder decrement before sp[0] to group the two lhu loads as target's scheduler does; (3) materialize &D_80126B96 via a local u16* to CSE the address (lui+addiu once) instead of %hi/%lo split-per-access.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
extern void func_80128EA8();
|
||||
extern void func_8012931C();
|
||||
extern int func_80128ED8();
|
||||
extern u8 *func_8012913C();
|
||||
extern void func_801292C8();
|
||||
extern int func_8012D664();
|
||||
|
||||
extern u16 D_801270C0;
|
||||
|
||||
void func_8018309C(s32 arg0) {
|
||||
|
||||
extern u8 D_8019EDA4;
|
||||
extern u8 D_8019EDB0;
|
||||
extern u16 D_80126B96;
|
||||
s32 iVar1;
|
||||
s32 rv;
|
||||
u8 *p;
|
||||
u16 sp[3];
|
||||
|
||||
if (*(u16 *)(arg0 + 2) == 0) {
|
||||
*(u8 **)(*(s32 *)(arg0 + 0x20) + 0x20) = &D_8019EDA4;
|
||||
*(u32 *)(*(s32 *)(arg0 + 0x20) + 4) |= 0x50000000;
|
||||
*(u8 *)(*(s32 *)(arg0 + 0x20) + 0x27) = 0x59;
|
||||
func_80128EA8(*(s32 *)(arg0 + 0x20), arg0 + 0x24, (s32)&D_8019EDB0);
|
||||
rv = rand();
|
||||
*(s32 *)(arg0 + 0x1c) = 0x10;
|
||||
*(s32 *)(arg0 + 0x2c) = 0x200;
|
||||
*(s16 *)(arg0 + 0x28) = rv % 15;
|
||||
*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) = 0x1200;
|
||||
*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x1a) = 0x1200;
|
||||
*(u16 *)(arg0 + 2) = *(u16 *)(arg0 + 2) + 1;
|
||||
} else if (*(s16 *)&D_801270C0 == 1) {
|
||||
func_8012931C(arg0);
|
||||
func_80128ED8(*(s32 *)(arg0 + 0x20), arg0 + 0x24);
|
||||
*(s32 *)(arg0 + 0x1c) -= 1;
|
||||
if ((rand() & 7) == 0 && (p = func_8012913C(0x22)) != 0) {
|
||||
*(u16 *)(p + 6) = *(u16 *)(arg0 + 6);
|
||||
*(u16 *)(p + 0xa) = *(u16 *)(arg0 + 0xa);
|
||||
*(u16 *)(p + 0xe) = *(u16 *)(arg0 + 0xe);
|
||||
*(s32 *)(p + 0x10) = *(s32 *)(arg0 + 0x10) >> 3;
|
||||
*(s32 *)(p + 0x14) = *(s32 *)(arg0 + 0x14) >> 3;
|
||||
*(s32 *)(p + 0x18) = *(s32 *)(arg0 + 0x18) >> 3;
|
||||
*(s16 *)(p + 0x34) = *(u16 *)(*(s32 *)(arg0 + 0x20) + 0x18) + 1;
|
||||
*(u16 *)(*(s32 *)(p + 0x20) + 0x2c) = 0xc008;
|
||||
}
|
||||
if (*(s32 *)(arg0 + 0x1c) == 0) {
|
||||
func_801292C8(arg0);
|
||||
} else {
|
||||
*(s32 *)(arg0 + 0x14) = 0xffff0000;
|
||||
iVar1 = *(s32 *)(arg0 + 0x2c) + 0x80;
|
||||
*(s32 *)(arg0 + 0x2c) = iVar1;
|
||||
*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) =
|
||||
*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) + (s16)iVar1;
|
||||
*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x1a) =
|
||||
*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x1a) + (s16)*(s32 *)(arg0 + 0x2c);
|
||||
*(s16 *)(arg0 + 0xa) = *(s16 *)(arg0 + 0xa) - 0x20;
|
||||
sp[0] = *(u16 *)(arg0 + 6);
|
||||
sp[1] = *(u16 *)(arg0 + 0xa);
|
||||
sp[2] = *(u16 *)(arg0 + 0xe);
|
||||
if (func_8012D664(sp, 0x10, 0xb4) == 1) {
|
||||
u16 *q = &D_80126B96;
|
||||
*q |= 0x4200;
|
||||
}
|
||||
*(s16 *)(arg0 + 0xa) = *(s16 *)(arg0 + 0xa) + 0x20;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_008/nonmatchings/ov_SC06_008_jr_8017C294", func_80183320);
|
||||
|
||||
@@ -4039,7 +4239,42 @@ INCLUDE_ASM("asm/ov_SC06_008/nonmatchings/ov_SC06_008_jr_8017C294", func_8018436
|
||||
void func_801843B0(void) {
|
||||
}
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_008/nonmatchings/ov_SC06_008_jr_8017C294", func_801843B8);
|
||||
|
||||
|
||||
|
||||
extern void func_80015978(s32 a0, s32 *a1);
|
||||
extern void func_8018451C();
|
||||
|
||||
void func_801843B8(s32 param_1) {
|
||||
|
||||
extern u32 *D_801A69A0[];
|
||||
extern Blk8 D_801A69BC[];
|
||||
s32 buf[2];
|
||||
Blk8 A;
|
||||
Blk8 B;
|
||||
Blk8 C;
|
||||
Blk8 D;
|
||||
u32 *basep;
|
||||
s32 i;
|
||||
s32 j;
|
||||
|
||||
basep = D_801A69A0[*(s32 *)(param_1 + 0x30)];
|
||||
*(s16 *)(param_1 + 0x10) = *(s32 *)(param_1 + 0x2c);
|
||||
func_80015978(param_1 + 4, buf);
|
||||
for (j = 0; j < 4; j++) {
|
||||
*(s16 *)&A = 0;
|
||||
*((s16 *)&A + 1) = 0;
|
||||
*((s16 *)&A + 2) = 0;
|
||||
B = A;
|
||||
C = A;
|
||||
for (i = 0; i < 4; i++) {
|
||||
D = D_801A69BC[i];
|
||||
*(s16 *)(param_1 + 0x12) = i + j;
|
||||
func_8018451C(param_1, buf, &A, &B, &C, &D, param_1 + 0x10, basep + i);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_008/nonmatchings/ov_SC06_008_jr_8017C294", func_8018451C);
|
||||
|
||||
|
||||
@@ -3573,7 +3573,42 @@ INCLUDE_ASM("asm/ov_SC06_010/nonmatchings/ov_SC06_010_jr_8017A4AC", func_8017DD1
|
||||
void func_8017DD60(void) {
|
||||
}
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_010/nonmatchings/ov_SC06_010_jr_8017A4AC", func_8017DD68);
|
||||
|
||||
|
||||
|
||||
extern void func_80015978(s32 a0, s32 *a1);
|
||||
extern void func_8017DECC();
|
||||
|
||||
void func_8017DD68(s32 param_1) {
|
||||
|
||||
extern u32 *D_8018A440[];
|
||||
extern Blk8 D_8018A45C[];
|
||||
s32 buf[2];
|
||||
Blk8 A;
|
||||
Blk8 B;
|
||||
Blk8 C;
|
||||
Blk8 D;
|
||||
u32 *basep;
|
||||
s32 i;
|
||||
s32 j;
|
||||
|
||||
basep = D_8018A440[*(s32 *)(param_1 + 0x30)];
|
||||
*(s16 *)(param_1 + 0x10) = *(s32 *)(param_1 + 0x2c);
|
||||
func_80015978(param_1 + 4, buf);
|
||||
for (j = 0; j < 4; j++) {
|
||||
*(s16 *)&A = 0;
|
||||
*((s16 *)&A + 1) = 0;
|
||||
*((s16 *)&A + 2) = 0;
|
||||
B = A;
|
||||
C = A;
|
||||
for (i = 0; i < 4; i++) {
|
||||
D = D_8018A45C[i];
|
||||
*(s16 *)(param_1 + 0x12) = i + j;
|
||||
func_8017DECC(param_1, buf, &A, &B, &C, &D, param_1 + 0x10, basep + i);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_010/nonmatchings/ov_SC06_010_jr_8017A4AC", func_8017DECC);
|
||||
|
||||
@@ -4121,13 +4156,213 @@ INCLUDE_ASM("asm/ov_SC06_010/nonmatchings/ov_SC06_010_jr_8017A4AC", func_801846A
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_010/nonmatchings/ov_SC06_010_jr_8017A4AC", func_801848A4);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_010/nonmatchings/ov_SC06_010_jr_8017A4AC", func_80184CEC);
|
||||
|
||||
// @class: struct
|
||||
// @stuck: none — MATCH
|
||||
|
||||
extern int rand(void);
|
||||
extern int func_80143C74(short *, int);
|
||||
extern int func_80047948(int);
|
||||
extern int func_8004787C(int);
|
||||
|
||||
void func_80184CEC(short *param_1)
|
||||
{
|
||||
|
||||
extern void (*D_801A723C[])(short *);
|
||||
int iVar3;
|
||||
unsigned int uVar2;
|
||||
short v;
|
||||
|
||||
v = param_1[0x81];
|
||||
if (v != 0) {
|
||||
v = v - 1;
|
||||
param_1[0x81] = v;
|
||||
if (v == 0) {
|
||||
*(unsigned short *)(param_1 + 0x2e) &= 0xbfff;
|
||||
}
|
||||
}
|
||||
D_801A723C[*(unsigned short *)(param_1 + 1)](param_1);
|
||||
if (*(unsigned short *)param_1 != 0) {
|
||||
if (param_1[0x7e] == 0) {
|
||||
*(int *)(param_1 + 2) = *(int *)(*(int *)(param_1 + 0x32) + 4);
|
||||
*(int *)(param_1 + 4) = *(int *)(*(int *)(param_1 + 0x32) + 8);
|
||||
*(int *)(param_1 + 6) = *(int *)(*(int *)(param_1 + 0x32) + 0xc);
|
||||
*(unsigned short *)(*(int *)(param_1 + 0x10) + 0x10) =
|
||||
*(unsigned short *)(*(int *)(*(int *)(param_1 + 0x32) + 0x20) + 0x10);
|
||||
*(unsigned short *)(*(int *)(param_1 + 0x10) + 0x12) =
|
||||
*(unsigned short *)(*(int *)(*(int *)(param_1 + 0x32) + 0x20) + 0x12);
|
||||
*(unsigned short *)(*(int *)(param_1 + 0x10) + 0x14) =
|
||||
*(unsigned short *)(*(int *)(*(int *)(param_1 + 0x32) + 0x20) + 0x14);
|
||||
}
|
||||
if ((param_1[0x3b] < 5) && ((rand() & 3) == 0) &&
|
||||
((iVar3 = func_80143C74(param_1, 0)) != 0)) {
|
||||
uVar2 = rand();
|
||||
*(int *)(iVar3 + 0x10) = ((uVar2 & 0x7ff) - 0x400) * 0x100;
|
||||
*(unsigned int *)(iVar3 + 0x14) = 0xfff00000;
|
||||
uVar2 = rand();
|
||||
*(int *)(iVar3 + 0x18) = ((uVar2 & 0x7ff) - 0x400) * 0x100;
|
||||
*(int *)(iVar3 + 4) +=
|
||||
func_80047948((int)*(short *)(*(int *)(param_1 + 0x10) + 0x12)) * 0x400;
|
||||
*(int *)(iVar3 + 0xc) -=
|
||||
func_8004787C((int)*(short *)(*(int *)(param_1 + 0x10) + 0x12)) * 0x400;
|
||||
uVar2 = rand();
|
||||
*(short *)(iVar3 + 6) -= 0x20;
|
||||
*(short *)(iVar3 + 6) += (uVar2 & 0x3f);
|
||||
*(short *)(iVar3 + 0xa) -= 0x40;
|
||||
uVar2 = rand();
|
||||
*(short *)(iVar3 + 0xe) -= 0x20;
|
||||
*(short *)(iVar3 + 0xe) += (uVar2 & 0x3f);
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_010/nonmatchings/ov_SC06_010_jr_8017A4AC", func_80184EFC);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_010/nonmatchings/ov_SC06_010_jr_8017A4AC", func_80185340);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_010/nonmatchings/ov_SC06_010_jr_8017A4AC", func_80185550);
|
||||
extern s32 rand(void);
|
||||
extern s32 func_80143C74();
|
||||
extern s32 func_80047948(s32 a0);
|
||||
extern s32 func_8004787C(s32 a0);
|
||||
|
||||
void func_80185340(s32 a0) {
|
||||
|
||||
extern void (*D_801A72B4[])(s32);
|
||||
s32 iVar3;
|
||||
s32 iVar4;
|
||||
s32 r;
|
||||
|
||||
{
|
||||
s16 t = *(s16 *)(a0 + 0x102);
|
||||
if (t != 0) {
|
||||
t--;
|
||||
*(s16 *)(a0 + 0x102) = t;
|
||||
if (t == 0) {
|
||||
*(u16 *)(a0 + 0x5C) &= 0xBFFF;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
D_801A72B4[*(u16 *)(a0 + 2)](a0);
|
||||
|
||||
if (*(u16 *)(a0 + 0) != 0) {
|
||||
if (*(s16 *)(a0 + 0xFC) == 0) {
|
||||
*(s32 *)(a0 + 4) = *(s32 *)(*(s32 *)(a0 + 0x64) + 4);
|
||||
*(s32 *)(a0 + 8) = *(s32 *)(*(s32 *)(a0 + 0x64) + 8);
|
||||
*(s32 *)(a0 + 0xC) = *(s32 *)(*(s32 *)(a0 + 0x64) + 0xC);
|
||||
*(s16 *)(*(s32 *)(a0 + 0x20) + 0x10) =
|
||||
*(s16 *)(*(s32 *)(*(s32 *)(a0 + 0x64) + 0x20) + 0x10);
|
||||
*(s16 *)(*(s32 *)(a0 + 0x20) + 0x12) =
|
||||
*(s16 *)(*(s32 *)(*(s32 *)(a0 + 0x64) + 0x20) + 0x12);
|
||||
*(s16 *)(*(s32 *)(a0 + 0x20) + 0x14) =
|
||||
*(s16 *)(*(s32 *)(*(s32 *)(a0 + 0x64) + 0x20) + 0x14);
|
||||
}
|
||||
if (*(s16 *)(a0 + 0x76) < 5 && (rand() & 3) == 0 &&
|
||||
(iVar3 = func_80143C74(a0, 0)) != 0) {
|
||||
*(s32 *)(iVar3 + 0x10) = ((rand() & 0x7FF) - 0x400) << 8;
|
||||
*(s32 *)(iVar3 + 0x14) = 0xFFF00000;
|
||||
*(s32 *)(iVar3 + 0x18) = ((rand() & 0x7FF) - 0x400) << 8;
|
||||
iVar4 = func_80047948((s32) * (s16 *)(*(s32 *)(a0 + 0x20) + 0x12));
|
||||
*(s32 *)(iVar3 + 4) = *(s32 *)(iVar3 + 4) - iVar4 * 0x400;
|
||||
iVar4 = func_8004787C((s32) * (s16 *)(*(s32 *)(a0 + 0x20) + 0x12));
|
||||
*(s32 *)(iVar3 + 0xC) = *(s32 *)(iVar3 + 0xC) + iVar4 * 0x400;
|
||||
r = rand();
|
||||
{
|
||||
s32 m6 = *(u16 *)(iVar3 + 6) - 0x20;
|
||||
*(u16 *)(iVar3 + 6) = m6 + (r & 0x3F);
|
||||
}
|
||||
*(u16 *)(iVar3 + 0xA) = *(u16 *)(iVar3 + 0xA) - 0x40;
|
||||
r = rand();
|
||||
{
|
||||
s32 mE = *(u16 *)(iVar3 + 0xE) - 0x20;
|
||||
*(u16 *)(iVar3 + 0xE) = mE + (r & 0x3F);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
// @class: schedule
|
||||
// @stuck: none — MATCH. Two levers: (1) split rand()-result into its own var (shared iVar1 forced an extra move a0,v0); (2) reorder decrement before sp[0] to group the two lhu loads as target's scheduler does; (3) materialize &D_80126B96 via a local u16* to CSE the address (lui+addiu once) instead of %hi/%lo split-per-access.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
extern void func_80128EA8();
|
||||
extern void func_8012931C();
|
||||
extern int func_80128ED8();
|
||||
extern u8 *func_8012913C();
|
||||
extern void func_801292C8();
|
||||
extern int func_8012D664();
|
||||
|
||||
extern u16 D_801270C0;
|
||||
|
||||
void func_80185550(s32 arg0) {
|
||||
|
||||
extern u8 D_801A7098;
|
||||
extern u8 D_801A70A4;
|
||||
extern u16 D_80126B96;
|
||||
s32 iVar1;
|
||||
s32 rv;
|
||||
u8 *p;
|
||||
u16 sp[3];
|
||||
|
||||
if (*(u16 *)(arg0 + 2) == 0) {
|
||||
*(u8 **)(*(s32 *)(arg0 + 0x20) + 0x20) = &D_801A7098;
|
||||
*(u32 *)(*(s32 *)(arg0 + 0x20) + 4) |= 0x50000000;
|
||||
*(u8 *)(*(s32 *)(arg0 + 0x20) + 0x27) = 0x59;
|
||||
func_80128EA8(*(s32 *)(arg0 + 0x20), arg0 + 0x24, (s32)&D_801A70A4);
|
||||
rv = rand();
|
||||
*(s32 *)(arg0 + 0x1c) = 0x10;
|
||||
*(s32 *)(arg0 + 0x2c) = 0x200;
|
||||
*(s16 *)(arg0 + 0x28) = rv % 15;
|
||||
*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) = 0x1200;
|
||||
*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x1a) = 0x1200;
|
||||
*(u16 *)(arg0 + 2) = *(u16 *)(arg0 + 2) + 1;
|
||||
} else if (*(s16 *)&D_801270C0 == 1) {
|
||||
func_8012931C(arg0);
|
||||
func_80128ED8(*(s32 *)(arg0 + 0x20), arg0 + 0x24);
|
||||
*(s32 *)(arg0 + 0x1c) -= 1;
|
||||
if ((rand() & 7) == 0 && (p = func_8012913C(0x22)) != 0) {
|
||||
*(u16 *)(p + 6) = *(u16 *)(arg0 + 6);
|
||||
*(u16 *)(p + 0xa) = *(u16 *)(arg0 + 0xa);
|
||||
*(u16 *)(p + 0xe) = *(u16 *)(arg0 + 0xe);
|
||||
*(s32 *)(p + 0x10) = *(s32 *)(arg0 + 0x10) >> 3;
|
||||
*(s32 *)(p + 0x14) = *(s32 *)(arg0 + 0x14) >> 3;
|
||||
*(s32 *)(p + 0x18) = *(s32 *)(arg0 + 0x18) >> 3;
|
||||
*(s16 *)(p + 0x34) = *(u16 *)(*(s32 *)(arg0 + 0x20) + 0x18) + 1;
|
||||
*(u16 *)(*(s32 *)(p + 0x20) + 0x2c) = 0xc008;
|
||||
}
|
||||
if (*(s32 *)(arg0 + 0x1c) == 0) {
|
||||
func_801292C8(arg0);
|
||||
} else {
|
||||
*(s32 *)(arg0 + 0x14) = 0xffff0000;
|
||||
iVar1 = *(s32 *)(arg0 + 0x2c) + 0x80;
|
||||
*(s32 *)(arg0 + 0x2c) = iVar1;
|
||||
*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) =
|
||||
*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) + (s16)iVar1;
|
||||
*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x1a) =
|
||||
*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x1a) + (s16)*(s32 *)(arg0 + 0x2c);
|
||||
*(s16 *)(arg0 + 0xa) = *(s16 *)(arg0 + 0xa) - 0x20;
|
||||
sp[0] = *(u16 *)(arg0 + 6);
|
||||
sp[1] = *(u16 *)(arg0 + 0xa);
|
||||
sp[2] = *(u16 *)(arg0 + 0xe);
|
||||
if (func_8012D664(sp, 0x10, 0xb4) == 1) {
|
||||
u16 *q = &D_80126B96;
|
||||
*q |= 0x4200;
|
||||
}
|
||||
*(s16 *)(arg0 + 0xa) = *(s16 *)(arg0 + 0xa) + 0x20;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_010/nonmatchings/ov_SC06_010_jr_8017A4AC", func_801857D4);
|
||||
|
||||
|
||||
@@ -3547,7 +3547,55 @@ void func_8017E1F0(void *a0) {
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_018/nonmatchings/ov_SC06_018_jr_8017C24C", func_8017E22C);
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (83 ins). $s3 is a dual-copy of iVar3 used only in the ==0 tail block; natural C coalesces to one $s0, so pin iVar3=$s0 and iVar3b=$s3 (different hard regs prevent gcc coalescing the copy). Also: outer+inner branch polarity inverted (if!=0 / if!=0 puts both short blocks at the tail as beqz targets); base = (int)D_801D4F2C + idx*0x40 (materialize form, arg to callees).
|
||||
|
||||
extern void func_801465C0(void);
|
||||
extern void func_8001CD9C(int, void*);
|
||||
extern void func_800233CC(void*, unsigned short);
|
||||
extern void func_8017E420(void*);
|
||||
extern void func_8017E3F0(int);
|
||||
extern int rand(void);
|
||||
extern unsigned char D_801D4F2C[];
|
||||
|
||||
void func_8017E22C(int param_1)
|
||||
{
|
||||
register int iVar3 __asm__("$16");
|
||||
register int iVar3b __asm__("$19");
|
||||
int iVar5;
|
||||
short sVar2;
|
||||
|
||||
iVar5 = (int)D_801D4F2C + *(int *)(param_1 + 0x2c) * 0x40;
|
||||
iVar3 = ((int (*)(void))func_801465C0)();
|
||||
*(int *)(param_1 + 0x20) = iVar3;
|
||||
iVar3b = iVar3;
|
||||
if (iVar3 != 0) {
|
||||
((void (*)(int, int))func_8001CD9C)(iVar3, iVar5);
|
||||
((void (*)(int, int))func_800233CC)(iVar5, 0x10);
|
||||
((void (*)(int))func_8017E420)(iVar5);
|
||||
*(unsigned int *)(iVar3 + 4) = *(unsigned int *)(iVar3 + 4) | 0x50000000;
|
||||
if (*(int *)(param_1 + 0x2c) != 0) {
|
||||
sVar2 = (rand() & 3) * 0x800 + 0x1000;
|
||||
*(short *)(iVar3 + 0x1a) = sVar2;
|
||||
*(short *)(iVar3 + 0x18) = sVar2;
|
||||
*(unsigned short *)(param_1 + 0x12) = (rand() & 0xf) + 3;
|
||||
if ((rand() & 1) != 0) {
|
||||
*(short *)(param_1 + 0x12) = -*(short *)(param_1 + 0x12);
|
||||
}
|
||||
*(unsigned short *)(param_1 + 0x1a) = (rand() & 0xf) + 3;
|
||||
if ((rand() & 1) != 0) {
|
||||
*(short *)(param_1 + 0x1a) = -*(short *)(param_1 + 0x1a);
|
||||
}
|
||||
} else {
|
||||
*(short *)(iVar3b + 0x1a) = 0x4000;
|
||||
*(short *)(iVar3b + 0x18) = 0x4000;
|
||||
}
|
||||
*(short *)(param_1 + 2) = *(short *)(param_1 + 2) + 1;
|
||||
} else {
|
||||
func_8017E3F0(param_1);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_018/nonmatchings/ov_SC06_018_jr_8017C24C", func_8017E378);
|
||||
|
||||
@@ -3577,9 +3625,172 @@ INCLUDE_ASM("asm/ov_SC06_018/nonmatchings/ov_SC06_018_jr_8017C24C", func_8017E52
|
||||
void func_8017E56C(void) {
|
||||
}
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_018/nonmatchings/ov_SC06_018_jr_8017C24C", func_8017E574);
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (89 ins). Blk8(align1) struct copies + array indexing (IV-base regalloc)
|
||||
#include "common.h"
|
||||
|
||||
|
||||
|
||||
extern u32 *D_8019717C[];
|
||||
extern Blk8 D_80197198[];
|
||||
extern void func_80015978(s32 a0, s32 *a1);
|
||||
extern void func_8017E6D8();
|
||||
|
||||
void func_8017E574(s32 param_1) {
|
||||
s32 buf[2];
|
||||
Blk8 A;
|
||||
Blk8 B;
|
||||
Blk8 C;
|
||||
Blk8 D;
|
||||
u32 *basep;
|
||||
s32 i;
|
||||
s32 j;
|
||||
|
||||
basep = D_8019717C[*(s32 *)(param_1 + 0x30)];
|
||||
*(s16 *)(param_1 + 0x10) = *(s32 *)(param_1 + 0x2c);
|
||||
func_80015978(param_1 + 4, buf);
|
||||
for (j = 0; j < 4; j++) {
|
||||
*(s16 *)&A = 0;
|
||||
*((s16 *)&A + 1) = 0;
|
||||
*((s16 *)&A + 2) = 0;
|
||||
B = A;
|
||||
C = A;
|
||||
for (i = 0; i < 4; i++) {
|
||||
D = D_80197198[i];
|
||||
*(s16 *)(param_1 + 0x12) = i + j;
|
||||
func_8017E6D8(param_1, buf, &A, &B, &C, &D, param_1 + 0x10, basep + i);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (223 ins). Giant GTE coord transform. Two levers: (1) vy = {int t=vy-0x10; t+(r&0x1f);}
|
||||
// blocks the (r&0x1f)-16 reassoc that materialized -0x10 via `li 0xfff0` (+1 ins); (2) inline the one-shot
|
||||
// r0_00+1 stsv arg so it stays a $v0 temp instead of stealing a saved reg from the reused pSVar6.
|
||||
|
||||
typedef struct { u16 vx, vy, vz, pad; } SVECTOR_8017E6D8; /* 8, align 2 -> lwl/lwr copy */
|
||||
typedef struct { s16 m[3][3]; s16 pad; s32 t[3]; } MATRIX_8017E6D8; /* 0x20 */
|
||||
struct PW8017E6D8 { int w; } __attribute__((packed, aligned(1))); /* 4, align 1 -> lwl/lwr */
|
||||
|
||||
extern void func_80013F3C(s32);
|
||||
extern void RotMatrixZ(s32, void *);
|
||||
extern void func_8004914C(void *);
|
||||
extern void func_800491AC(void *);
|
||||
extern int rand(void);
|
||||
extern void func_80017714(void *);
|
||||
|
||||
extern SVECTOR_8017E6D8 D_801D542C[4];
|
||||
extern struct PW8017E6D8 D_801D544C;
|
||||
extern struct PW8017E6D8 D_801D5450;
|
||||
extern u8 D_801D5454, D_801D5455, D_801D5456, D_801D5458, D_801D5459, D_801D545A;
|
||||
extern int D_801D545C;
|
||||
|
||||
#define gte_ldv0(r0) __asm__ __volatile__( \
|
||||
"lwc2 $0, 0(%0)\n" \
|
||||
"lwc2 $1, 4(%0)\n" \
|
||||
: : "r"(r0) : "memory")
|
||||
|
||||
#define gte_rt() __asm__ __volatile__( \
|
||||
"nop\n" \
|
||||
"nop\n" \
|
||||
"mvmva 1, 0, 0, 0, 0\n" \
|
||||
: : : "memory")
|
||||
|
||||
#define gte_stsv(r0) __asm__ __volatile__( \
|
||||
"mfc2 $12, $9\n" \
|
||||
"mfc2 $13, $10\n" \
|
||||
"mfc2 $14, $11\n" \
|
||||
"sh $12, 0(%0)\n" \
|
||||
"sh $13, 2(%0)\n" \
|
||||
"sh $14, 4(%0)\n" \
|
||||
: : "r"(r0) : "$12", "$13", "$14", "memory")
|
||||
|
||||
void func_8017E6D8(int a, s16 *b, SVECTOR_8017E6D8 *c, SVECTOR_8017E6D8 *d,
|
||||
SVECTOR_8017E6D8 *e, SVECTOR_8017E6D8 *f, s16 *g, struct PW8017E6D8 *h)
|
||||
{
|
||||
MATRIX_8017E6D8 m;
|
||||
SVECTOR_8017E6D8 *r0_00;
|
||||
SVECTOR_8017E6D8 *pSVar6;
|
||||
SVECTOR_8017E6D8 *r0;
|
||||
int r;
|
||||
int mask;
|
||||
|
||||
func_80013F3C((s32)&m);
|
||||
RotMatrixZ(g[0], &m);
|
||||
m.t[0] = b[0];
|
||||
m.t[1] = b[1];
|
||||
m.t[2] = 0;
|
||||
func_8004914C(&m);
|
||||
func_800491AC(&m);
|
||||
|
||||
r0_00 = &D_801D542C[0];
|
||||
if (*(s16 *)(a + 0x12) == 0) {
|
||||
D_801D545C = 0x50000000;
|
||||
D_801D5454 = 0;
|
||||
D_801D5455 = 0;
|
||||
D_801D5456 = 0;
|
||||
D_801D5458 = 0;
|
||||
D_801D5459 = 0;
|
||||
D_801D545A = 0;
|
||||
}
|
||||
D_801D544C = h[0];
|
||||
D_801D5450 = h[1];
|
||||
|
||||
f->vx = f->vx + c->vx;
|
||||
f->vy = f->vy + c->vy;
|
||||
r = rand();
|
||||
mask = f->pad & r;
|
||||
if (*(u16 *)(a + 0x12) & 1)
|
||||
f->vx = f->vx + mask;
|
||||
else
|
||||
f->vx = f->vx - mask;
|
||||
r = rand();
|
||||
{ int t = f->vy - 0x10; f->vy = t + (r & 0x1f); }
|
||||
|
||||
gte_ldv0(c);
|
||||
gte_rt();
|
||||
gte_stsv(r0_00);
|
||||
|
||||
gte_ldv0(f);
|
||||
gte_rt();
|
||||
gte_stsv(r0_00 + 1);
|
||||
|
||||
gte_ldv0(d);
|
||||
gte_rt();
|
||||
r0 = r0_00 + 2;
|
||||
gte_stsv(r0);
|
||||
|
||||
*d = *f;
|
||||
r = rand();
|
||||
d->vx = d->vx - (f->pad & r);
|
||||
|
||||
gte_ldv0(d);
|
||||
gte_rt();
|
||||
pSVar6 = r0_00 + 3;
|
||||
gte_stsv(pSVar6);
|
||||
|
||||
r0_00->vz = ((u16 *)b)[2];
|
||||
func_80017714(r0_00);
|
||||
|
||||
gte_ldv0(e);
|
||||
gte_rt();
|
||||
gte_stsv(r0);
|
||||
|
||||
*e = *f;
|
||||
r = rand();
|
||||
e->vx = e->vx + (f->pad & r);
|
||||
|
||||
gte_ldv0(e);
|
||||
gte_rt();
|
||||
gte_stsv(pSVar6);
|
||||
|
||||
r0_00->vz = ((u16 *)b)[2];
|
||||
func_80017714(r0_00);
|
||||
|
||||
*c = *f;
|
||||
}
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_018/nonmatchings/ov_SC06_018_jr_8017C24C", func_8017E6D8);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_018/nonmatchings/ov_SC06_018_jr_8017C24C", func_8017EA54);
|
||||
|
||||
@@ -3888,7 +4099,59 @@ void func_80180868(void *a0) {
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_018/nonmatchings/ov_SC06_018_jr_8017C24C", func_801808A4);
|
||||
// @class: schedule
|
||||
// @stuck: none — MATCH (132 ins, match_one). Levers: (1) block2 statement order — compute sv1.vz (with the *(p+0xe) load) right after the 2nd call so gcc hoists that load into $v1, forcing the sv2.vx=sv1.vx copy through $a3, which globally pushes every `func*param>>12` product from $a3 to $t0; (2) sv2 store order vx-before-vy; (3) SHARED return-0 join via gotos placed BEFORE the copy block (ret0: before docopy:) — this blocks gcc's conditional-jump-over-jump inversion + return-threading, so the copy block falls through to the epilogue with v0=1 preset in the beqz delay slot (drops the extra `li v0,1`).
|
||||
|
||||
|
||||
extern int func_8004787C(int);
|
||||
extern int func_80047948(int);
|
||||
extern s32 func_80133784(s32, void*, s32);
|
||||
|
||||
int func_801808A4(int param_1, short param_2)
|
||||
{
|
||||
int iVar1;
|
||||
unsigned int uVar2;
|
||||
int iVar3;
|
||||
SVECTOR sv1;
|
||||
SVECTOR sv2;
|
||||
|
||||
if (*(int *)(param_1 + 0xdc) != 0) goto ret0;
|
||||
sv1.vx = *(short *)(param_1 + 6);
|
||||
sv1.vy = *(short *)(param_1 + 0xa) + -0x20;
|
||||
sv1.vz = *(short *)(param_1 + 0xe);
|
||||
iVar1 = func_8004787C(*(unsigned short *)(*(int *)(param_1 + 0x20) + 0x12) & 0xfff);
|
||||
iVar3 = (int)param_2;
|
||||
sv2.vy = sv1.vy;
|
||||
sv2.vx = sv1.vx - (short)(iVar1 * iVar3 >> 0xc);
|
||||
iVar1 = func_80047948(*(unsigned short *)(*(int *)(param_1 + 0x20) + 0x12) & 0xfff);
|
||||
sv2.vz = sv1.vz - (short)(iVar1 * iVar3 >> 0xc);
|
||||
uVar2 = ((int (*)(int, SVECTOR *, SVECTOR *))func_80133784)(1, &sv1, &sv2);
|
||||
if ((uVar2 & 0x8000) != 0) {
|
||||
iVar1 = func_8004787C(*(unsigned short *)(*(int *)(param_1 + 0x20) + 0x12) & 0xfff);
|
||||
*(short *)(param_1 + 6) = sv2.vx + (short)(iVar1 * iVar3 >> 0xc);
|
||||
iVar1 = func_80047948(*(unsigned short *)(*(int *)(param_1 + 0x20) + 0x12) & 0xfff);
|
||||
*(short *)(param_1 + 0xe) = sv2.vz + (short)(iVar1 * iVar3 >> 0xc);
|
||||
return 1;
|
||||
}
|
||||
iVar1 = func_8004787C(*(unsigned short *)(*(int *)(param_1 + 0x20) + 0x12) & 0xfff);
|
||||
sv1.vx = *(short *)(param_1 + 6) - (short)(iVar1 * iVar3 >> 0xc);
|
||||
sv1.vy = *(short *)(param_1 + 0xa) + -0x10;
|
||||
iVar1 = func_80047948(*(unsigned short *)(*(int *)(param_1 + 0x20) + 0x12) & 0xfff);
|
||||
sv1.vz = *(short *)(param_1 + 0xe) - (short)(iVar1 * iVar3 >> 0xc);
|
||||
sv2.vx = sv1.vx;
|
||||
sv2.vy = sv1.vy + 0x20;
|
||||
sv2.vz = sv1.vz;
|
||||
uVar2 = ((int (*)(int, SVECTOR *, SVECTOR *))func_80133784)(1, &sv1, &sv2);
|
||||
if ((uVar2 & 0x6000) == 0) goto docopy;
|
||||
ret0:
|
||||
return 0;
|
||||
docopy:
|
||||
*(int *)(param_1 + 4) = *(int *)(param_1 + 0x38);
|
||||
*(int *)(param_1 + 8) = *(int *)(param_1 + 0x3c);
|
||||
*(int *)(param_1 + 0xc) = *(int *)(param_1 + 0x40);
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_018/nonmatchings/ov_SC06_018_jr_8017C24C", func_80180AB4);
|
||||
|
||||
@@ -3910,13 +4173,214 @@ INCLUDE_ASM("asm/ov_SC06_018/nonmatchings/ov_SC06_018_jr_8017C24C", func_8018200
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_018/nonmatchings/ov_SC06_018_jr_8017C24C", func_801821FC);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_018/nonmatchings/ov_SC06_018_jr_8017C24C", func_80182644);
|
||||
// @class: struct
|
||||
// @stuck: none — MATCH
|
||||
|
||||
extern int rand(void);
|
||||
extern int func_80143C74(short *, int);
|
||||
extern int func_80047948(int);
|
||||
extern int func_8004787C(int);
|
||||
extern void (*D_801AD568[])(short *);
|
||||
|
||||
void func_80182644(short *param_1)
|
||||
{
|
||||
int iVar3;
|
||||
unsigned int uVar2;
|
||||
short v;
|
||||
|
||||
v = param_1[0x81];
|
||||
if (v != 0) {
|
||||
v = v - 1;
|
||||
param_1[0x81] = v;
|
||||
if (v == 0) {
|
||||
*(unsigned short *)(param_1 + 0x2e) &= 0xbfff;
|
||||
}
|
||||
}
|
||||
D_801AD568[*(unsigned short *)(param_1 + 1)](param_1);
|
||||
if (*(unsigned short *)param_1 != 0) {
|
||||
if (param_1[0x7e] == 0) {
|
||||
*(int *)(param_1 + 2) = *(int *)(*(int *)(param_1 + 0x32) + 4);
|
||||
*(int *)(param_1 + 4) = *(int *)(*(int *)(param_1 + 0x32) + 8);
|
||||
*(int *)(param_1 + 6) = *(int *)(*(int *)(param_1 + 0x32) + 0xc);
|
||||
*(unsigned short *)(*(int *)(param_1 + 0x10) + 0x10) =
|
||||
*(unsigned short *)(*(int *)(*(int *)(param_1 + 0x32) + 0x20) + 0x10);
|
||||
*(unsigned short *)(*(int *)(param_1 + 0x10) + 0x12) =
|
||||
*(unsigned short *)(*(int *)(*(int *)(param_1 + 0x32) + 0x20) + 0x12);
|
||||
*(unsigned short *)(*(int *)(param_1 + 0x10) + 0x14) =
|
||||
*(unsigned short *)(*(int *)(*(int *)(param_1 + 0x32) + 0x20) + 0x14);
|
||||
}
|
||||
if ((param_1[0x3b] < 5) && ((rand() & 3) == 0) &&
|
||||
((iVar3 = func_80143C74(param_1, 0)) != 0)) {
|
||||
uVar2 = rand();
|
||||
*(int *)(iVar3 + 0x10) = ((uVar2 & 0x7ff) - 0x400) * 0x100;
|
||||
*(unsigned int *)(iVar3 + 0x14) = 0xfff00000;
|
||||
uVar2 = rand();
|
||||
*(int *)(iVar3 + 0x18) = ((uVar2 & 0x7ff) - 0x400) * 0x100;
|
||||
*(int *)(iVar3 + 4) +=
|
||||
func_80047948((int)*(short *)(*(int *)(param_1 + 0x10) + 0x12)) * 0x400;
|
||||
*(int *)(iVar3 + 0xc) -=
|
||||
func_8004787C((int)*(short *)(*(int *)(param_1 + 0x10) + 0x12)) * 0x400;
|
||||
uVar2 = rand();
|
||||
*(short *)(iVar3 + 6) -= 0x20;
|
||||
*(short *)(iVar3 + 6) += (uVar2 & 0x3f);
|
||||
*(short *)(iVar3 + 0xa) -= 0x40;
|
||||
uVar2 = rand();
|
||||
*(short *)(iVar3 + 0xe) -= 0x20;
|
||||
*(short *)(iVar3 + 0xe) += (uVar2 & 0x3f);
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_018/nonmatchings/ov_SC06_018_jr_8017C24C", func_80182854);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_018/nonmatchings/ov_SC06_018_jr_8017C24C", func_80182C98);
|
||||
// @class: other
|
||||
// @stuck: none — MATCH (132 ins). Blocker was gcc reassociating `mem - 0x20 + masked`
|
||||
// into `mem + (masked - 0x20)` and CSE-hoisting the shared -0x20 (as 0xffe0/ori) into the
|
||||
// freed s0, which then filled the jal func_8004787C delay slot. Fix: split `mem - 0x20`
|
||||
// into its own temp so addiu -0x20 stays on the memory operand at each of the two sites.
|
||||
|
||||
#include "common.h"
|
||||
|
||||
extern s32 rand(void);
|
||||
extern void (*D_801AD5E0[])(s32);
|
||||
extern s32 func_80143C74();
|
||||
extern s32 func_80047948(s32 a0);
|
||||
extern s32 func_8004787C(s32 a0);
|
||||
|
||||
void func_80182C98(s32 a0) {
|
||||
s32 iVar3;
|
||||
s32 iVar4;
|
||||
s32 r;
|
||||
|
||||
{
|
||||
s16 t = *(s16 *)(a0 + 0x102);
|
||||
if (t != 0) {
|
||||
t--;
|
||||
*(s16 *)(a0 + 0x102) = t;
|
||||
if (t == 0) {
|
||||
*(u16 *)(a0 + 0x5C) &= 0xBFFF;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
D_801AD5E0[*(u16 *)(a0 + 2)](a0);
|
||||
|
||||
if (*(u16 *)(a0 + 0) != 0) {
|
||||
if (*(s16 *)(a0 + 0xFC) == 0) {
|
||||
*(s32 *)(a0 + 4) = *(s32 *)(*(s32 *)(a0 + 0x64) + 4);
|
||||
*(s32 *)(a0 + 8) = *(s32 *)(*(s32 *)(a0 + 0x64) + 8);
|
||||
*(s32 *)(a0 + 0xC) = *(s32 *)(*(s32 *)(a0 + 0x64) + 0xC);
|
||||
*(s16 *)(*(s32 *)(a0 + 0x20) + 0x10) =
|
||||
*(s16 *)(*(s32 *)(*(s32 *)(a0 + 0x64) + 0x20) + 0x10);
|
||||
*(s16 *)(*(s32 *)(a0 + 0x20) + 0x12) =
|
||||
*(s16 *)(*(s32 *)(*(s32 *)(a0 + 0x64) + 0x20) + 0x12);
|
||||
*(s16 *)(*(s32 *)(a0 + 0x20) + 0x14) =
|
||||
*(s16 *)(*(s32 *)(*(s32 *)(a0 + 0x64) + 0x20) + 0x14);
|
||||
}
|
||||
if (*(s16 *)(a0 + 0x76) < 5 && (rand() & 3) == 0 &&
|
||||
(iVar3 = func_80143C74(a0, 0)) != 0) {
|
||||
*(s32 *)(iVar3 + 0x10) = ((rand() & 0x7FF) - 0x400) << 8;
|
||||
*(s32 *)(iVar3 + 0x14) = 0xFFF00000;
|
||||
*(s32 *)(iVar3 + 0x18) = ((rand() & 0x7FF) - 0x400) << 8;
|
||||
iVar4 = func_80047948((s32) * (s16 *)(*(s32 *)(a0 + 0x20) + 0x12));
|
||||
*(s32 *)(iVar3 + 4) = *(s32 *)(iVar3 + 4) - iVar4 * 0x400;
|
||||
iVar4 = func_8004787C((s32) * (s16 *)(*(s32 *)(a0 + 0x20) + 0x12));
|
||||
*(s32 *)(iVar3 + 0xC) = *(s32 *)(iVar3 + 0xC) + iVar4 * 0x400;
|
||||
r = rand();
|
||||
{
|
||||
s32 m6 = *(u16 *)(iVar3 + 6) - 0x20;
|
||||
*(u16 *)(iVar3 + 6) = m6 + (r & 0x3F);
|
||||
}
|
||||
*(u16 *)(iVar3 + 0xA) = *(u16 *)(iVar3 + 0xA) - 0x40;
|
||||
r = rand();
|
||||
{
|
||||
s32 mE = *(u16 *)(iVar3 + 0xE) - 0x20;
|
||||
*(u16 *)(iVar3 + 0xE) = mE + (r & 0x3F);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
// @class: schedule
|
||||
// @stuck: none — MATCH. Two levers: (1) split rand()-result into its own var (shared iVar1 forced an extra move a0,v0); (2) reorder decrement before sp[0] to group the two lhu loads as target's scheduler does; (3) materialize &D_80126B96 via a local u16* to CSE the address (lui+addiu once) instead of %hi/%lo split-per-access.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
extern void func_80128EA8();
|
||||
extern void func_8012931C();
|
||||
extern int func_80128ED8();
|
||||
extern u8 *func_8012913C();
|
||||
extern void func_801292C8();
|
||||
extern int func_8012D664();
|
||||
|
||||
extern u8 D_801AD3C4;
|
||||
extern u8 D_801AD3D0;
|
||||
extern u16 D_80126B96;
|
||||
extern u16 D_801270C0;
|
||||
|
||||
void func_80182EA8(s32 arg0) {
|
||||
s32 iVar1;
|
||||
s32 rv;
|
||||
u8 *p;
|
||||
u16 sp[3];
|
||||
|
||||
if (*(u16 *)(arg0 + 2) == 0) {
|
||||
*(u8 **)(*(s32 *)(arg0 + 0x20) + 0x20) = &D_801AD3C4;
|
||||
*(u32 *)(*(s32 *)(arg0 + 0x20) + 4) |= 0x50000000;
|
||||
*(u8 *)(*(s32 *)(arg0 + 0x20) + 0x27) = 0x59;
|
||||
func_80128EA8(*(s32 *)(arg0 + 0x20), arg0 + 0x24, (s32)&D_801AD3D0);
|
||||
rv = rand();
|
||||
*(s32 *)(arg0 + 0x1c) = 0x10;
|
||||
*(s32 *)(arg0 + 0x2c) = 0x200;
|
||||
*(s16 *)(arg0 + 0x28) = rv % 15;
|
||||
*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) = 0x1200;
|
||||
*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x1a) = 0x1200;
|
||||
*(u16 *)(arg0 + 2) = *(u16 *)(arg0 + 2) + 1;
|
||||
} else if (*(s16 *)&D_801270C0 == 1) {
|
||||
func_8012931C(arg0);
|
||||
func_80128ED8(*(s32 *)(arg0 + 0x20), arg0 + 0x24);
|
||||
*(s32 *)(arg0 + 0x1c) -= 1;
|
||||
if ((rand() & 7) == 0 && (p = func_8012913C(0x22)) != 0) {
|
||||
*(u16 *)(p + 6) = *(u16 *)(arg0 + 6);
|
||||
*(u16 *)(p + 0xa) = *(u16 *)(arg0 + 0xa);
|
||||
*(u16 *)(p + 0xe) = *(u16 *)(arg0 + 0xe);
|
||||
*(s32 *)(p + 0x10) = *(s32 *)(arg0 + 0x10) >> 3;
|
||||
*(s32 *)(p + 0x14) = *(s32 *)(arg0 + 0x14) >> 3;
|
||||
*(s32 *)(p + 0x18) = *(s32 *)(arg0 + 0x18) >> 3;
|
||||
*(s16 *)(p + 0x34) = *(u16 *)(*(s32 *)(arg0 + 0x20) + 0x18) + 1;
|
||||
*(u16 *)(*(s32 *)(p + 0x20) + 0x2c) = 0xc008;
|
||||
}
|
||||
if (*(s32 *)(arg0 + 0x1c) == 0) {
|
||||
func_801292C8(arg0);
|
||||
} else {
|
||||
*(s32 *)(arg0 + 0x14) = 0xffff0000;
|
||||
iVar1 = *(s32 *)(arg0 + 0x2c) + 0x80;
|
||||
*(s32 *)(arg0 + 0x2c) = iVar1;
|
||||
*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) =
|
||||
*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) + (s16)iVar1;
|
||||
*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x1a) =
|
||||
*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x1a) + (s16)*(s32 *)(arg0 + 0x2c);
|
||||
*(s16 *)(arg0 + 0xa) = *(s16 *)(arg0 + 0xa) - 0x20;
|
||||
sp[0] = *(u16 *)(arg0 + 6);
|
||||
sp[1] = *(u16 *)(arg0 + 0xa);
|
||||
sp[2] = *(u16 *)(arg0 + 0xe);
|
||||
if (func_8012D664(sp, 0x10, 0xb4) == 1) {
|
||||
u16 *q = &D_80126B96;
|
||||
*q |= 0x4200;
|
||||
}
|
||||
*(s16 *)(arg0 + 0xa) = *(s16 *)(arg0 + 0xa) + 0x20;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_018/nonmatchings/ov_SC06_018_jr_8017C24C", func_80182EA8);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_018/nonmatchings/ov_SC06_018_jr_8017C24C", func_8018312C);
|
||||
|
||||
@@ -4018,7 +4482,98 @@ INCLUDE_ASM("asm/ov_SC06_018/nonmatchings/ov_SC06_018_jr_8017C24C", func_8018544
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_018/nonmatchings/ov_SC06_018_jr_8017C24C", func_801854C0);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_018/nonmatchings/ov_SC06_018_jr_8017C24C", func_801854F8);
|
||||
// @class: schedule
|
||||
// @stuck: none — MATCH (181 ins, relocation-masked)
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
extern s32 func_8012BEE8();
|
||||
extern void func_8012A828(s32 a0, void *a1);
|
||||
extern s32 func_8012B8E4(s32 a0, s32 a1);
|
||||
extern void func_80189380(s32 a0, void *a1, void *a2, s32 a3);
|
||||
extern void func_8018931C(s32 a0, void *a1, s32 a2, s32 a3, s32 a4, s32 a5);
|
||||
extern s32 func_80132EF4(s32 a0, s32 a1);
|
||||
extern void func_80049CAC(s32, s32);
|
||||
extern void func_800484EC(s32, s32, s32);
|
||||
extern void func_80189E60(s32 a0, s32 a1);
|
||||
extern void func_8012F214(s32, s32, s32);
|
||||
extern s32 func_8012BCCC(s32 a0);
|
||||
extern s32 func_80189284(void *a0, s32 a1, s32 a2);
|
||||
extern s32 rand(void);
|
||||
|
||||
extern u8 D_801CC3D0[];
|
||||
extern u8 D_801CC358[];
|
||||
extern u8 D_801B517C[];
|
||||
extern u8 D_801B518C[];
|
||||
extern u8 D_801B5164[];
|
||||
|
||||
void func_801854F8(s32 p) {
|
||||
s32 buf58[8]; /* auStack_58 sp+0x18 (0x20) */
|
||||
s32 g38[4]; /* uStack_38/34, iStack_30 sp+0x38 (0x10) */
|
||||
u16 g28[4]; /* uStack_28/26/24 sp+0x48 (0x08) */
|
||||
u16 out[4]; /* func_80189380 output sp+0x50 (0x08) */
|
||||
s32 buf18[2]; /* auStack_18 sp+0x58 (0x08) */
|
||||
s32 i;
|
||||
s32 e;
|
||||
|
||||
if (*(u16 *)(p + 0x34) == 0) {
|
||||
if (func_8012BEE8() == 0) return;
|
||||
func_8012A828(p, D_801CC3D0);
|
||||
*(u16 *)(p + 0x34) += 1;
|
||||
}
|
||||
if (*(s32 *)(p + 0x94) < 0xe) {
|
||||
*(u16 *)(*(s32 *)(p + 0x20) + 0x12) += func_8012B8E4(p, 8);
|
||||
}
|
||||
if (*(s32 *)(p + 0x94) == 0xe) {
|
||||
func_80189380(p, D_801B517C, out, 0xb);
|
||||
func_8018931C(p, out, 0x282, 0, 0, 0);
|
||||
e = func_80132EF4(p, 0x22);
|
||||
if (e != 0) {
|
||||
*(u16 *)(e + 0x34) = 0x7002;
|
||||
*(u16 *)(e + 6) = out[0];
|
||||
*(u16 *)(e + 0xa) = out[1];
|
||||
*(u16 *)(e + 0xe) = out[2];
|
||||
*(u16 *)(*(s32 *)(e + 0x20) + 0x2c) = 0xc006;
|
||||
}
|
||||
g28[0] = 0x40;
|
||||
g28[1] = *(u16 *)(*(s32 *)(p + 0x20) + 0x12);
|
||||
g28[2] = 0;
|
||||
((void (*)(void *, void *))func_80049CAC)(g28, buf58);
|
||||
i = 0;
|
||||
do {
|
||||
e = func_80132EF4(p, 0x22);
|
||||
if (e != 0) {
|
||||
g38[1] = 0;
|
||||
g38[0] = 0;
|
||||
g38[2] = (rand() % 5 + 4) << 16;
|
||||
((void (*)(void *, void *, s32))func_800484EC)(buf58, g38, e + 0x10);
|
||||
*(u16 *)(e + 0x34) = ((rand() % 2 + 2) << 12) | 1;
|
||||
*(u16 *)(*(s32 *)(e + 0x20) + 0x2c) = 0xc006;
|
||||
func_80189380(p, D_801B518C + i * 8, out, 0xb);
|
||||
*(u16 *)(e + 6) = out[0];
|
||||
*(u16 *)(e + 0xa) = out[1];
|
||||
*(u16 *)(e + 0xe) = out[2];
|
||||
}
|
||||
i++;
|
||||
} while (i < 5);
|
||||
func_80189E60(p, 0x8be);
|
||||
}
|
||||
if (*(u16 *)(p + 0x72) & 0x4000) {
|
||||
((void (*)(s32, void *, void *))func_8012F214)(p, D_801B5164, buf18);
|
||||
if (0x63fff < func_8012BCCC(p) ||
|
||||
func_80189284(buf18, *(s16 *)(*(s32 *)(p + 0x20) + 0x12), 0x380) == 0) {
|
||||
*(u16 *)(p + 2) = 0x1b;
|
||||
func_8012A828(p, D_801CC358);
|
||||
*(s32 *)(p + 0x1c) = 0x20;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_018/nonmatchings/ov_SC06_018_jr_8017C24C", func_801857CC);
|
||||
|
||||
|
||||
@@ -4274,13 +4274,213 @@ INCLUDE_ASM("asm/ov_SC06_022/nonmatchings/ov_SC06_022_jr_8017BEBC", func_80189EB
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_022/nonmatchings/ov_SC06_022_jr_8017BEBC", func_8018A0AC);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_022/nonmatchings/ov_SC06_022_jr_8017BEBC", func_8018A4F4);
|
||||
|
||||
// @class: struct
|
||||
// @stuck: none — MATCH
|
||||
|
||||
extern int rand(void);
|
||||
extern int func_80143C74(short *, int);
|
||||
extern int func_80047948(int);
|
||||
extern int func_8004787C(int);
|
||||
|
||||
void func_8018A4F4(short *param_1)
|
||||
{
|
||||
|
||||
extern void (*D_801D5B50[])(short *);
|
||||
int iVar3;
|
||||
unsigned int uVar2;
|
||||
short v;
|
||||
|
||||
v = param_1[0x81];
|
||||
if (v != 0) {
|
||||
v = v - 1;
|
||||
param_1[0x81] = v;
|
||||
if (v == 0) {
|
||||
*(unsigned short *)(param_1 + 0x2e) &= 0xbfff;
|
||||
}
|
||||
}
|
||||
D_801D5B50[*(unsigned short *)(param_1 + 1)](param_1);
|
||||
if (*(unsigned short *)param_1 != 0) {
|
||||
if (param_1[0x7e] == 0) {
|
||||
*(int *)(param_1 + 2) = *(int *)(*(int *)(param_1 + 0x32) + 4);
|
||||
*(int *)(param_1 + 4) = *(int *)(*(int *)(param_1 + 0x32) + 8);
|
||||
*(int *)(param_1 + 6) = *(int *)(*(int *)(param_1 + 0x32) + 0xc);
|
||||
*(unsigned short *)(*(int *)(param_1 + 0x10) + 0x10) =
|
||||
*(unsigned short *)(*(int *)(*(int *)(param_1 + 0x32) + 0x20) + 0x10);
|
||||
*(unsigned short *)(*(int *)(param_1 + 0x10) + 0x12) =
|
||||
*(unsigned short *)(*(int *)(*(int *)(param_1 + 0x32) + 0x20) + 0x12);
|
||||
*(unsigned short *)(*(int *)(param_1 + 0x10) + 0x14) =
|
||||
*(unsigned short *)(*(int *)(*(int *)(param_1 + 0x32) + 0x20) + 0x14);
|
||||
}
|
||||
if ((param_1[0x3b] < 5) && ((rand() & 3) == 0) &&
|
||||
((iVar3 = func_80143C74(param_1, 0)) != 0)) {
|
||||
uVar2 = rand();
|
||||
*(int *)(iVar3 + 0x10) = ((uVar2 & 0x7ff) - 0x400) * 0x100;
|
||||
*(unsigned int *)(iVar3 + 0x14) = 0xfff00000;
|
||||
uVar2 = rand();
|
||||
*(int *)(iVar3 + 0x18) = ((uVar2 & 0x7ff) - 0x400) * 0x100;
|
||||
*(int *)(iVar3 + 4) +=
|
||||
func_80047948((int)*(short *)(*(int *)(param_1 + 0x10) + 0x12)) * 0x400;
|
||||
*(int *)(iVar3 + 0xc) -=
|
||||
func_8004787C((int)*(short *)(*(int *)(param_1 + 0x10) + 0x12)) * 0x400;
|
||||
uVar2 = rand();
|
||||
*(short *)(iVar3 + 6) -= 0x20;
|
||||
*(short *)(iVar3 + 6) += (uVar2 & 0x3f);
|
||||
*(short *)(iVar3 + 0xa) -= 0x40;
|
||||
uVar2 = rand();
|
||||
*(short *)(iVar3 + 0xe) -= 0x20;
|
||||
*(short *)(iVar3 + 0xe) += (uVar2 & 0x3f);
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_022/nonmatchings/ov_SC06_022_jr_8017BEBC", func_8018A704);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_022/nonmatchings/ov_SC06_022_jr_8017BEBC", func_8018AB48);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_022/nonmatchings/ov_SC06_022_jr_8017BEBC", func_8018AD58);
|
||||
extern s32 rand(void);
|
||||
extern s32 func_80143C74();
|
||||
extern s32 func_80047948(s32 a0);
|
||||
extern s32 func_8004787C(s32 a0);
|
||||
|
||||
void func_8018AB48(s32 a0) {
|
||||
|
||||
extern void (*D_801D5BC8[])(s32);
|
||||
s32 iVar3;
|
||||
s32 iVar4;
|
||||
s32 r;
|
||||
|
||||
{
|
||||
s16 t = *(s16 *)(a0 + 0x102);
|
||||
if (t != 0) {
|
||||
t--;
|
||||
*(s16 *)(a0 + 0x102) = t;
|
||||
if (t == 0) {
|
||||
*(u16 *)(a0 + 0x5C) &= 0xBFFF;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
D_801D5BC8[*(u16 *)(a0 + 2)](a0);
|
||||
|
||||
if (*(u16 *)(a0 + 0) != 0) {
|
||||
if (*(s16 *)(a0 + 0xFC) == 0) {
|
||||
*(s32 *)(a0 + 4) = *(s32 *)(*(s32 *)(a0 + 0x64) + 4);
|
||||
*(s32 *)(a0 + 8) = *(s32 *)(*(s32 *)(a0 + 0x64) + 8);
|
||||
*(s32 *)(a0 + 0xC) = *(s32 *)(*(s32 *)(a0 + 0x64) + 0xC);
|
||||
*(s16 *)(*(s32 *)(a0 + 0x20) + 0x10) =
|
||||
*(s16 *)(*(s32 *)(*(s32 *)(a0 + 0x64) + 0x20) + 0x10);
|
||||
*(s16 *)(*(s32 *)(a0 + 0x20) + 0x12) =
|
||||
*(s16 *)(*(s32 *)(*(s32 *)(a0 + 0x64) + 0x20) + 0x12);
|
||||
*(s16 *)(*(s32 *)(a0 + 0x20) + 0x14) =
|
||||
*(s16 *)(*(s32 *)(*(s32 *)(a0 + 0x64) + 0x20) + 0x14);
|
||||
}
|
||||
if (*(s16 *)(a0 + 0x76) < 5 && (rand() & 3) == 0 &&
|
||||
(iVar3 = func_80143C74(a0, 0)) != 0) {
|
||||
*(s32 *)(iVar3 + 0x10) = ((rand() & 0x7FF) - 0x400) << 8;
|
||||
*(s32 *)(iVar3 + 0x14) = 0xFFF00000;
|
||||
*(s32 *)(iVar3 + 0x18) = ((rand() & 0x7FF) - 0x400) << 8;
|
||||
iVar4 = func_80047948((s32) * (s16 *)(*(s32 *)(a0 + 0x20) + 0x12));
|
||||
*(s32 *)(iVar3 + 4) = *(s32 *)(iVar3 + 4) - iVar4 * 0x400;
|
||||
iVar4 = func_8004787C((s32) * (s16 *)(*(s32 *)(a0 + 0x20) + 0x12));
|
||||
*(s32 *)(iVar3 + 0xC) = *(s32 *)(iVar3 + 0xC) + iVar4 * 0x400;
|
||||
r = rand();
|
||||
{
|
||||
s32 m6 = *(u16 *)(iVar3 + 6) - 0x20;
|
||||
*(u16 *)(iVar3 + 6) = m6 + (r & 0x3F);
|
||||
}
|
||||
*(u16 *)(iVar3 + 0xA) = *(u16 *)(iVar3 + 0xA) - 0x40;
|
||||
r = rand();
|
||||
{
|
||||
s32 mE = *(u16 *)(iVar3 + 0xE) - 0x20;
|
||||
*(u16 *)(iVar3 + 0xE) = mE + (r & 0x3F);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
// @class: schedule
|
||||
// @stuck: none — MATCH. Two levers: (1) split rand()-result into its own var (shared iVar1 forced an extra move a0,v0); (2) reorder decrement before sp[0] to group the two lhu loads as target's scheduler does; (3) materialize &D_80126B96 via a local u16* to CSE the address (lui+addiu once) instead of %hi/%lo split-per-access.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
extern void func_80128EA8();
|
||||
extern void func_8012931C();
|
||||
extern int func_80128ED8();
|
||||
extern u8 *func_8012913C();
|
||||
extern void func_801292C8();
|
||||
extern int func_8012D664();
|
||||
|
||||
extern u16 D_801270C0;
|
||||
|
||||
void func_8018AD58(s32 arg0) {
|
||||
|
||||
extern u8 D_801D59AC;
|
||||
extern u8 D_801D59B8;
|
||||
extern u16 D_80126B96;
|
||||
s32 iVar1;
|
||||
s32 rv;
|
||||
u8 *p;
|
||||
u16 sp[3];
|
||||
|
||||
if (*(u16 *)(arg0 + 2) == 0) {
|
||||
*(u8 **)(*(s32 *)(arg0 + 0x20) + 0x20) = &D_801D59AC;
|
||||
*(u32 *)(*(s32 *)(arg0 + 0x20) + 4) |= 0x50000000;
|
||||
*(u8 *)(*(s32 *)(arg0 + 0x20) + 0x27) = 0x59;
|
||||
func_80128EA8(*(s32 *)(arg0 + 0x20), arg0 + 0x24, (s32)&D_801D59B8);
|
||||
rv = rand();
|
||||
*(s32 *)(arg0 + 0x1c) = 0x10;
|
||||
*(s32 *)(arg0 + 0x2c) = 0x200;
|
||||
*(s16 *)(arg0 + 0x28) = rv % 15;
|
||||
*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) = 0x1200;
|
||||
*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x1a) = 0x1200;
|
||||
*(u16 *)(arg0 + 2) = *(u16 *)(arg0 + 2) + 1;
|
||||
} else if (*(s16 *)&D_801270C0 == 1) {
|
||||
func_8012931C(arg0);
|
||||
func_80128ED8(*(s32 *)(arg0 + 0x20), arg0 + 0x24);
|
||||
*(s32 *)(arg0 + 0x1c) -= 1;
|
||||
if ((rand() & 7) == 0 && (p = func_8012913C(0x22)) != 0) {
|
||||
*(u16 *)(p + 6) = *(u16 *)(arg0 + 6);
|
||||
*(u16 *)(p + 0xa) = *(u16 *)(arg0 + 0xa);
|
||||
*(u16 *)(p + 0xe) = *(u16 *)(arg0 + 0xe);
|
||||
*(s32 *)(p + 0x10) = *(s32 *)(arg0 + 0x10) >> 3;
|
||||
*(s32 *)(p + 0x14) = *(s32 *)(arg0 + 0x14) >> 3;
|
||||
*(s32 *)(p + 0x18) = *(s32 *)(arg0 + 0x18) >> 3;
|
||||
*(s16 *)(p + 0x34) = *(u16 *)(*(s32 *)(arg0 + 0x20) + 0x18) + 1;
|
||||
*(u16 *)(*(s32 *)(p + 0x20) + 0x2c) = 0xc008;
|
||||
}
|
||||
if (*(s32 *)(arg0 + 0x1c) == 0) {
|
||||
func_801292C8(arg0);
|
||||
} else {
|
||||
*(s32 *)(arg0 + 0x14) = 0xffff0000;
|
||||
iVar1 = *(s32 *)(arg0 + 0x2c) + 0x80;
|
||||
*(s32 *)(arg0 + 0x2c) = iVar1;
|
||||
*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) =
|
||||
*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) + (s16)iVar1;
|
||||
*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x1a) =
|
||||
*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x1a) + (s16)*(s32 *)(arg0 + 0x2c);
|
||||
*(s16 *)(arg0 + 0xa) = *(s16 *)(arg0 + 0xa) - 0x20;
|
||||
sp[0] = *(u16 *)(arg0 + 6);
|
||||
sp[1] = *(u16 *)(arg0 + 0xa);
|
||||
sp[2] = *(u16 *)(arg0 + 0xe);
|
||||
if (func_8012D664(sp, 0x10, 0xb4) == 1) {
|
||||
u16 *q = &D_80126B96;
|
||||
*q |= 0x4200;
|
||||
}
|
||||
*(s16 *)(arg0 + 0xa) = *(s16 *)(arg0 + 0xa) + 0x20;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_022/nonmatchings/ov_SC06_022_jr_8017BEBC", func_8018AFDC);
|
||||
|
||||
|
||||
@@ -3754,7 +3754,42 @@ INCLUDE_ASM("asm/ov_SC06_024/nonmatchings/ov_SC06_024_jr_8017BEBC", func_8018180
|
||||
void func_8018184C(void) {
|
||||
}
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_024/nonmatchings/ov_SC06_024_jr_8017BEBC", func_80181854);
|
||||
|
||||
|
||||
|
||||
extern void func_80015978(s32 a0, s32 *a1);
|
||||
extern void func_801819B8();
|
||||
|
||||
void func_80181854(s32 param_1) {
|
||||
|
||||
extern u32 *D_80193844[];
|
||||
extern Blk8 D_80193860[];
|
||||
s32 buf[2];
|
||||
Blk8 A;
|
||||
Blk8 B;
|
||||
Blk8 C;
|
||||
Blk8 D;
|
||||
u32 *basep;
|
||||
s32 i;
|
||||
s32 j;
|
||||
|
||||
basep = D_80193844[*(s32 *)(param_1 + 0x30)];
|
||||
*(s16 *)(param_1 + 0x10) = *(s32 *)(param_1 + 0x2c);
|
||||
func_80015978(param_1 + 4, buf);
|
||||
for (j = 0; j < 4; j++) {
|
||||
*(s16 *)&A = 0;
|
||||
*((s16 *)&A + 1) = 0;
|
||||
*((s16 *)&A + 2) = 0;
|
||||
B = A;
|
||||
C = A;
|
||||
for (i = 0; i < 4; i++) {
|
||||
D = D_80193860[i];
|
||||
*(s16 *)(param_1 + 0x12) = i + j;
|
||||
func_801819B8(param_1, buf, &A, &B, &C, &D, param_1 + 0x10, basep + i);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_024/nonmatchings/ov_SC06_024_jr_8017BEBC", func_801819B8);
|
||||
|
||||
@@ -4173,13 +4208,213 @@ INCLUDE_ASM("asm/ov_SC06_024/nonmatchings/ov_SC06_024_jr_8017BEBC", func_8018C38
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_024/nonmatchings/ov_SC06_024_jr_8017BEBC", func_8018C584);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_024/nonmatchings/ov_SC06_024_jr_8017BEBC", func_8018C9CC);
|
||||
|
||||
// @class: struct
|
||||
// @stuck: none — MATCH
|
||||
|
||||
extern int rand(void);
|
||||
extern int func_80143C74(short *, int);
|
||||
extern int func_80047948(int);
|
||||
extern int func_8004787C(int);
|
||||
|
||||
void func_8018C9CC(short *param_1)
|
||||
{
|
||||
|
||||
extern void (*D_801D4C94[])(short *);
|
||||
int iVar3;
|
||||
unsigned int uVar2;
|
||||
short v;
|
||||
|
||||
v = param_1[0x81];
|
||||
if (v != 0) {
|
||||
v = v - 1;
|
||||
param_1[0x81] = v;
|
||||
if (v == 0) {
|
||||
*(unsigned short *)(param_1 + 0x2e) &= 0xbfff;
|
||||
}
|
||||
}
|
||||
D_801D4C94[*(unsigned short *)(param_1 + 1)](param_1);
|
||||
if (*(unsigned short *)param_1 != 0) {
|
||||
if (param_1[0x7e] == 0) {
|
||||
*(int *)(param_1 + 2) = *(int *)(*(int *)(param_1 + 0x32) + 4);
|
||||
*(int *)(param_1 + 4) = *(int *)(*(int *)(param_1 + 0x32) + 8);
|
||||
*(int *)(param_1 + 6) = *(int *)(*(int *)(param_1 + 0x32) + 0xc);
|
||||
*(unsigned short *)(*(int *)(param_1 + 0x10) + 0x10) =
|
||||
*(unsigned short *)(*(int *)(*(int *)(param_1 + 0x32) + 0x20) + 0x10);
|
||||
*(unsigned short *)(*(int *)(param_1 + 0x10) + 0x12) =
|
||||
*(unsigned short *)(*(int *)(*(int *)(param_1 + 0x32) + 0x20) + 0x12);
|
||||
*(unsigned short *)(*(int *)(param_1 + 0x10) + 0x14) =
|
||||
*(unsigned short *)(*(int *)(*(int *)(param_1 + 0x32) + 0x20) + 0x14);
|
||||
}
|
||||
if ((param_1[0x3b] < 5) && ((rand() & 3) == 0) &&
|
||||
((iVar3 = func_80143C74(param_1, 0)) != 0)) {
|
||||
uVar2 = rand();
|
||||
*(int *)(iVar3 + 0x10) = ((uVar2 & 0x7ff) - 0x400) * 0x100;
|
||||
*(unsigned int *)(iVar3 + 0x14) = 0xfff00000;
|
||||
uVar2 = rand();
|
||||
*(int *)(iVar3 + 0x18) = ((uVar2 & 0x7ff) - 0x400) * 0x100;
|
||||
*(int *)(iVar3 + 4) +=
|
||||
func_80047948((int)*(short *)(*(int *)(param_1 + 0x10) + 0x12)) * 0x400;
|
||||
*(int *)(iVar3 + 0xc) -=
|
||||
func_8004787C((int)*(short *)(*(int *)(param_1 + 0x10) + 0x12)) * 0x400;
|
||||
uVar2 = rand();
|
||||
*(short *)(iVar3 + 6) -= 0x20;
|
||||
*(short *)(iVar3 + 6) += (uVar2 & 0x3f);
|
||||
*(short *)(iVar3 + 0xa) -= 0x40;
|
||||
uVar2 = rand();
|
||||
*(short *)(iVar3 + 0xe) -= 0x20;
|
||||
*(short *)(iVar3 + 0xe) += (uVar2 & 0x3f);
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_024/nonmatchings/ov_SC06_024_jr_8017BEBC", func_8018CBDC);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_024/nonmatchings/ov_SC06_024_jr_8017BEBC", func_8018D020);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_024/nonmatchings/ov_SC06_024_jr_8017BEBC", func_8018D230);
|
||||
extern s32 rand(void);
|
||||
extern s32 func_80143C74();
|
||||
extern s32 func_80047948(s32 a0);
|
||||
extern s32 func_8004787C(s32 a0);
|
||||
|
||||
void func_8018D020(s32 a0) {
|
||||
|
||||
extern void (*D_801D4D0C[])(s32);
|
||||
s32 iVar3;
|
||||
s32 iVar4;
|
||||
s32 r;
|
||||
|
||||
{
|
||||
s16 t = *(s16 *)(a0 + 0x102);
|
||||
if (t != 0) {
|
||||
t--;
|
||||
*(s16 *)(a0 + 0x102) = t;
|
||||
if (t == 0) {
|
||||
*(u16 *)(a0 + 0x5C) &= 0xBFFF;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
D_801D4D0C[*(u16 *)(a0 + 2)](a0);
|
||||
|
||||
if (*(u16 *)(a0 + 0) != 0) {
|
||||
if (*(s16 *)(a0 + 0xFC) == 0) {
|
||||
*(s32 *)(a0 + 4) = *(s32 *)(*(s32 *)(a0 + 0x64) + 4);
|
||||
*(s32 *)(a0 + 8) = *(s32 *)(*(s32 *)(a0 + 0x64) + 8);
|
||||
*(s32 *)(a0 + 0xC) = *(s32 *)(*(s32 *)(a0 + 0x64) + 0xC);
|
||||
*(s16 *)(*(s32 *)(a0 + 0x20) + 0x10) =
|
||||
*(s16 *)(*(s32 *)(*(s32 *)(a0 + 0x64) + 0x20) + 0x10);
|
||||
*(s16 *)(*(s32 *)(a0 + 0x20) + 0x12) =
|
||||
*(s16 *)(*(s32 *)(*(s32 *)(a0 + 0x64) + 0x20) + 0x12);
|
||||
*(s16 *)(*(s32 *)(a0 + 0x20) + 0x14) =
|
||||
*(s16 *)(*(s32 *)(*(s32 *)(a0 + 0x64) + 0x20) + 0x14);
|
||||
}
|
||||
if (*(s16 *)(a0 + 0x76) < 5 && (rand() & 3) == 0 &&
|
||||
(iVar3 = func_80143C74(a0, 0)) != 0) {
|
||||
*(s32 *)(iVar3 + 0x10) = ((rand() & 0x7FF) - 0x400) << 8;
|
||||
*(s32 *)(iVar3 + 0x14) = 0xFFF00000;
|
||||
*(s32 *)(iVar3 + 0x18) = ((rand() & 0x7FF) - 0x400) << 8;
|
||||
iVar4 = func_80047948((s32) * (s16 *)(*(s32 *)(a0 + 0x20) + 0x12));
|
||||
*(s32 *)(iVar3 + 4) = *(s32 *)(iVar3 + 4) - iVar4 * 0x400;
|
||||
iVar4 = func_8004787C((s32) * (s16 *)(*(s32 *)(a0 + 0x20) + 0x12));
|
||||
*(s32 *)(iVar3 + 0xC) = *(s32 *)(iVar3 + 0xC) + iVar4 * 0x400;
|
||||
r = rand();
|
||||
{
|
||||
s32 m6 = *(u16 *)(iVar3 + 6) - 0x20;
|
||||
*(u16 *)(iVar3 + 6) = m6 + (r & 0x3F);
|
||||
}
|
||||
*(u16 *)(iVar3 + 0xA) = *(u16 *)(iVar3 + 0xA) - 0x40;
|
||||
r = rand();
|
||||
{
|
||||
s32 mE = *(u16 *)(iVar3 + 0xE) - 0x20;
|
||||
*(u16 *)(iVar3 + 0xE) = mE + (r & 0x3F);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
// @class: schedule
|
||||
// @stuck: none — MATCH. Two levers: (1) split rand()-result into its own var (shared iVar1 forced an extra move a0,v0); (2) reorder decrement before sp[0] to group the two lhu loads as target's scheduler does; (3) materialize &D_80126B96 via a local u16* to CSE the address (lui+addiu once) instead of %hi/%lo split-per-access.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
extern void func_80128EA8();
|
||||
extern void func_8012931C();
|
||||
extern int func_80128ED8();
|
||||
extern u8 *func_8012913C();
|
||||
extern void func_801292C8();
|
||||
extern int func_8012D664();
|
||||
|
||||
extern u16 D_801270C0;
|
||||
|
||||
void func_8018D230(s32 arg0) {
|
||||
|
||||
extern u8 D_801D4AF0;
|
||||
extern u8 D_801D4AFC;
|
||||
extern u16 D_80126B96;
|
||||
s32 iVar1;
|
||||
s32 rv;
|
||||
u8 *p;
|
||||
u16 sp[3];
|
||||
|
||||
if (*(u16 *)(arg0 + 2) == 0) {
|
||||
*(u8 **)(*(s32 *)(arg0 + 0x20) + 0x20) = &D_801D4AF0;
|
||||
*(u32 *)(*(s32 *)(arg0 + 0x20) + 4) |= 0x50000000;
|
||||
*(u8 *)(*(s32 *)(arg0 + 0x20) + 0x27) = 0x59;
|
||||
func_80128EA8(*(s32 *)(arg0 + 0x20), arg0 + 0x24, (s32)&D_801D4AFC);
|
||||
rv = rand();
|
||||
*(s32 *)(arg0 + 0x1c) = 0x10;
|
||||
*(s32 *)(arg0 + 0x2c) = 0x200;
|
||||
*(s16 *)(arg0 + 0x28) = rv % 15;
|
||||
*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) = 0x1200;
|
||||
*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x1a) = 0x1200;
|
||||
*(u16 *)(arg0 + 2) = *(u16 *)(arg0 + 2) + 1;
|
||||
} else if (*(s16 *)&D_801270C0 == 1) {
|
||||
func_8012931C(arg0);
|
||||
func_80128ED8(*(s32 *)(arg0 + 0x20), arg0 + 0x24);
|
||||
*(s32 *)(arg0 + 0x1c) -= 1;
|
||||
if ((rand() & 7) == 0 && (p = func_8012913C(0x22)) != 0) {
|
||||
*(u16 *)(p + 6) = *(u16 *)(arg0 + 6);
|
||||
*(u16 *)(p + 0xa) = *(u16 *)(arg0 + 0xa);
|
||||
*(u16 *)(p + 0xe) = *(u16 *)(arg0 + 0xe);
|
||||
*(s32 *)(p + 0x10) = *(s32 *)(arg0 + 0x10) >> 3;
|
||||
*(s32 *)(p + 0x14) = *(s32 *)(arg0 + 0x14) >> 3;
|
||||
*(s32 *)(p + 0x18) = *(s32 *)(arg0 + 0x18) >> 3;
|
||||
*(s16 *)(p + 0x34) = *(u16 *)(*(s32 *)(arg0 + 0x20) + 0x18) + 1;
|
||||
*(u16 *)(*(s32 *)(p + 0x20) + 0x2c) = 0xc008;
|
||||
}
|
||||
if (*(s32 *)(arg0 + 0x1c) == 0) {
|
||||
func_801292C8(arg0);
|
||||
} else {
|
||||
*(s32 *)(arg0 + 0x14) = 0xffff0000;
|
||||
iVar1 = *(s32 *)(arg0 + 0x2c) + 0x80;
|
||||
*(s32 *)(arg0 + 0x2c) = iVar1;
|
||||
*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) =
|
||||
*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) + (s16)iVar1;
|
||||
*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x1a) =
|
||||
*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x1a) + (s16)*(s32 *)(arg0 + 0x2c);
|
||||
*(s16 *)(arg0 + 0xa) = *(s16 *)(arg0 + 0xa) - 0x20;
|
||||
sp[0] = *(u16 *)(arg0 + 6);
|
||||
sp[1] = *(u16 *)(arg0 + 0xa);
|
||||
sp[2] = *(u16 *)(arg0 + 0xe);
|
||||
if (func_8012D664(sp, 0x10, 0xb4) == 1) {
|
||||
u16 *q = &D_80126B96;
|
||||
*q |= 0x4200;
|
||||
}
|
||||
*(s16 *)(arg0 + 0xa) = *(s16 *)(arg0 + 0xa) + 0x20;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_024/nonmatchings/ov_SC06_024_jr_8017BEBC", func_8018D4B4);
|
||||
|
||||
|
||||
@@ -3944,7 +3944,42 @@ INCLUDE_ASM("asm/ov_SC06_025/nonmatchings/ov_SC06_025_jr_8017BEBC", func_80183D2
|
||||
void func_80183D6C(void) {
|
||||
}
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_025/nonmatchings/ov_SC06_025_jr_8017BEBC", func_80183D74);
|
||||
|
||||
|
||||
|
||||
extern void func_80015978(s32 a0, s32 *a1);
|
||||
extern void func_80183ED8();
|
||||
|
||||
void func_80183D74(s32 param_1) {
|
||||
|
||||
extern u32 *D_801ADA48[];
|
||||
extern Blk8 D_801ADA64[];
|
||||
s32 buf[2];
|
||||
Blk8 A;
|
||||
Blk8 B;
|
||||
Blk8 C;
|
||||
Blk8 D;
|
||||
u32 *basep;
|
||||
s32 i;
|
||||
s32 j;
|
||||
|
||||
basep = D_801ADA48[*(s32 *)(param_1 + 0x30)];
|
||||
*(s16 *)(param_1 + 0x10) = *(s32 *)(param_1 + 0x2c);
|
||||
func_80015978(param_1 + 4, buf);
|
||||
for (j = 0; j < 4; j++) {
|
||||
*(s16 *)&A = 0;
|
||||
*((s16 *)&A + 1) = 0;
|
||||
*((s16 *)&A + 2) = 0;
|
||||
B = A;
|
||||
C = A;
|
||||
for (i = 0; i < 4; i++) {
|
||||
D = D_801ADA64[i];
|
||||
*(s16 *)(param_1 + 0x12) = i + j;
|
||||
func_80183ED8(param_1, buf, &A, &B, &C, &D, param_1 + 0x10, basep + i);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_025/nonmatchings/ov_SC06_025_jr_8017BEBC", func_80183ED8);
|
||||
|
||||
|
||||
@@ -4377,7 +4377,42 @@ INCLUDE_ASM("asm/ov_SC06_029/nonmatchings/ov_SC06_029_jr_8017AE2C", func_8018B8A
|
||||
void func_8018B8F0(void) {
|
||||
}
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_029/nonmatchings/ov_SC06_029_jr_8017AE2C", func_8018B8F8);
|
||||
|
||||
|
||||
|
||||
extern void func_80015978(s32 a0, s32 *a1);
|
||||
extern void func_8018BA5C();
|
||||
|
||||
void func_8018B8F8(s32 param_1) {
|
||||
|
||||
extern u32 *D_801D72F8[];
|
||||
extern Blk8 D_801D7314[];
|
||||
s32 buf[2];
|
||||
Blk8 A;
|
||||
Blk8 B;
|
||||
Blk8 C;
|
||||
Blk8 D;
|
||||
u32 *basep;
|
||||
s32 i;
|
||||
s32 j;
|
||||
|
||||
basep = D_801D72F8[*(s32 *)(param_1 + 0x30)];
|
||||
*(s16 *)(param_1 + 0x10) = *(s32 *)(param_1 + 0x2c);
|
||||
func_80015978(param_1 + 4, buf);
|
||||
for (j = 0; j < 4; j++) {
|
||||
*(s16 *)&A = 0;
|
||||
*((s16 *)&A + 1) = 0;
|
||||
*((s16 *)&A + 2) = 0;
|
||||
B = A;
|
||||
C = A;
|
||||
for (i = 0; i < 4; i++) {
|
||||
D = D_801D7314[i];
|
||||
*(s16 *)(param_1 + 0x12) = i + j;
|
||||
func_8018BA5C(param_1, buf, &A, &B, &C, &D, param_1 + 0x10, basep + i);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_029/nonmatchings/ov_SC06_029_jr_8017AE2C", func_8018BA5C);
|
||||
|
||||
|
||||
@@ -3550,7 +3550,42 @@ INCLUDE_ASM("asm/ov_SC06_032/nonmatchings/ov_SC06_032_jr_8017C24C", func_8017E27
|
||||
void func_8017E2BC(void) {
|
||||
}
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_032/nonmatchings/ov_SC06_032_jr_8017C24C", func_8017E2C4);
|
||||
|
||||
|
||||
|
||||
extern void func_80015978(s32 a0, s32 *a1);
|
||||
extern void func_8017E428();
|
||||
|
||||
void func_8017E2C4(s32 param_1) {
|
||||
|
||||
extern u32 *D_80196E4C[];
|
||||
extern Blk8 D_80196E68[];
|
||||
s32 buf[2];
|
||||
Blk8 A;
|
||||
Blk8 B;
|
||||
Blk8 C;
|
||||
Blk8 D;
|
||||
u32 *basep;
|
||||
s32 i;
|
||||
s32 j;
|
||||
|
||||
basep = D_80196E4C[*(s32 *)(param_1 + 0x30)];
|
||||
*(s16 *)(param_1 + 0x10) = *(s32 *)(param_1 + 0x2c);
|
||||
func_80015978(param_1 + 4, buf);
|
||||
for (j = 0; j < 4; j++) {
|
||||
*(s16 *)&A = 0;
|
||||
*((s16 *)&A + 1) = 0;
|
||||
*((s16 *)&A + 2) = 0;
|
||||
B = A;
|
||||
C = A;
|
||||
for (i = 0; i < 4; i++) {
|
||||
D = D_80196E68[i];
|
||||
*(s16 *)(param_1 + 0x12) = i + j;
|
||||
func_8017E428(param_1, buf, &A, &B, &C, &D, param_1 + 0x10, basep + i);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_032/nonmatchings/ov_SC06_032_jr_8017C24C", func_8017E428);
|
||||
|
||||
@@ -4149,13 +4184,213 @@ INCLUDE_ASM("asm/ov_SC06_032/nonmatchings/ov_SC06_032_jr_8017C24C", func_80189D4
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_032/nonmatchings/ov_SC06_032_jr_8017C24C", func_80189F3C);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_032/nonmatchings/ov_SC06_032_jr_8017C24C", func_8018A384);
|
||||
|
||||
// @class: struct
|
||||
// @stuck: none — MATCH
|
||||
|
||||
extern int rand(void);
|
||||
extern int func_80143C74(short *, int);
|
||||
extern int func_80047948(int);
|
||||
extern int func_8004787C(int);
|
||||
|
||||
void func_8018A384(short *param_1)
|
||||
{
|
||||
|
||||
extern void (*D_801C2D84[])(short *);
|
||||
int iVar3;
|
||||
unsigned int uVar2;
|
||||
short v;
|
||||
|
||||
v = param_1[0x81];
|
||||
if (v != 0) {
|
||||
v = v - 1;
|
||||
param_1[0x81] = v;
|
||||
if (v == 0) {
|
||||
*(unsigned short *)(param_1 + 0x2e) &= 0xbfff;
|
||||
}
|
||||
}
|
||||
D_801C2D84[*(unsigned short *)(param_1 + 1)](param_1);
|
||||
if (*(unsigned short *)param_1 != 0) {
|
||||
if (param_1[0x7e] == 0) {
|
||||
*(int *)(param_1 + 2) = *(int *)(*(int *)(param_1 + 0x32) + 4);
|
||||
*(int *)(param_1 + 4) = *(int *)(*(int *)(param_1 + 0x32) + 8);
|
||||
*(int *)(param_1 + 6) = *(int *)(*(int *)(param_1 + 0x32) + 0xc);
|
||||
*(unsigned short *)(*(int *)(param_1 + 0x10) + 0x10) =
|
||||
*(unsigned short *)(*(int *)(*(int *)(param_1 + 0x32) + 0x20) + 0x10);
|
||||
*(unsigned short *)(*(int *)(param_1 + 0x10) + 0x12) =
|
||||
*(unsigned short *)(*(int *)(*(int *)(param_1 + 0x32) + 0x20) + 0x12);
|
||||
*(unsigned short *)(*(int *)(param_1 + 0x10) + 0x14) =
|
||||
*(unsigned short *)(*(int *)(*(int *)(param_1 + 0x32) + 0x20) + 0x14);
|
||||
}
|
||||
if ((param_1[0x3b] < 5) && ((rand() & 3) == 0) &&
|
||||
((iVar3 = func_80143C74(param_1, 0)) != 0)) {
|
||||
uVar2 = rand();
|
||||
*(int *)(iVar3 + 0x10) = ((uVar2 & 0x7ff) - 0x400) * 0x100;
|
||||
*(unsigned int *)(iVar3 + 0x14) = 0xfff00000;
|
||||
uVar2 = rand();
|
||||
*(int *)(iVar3 + 0x18) = ((uVar2 & 0x7ff) - 0x400) * 0x100;
|
||||
*(int *)(iVar3 + 4) +=
|
||||
func_80047948((int)*(short *)(*(int *)(param_1 + 0x10) + 0x12)) * 0x400;
|
||||
*(int *)(iVar3 + 0xc) -=
|
||||
func_8004787C((int)*(short *)(*(int *)(param_1 + 0x10) + 0x12)) * 0x400;
|
||||
uVar2 = rand();
|
||||
*(short *)(iVar3 + 6) -= 0x20;
|
||||
*(short *)(iVar3 + 6) += (uVar2 & 0x3f);
|
||||
*(short *)(iVar3 + 0xa) -= 0x40;
|
||||
uVar2 = rand();
|
||||
*(short *)(iVar3 + 0xe) -= 0x20;
|
||||
*(short *)(iVar3 + 0xe) += (uVar2 & 0x3f);
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_032/nonmatchings/ov_SC06_032_jr_8017C24C", func_8018A594);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_032/nonmatchings/ov_SC06_032_jr_8017C24C", func_8018A9D8);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_032/nonmatchings/ov_SC06_032_jr_8017C24C", func_8018ABE8);
|
||||
extern s32 rand(void);
|
||||
extern s32 func_80143C74();
|
||||
extern s32 func_80047948(s32 a0);
|
||||
extern s32 func_8004787C(s32 a0);
|
||||
|
||||
void func_8018A9D8(s32 a0) {
|
||||
|
||||
extern void (*D_801C2DFC[])(s32);
|
||||
s32 iVar3;
|
||||
s32 iVar4;
|
||||
s32 r;
|
||||
|
||||
{
|
||||
s16 t = *(s16 *)(a0 + 0x102);
|
||||
if (t != 0) {
|
||||
t--;
|
||||
*(s16 *)(a0 + 0x102) = t;
|
||||
if (t == 0) {
|
||||
*(u16 *)(a0 + 0x5C) &= 0xBFFF;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
D_801C2DFC[*(u16 *)(a0 + 2)](a0);
|
||||
|
||||
if (*(u16 *)(a0 + 0) != 0) {
|
||||
if (*(s16 *)(a0 + 0xFC) == 0) {
|
||||
*(s32 *)(a0 + 4) = *(s32 *)(*(s32 *)(a0 + 0x64) + 4);
|
||||
*(s32 *)(a0 + 8) = *(s32 *)(*(s32 *)(a0 + 0x64) + 8);
|
||||
*(s32 *)(a0 + 0xC) = *(s32 *)(*(s32 *)(a0 + 0x64) + 0xC);
|
||||
*(s16 *)(*(s32 *)(a0 + 0x20) + 0x10) =
|
||||
*(s16 *)(*(s32 *)(*(s32 *)(a0 + 0x64) + 0x20) + 0x10);
|
||||
*(s16 *)(*(s32 *)(a0 + 0x20) + 0x12) =
|
||||
*(s16 *)(*(s32 *)(*(s32 *)(a0 + 0x64) + 0x20) + 0x12);
|
||||
*(s16 *)(*(s32 *)(a0 + 0x20) + 0x14) =
|
||||
*(s16 *)(*(s32 *)(*(s32 *)(a0 + 0x64) + 0x20) + 0x14);
|
||||
}
|
||||
if (*(s16 *)(a0 + 0x76) < 5 && (rand() & 3) == 0 &&
|
||||
(iVar3 = func_80143C74(a0, 0)) != 0) {
|
||||
*(s32 *)(iVar3 + 0x10) = ((rand() & 0x7FF) - 0x400) << 8;
|
||||
*(s32 *)(iVar3 + 0x14) = 0xFFF00000;
|
||||
*(s32 *)(iVar3 + 0x18) = ((rand() & 0x7FF) - 0x400) << 8;
|
||||
iVar4 = func_80047948((s32) * (s16 *)(*(s32 *)(a0 + 0x20) + 0x12));
|
||||
*(s32 *)(iVar3 + 4) = *(s32 *)(iVar3 + 4) - iVar4 * 0x400;
|
||||
iVar4 = func_8004787C((s32) * (s16 *)(*(s32 *)(a0 + 0x20) + 0x12));
|
||||
*(s32 *)(iVar3 + 0xC) = *(s32 *)(iVar3 + 0xC) + iVar4 * 0x400;
|
||||
r = rand();
|
||||
{
|
||||
s32 m6 = *(u16 *)(iVar3 + 6) - 0x20;
|
||||
*(u16 *)(iVar3 + 6) = m6 + (r & 0x3F);
|
||||
}
|
||||
*(u16 *)(iVar3 + 0xA) = *(u16 *)(iVar3 + 0xA) - 0x40;
|
||||
r = rand();
|
||||
{
|
||||
s32 mE = *(u16 *)(iVar3 + 0xE) - 0x20;
|
||||
*(u16 *)(iVar3 + 0xE) = mE + (r & 0x3F);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
// @class: schedule
|
||||
// @stuck: none — MATCH. Two levers: (1) split rand()-result into its own var (shared iVar1 forced an extra move a0,v0); (2) reorder decrement before sp[0] to group the two lhu loads as target's scheduler does; (3) materialize &D_80126B96 via a local u16* to CSE the address (lui+addiu once) instead of %hi/%lo split-per-access.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
extern void func_80128EA8();
|
||||
extern void func_8012931C();
|
||||
extern int func_80128ED8();
|
||||
extern u8 *func_8012913C();
|
||||
extern void func_801292C8();
|
||||
extern int func_8012D664();
|
||||
|
||||
extern u16 D_801270C0;
|
||||
|
||||
void func_8018ABE8(s32 arg0) {
|
||||
|
||||
extern u8 D_801C2BE0;
|
||||
extern u8 D_801C2BEC;
|
||||
extern u16 D_80126B96;
|
||||
s32 iVar1;
|
||||
s32 rv;
|
||||
u8 *p;
|
||||
u16 sp[3];
|
||||
|
||||
if (*(u16 *)(arg0 + 2) == 0) {
|
||||
*(u8 **)(*(s32 *)(arg0 + 0x20) + 0x20) = &D_801C2BE0;
|
||||
*(u32 *)(*(s32 *)(arg0 + 0x20) + 4) |= 0x50000000;
|
||||
*(u8 *)(*(s32 *)(arg0 + 0x20) + 0x27) = 0x59;
|
||||
func_80128EA8(*(s32 *)(arg0 + 0x20), arg0 + 0x24, (s32)&D_801C2BEC);
|
||||
rv = rand();
|
||||
*(s32 *)(arg0 + 0x1c) = 0x10;
|
||||
*(s32 *)(arg0 + 0x2c) = 0x200;
|
||||
*(s16 *)(arg0 + 0x28) = rv % 15;
|
||||
*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) = 0x1200;
|
||||
*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x1a) = 0x1200;
|
||||
*(u16 *)(arg0 + 2) = *(u16 *)(arg0 + 2) + 1;
|
||||
} else if (*(s16 *)&D_801270C0 == 1) {
|
||||
func_8012931C(arg0);
|
||||
func_80128ED8(*(s32 *)(arg0 + 0x20), arg0 + 0x24);
|
||||
*(s32 *)(arg0 + 0x1c) -= 1;
|
||||
if ((rand() & 7) == 0 && (p = func_8012913C(0x22)) != 0) {
|
||||
*(u16 *)(p + 6) = *(u16 *)(arg0 + 6);
|
||||
*(u16 *)(p + 0xa) = *(u16 *)(arg0 + 0xa);
|
||||
*(u16 *)(p + 0xe) = *(u16 *)(arg0 + 0xe);
|
||||
*(s32 *)(p + 0x10) = *(s32 *)(arg0 + 0x10) >> 3;
|
||||
*(s32 *)(p + 0x14) = *(s32 *)(arg0 + 0x14) >> 3;
|
||||
*(s32 *)(p + 0x18) = *(s32 *)(arg0 + 0x18) >> 3;
|
||||
*(s16 *)(p + 0x34) = *(u16 *)(*(s32 *)(arg0 + 0x20) + 0x18) + 1;
|
||||
*(u16 *)(*(s32 *)(p + 0x20) + 0x2c) = 0xc008;
|
||||
}
|
||||
if (*(s32 *)(arg0 + 0x1c) == 0) {
|
||||
func_801292C8(arg0);
|
||||
} else {
|
||||
*(s32 *)(arg0 + 0x14) = 0xffff0000;
|
||||
iVar1 = *(s32 *)(arg0 + 0x2c) + 0x80;
|
||||
*(s32 *)(arg0 + 0x2c) = iVar1;
|
||||
*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) =
|
||||
*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) + (s16)iVar1;
|
||||
*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x1a) =
|
||||
*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x1a) + (s16)*(s32 *)(arg0 + 0x2c);
|
||||
*(s16 *)(arg0 + 0xa) = *(s16 *)(arg0 + 0xa) - 0x20;
|
||||
sp[0] = *(u16 *)(arg0 + 6);
|
||||
sp[1] = *(u16 *)(arg0 + 0xa);
|
||||
sp[2] = *(u16 *)(arg0 + 0xe);
|
||||
if (func_8012D664(sp, 0x10, 0xb4) == 1) {
|
||||
u16 *q = &D_80126B96;
|
||||
*q |= 0x4200;
|
||||
}
|
||||
*(s16 *)(arg0 + 0xa) = *(s16 *)(arg0 + 0xa) + 0x20;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_032/nonmatchings/ov_SC06_032_jr_8017C24C", func_8018AE6C);
|
||||
|
||||
|
||||
@@ -3611,7 +3611,42 @@ INCLUDE_ASM("asm/ov_SC06_033/nonmatchings/ov_SC06_033_jr_8017C24C", func_8017EDF
|
||||
void func_8017EE44(void) {
|
||||
}
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_033/nonmatchings/ov_SC06_033_jr_8017C24C", func_8017EE4C);
|
||||
|
||||
|
||||
|
||||
extern void func_80015978(s32 a0, s32 *a1);
|
||||
extern void func_8017EFB0();
|
||||
|
||||
void func_8017EE4C(s32 param_1) {
|
||||
|
||||
extern u32 *D_80195400[];
|
||||
extern Blk8 D_8019541C[];
|
||||
s32 buf[2];
|
||||
Blk8 A;
|
||||
Blk8 B;
|
||||
Blk8 C;
|
||||
Blk8 D;
|
||||
u32 *basep;
|
||||
s32 i;
|
||||
s32 j;
|
||||
|
||||
basep = D_80195400[*(s32 *)(param_1 + 0x30)];
|
||||
*(s16 *)(param_1 + 0x10) = *(s32 *)(param_1 + 0x2c);
|
||||
func_80015978(param_1 + 4, buf);
|
||||
for (j = 0; j < 4; j++) {
|
||||
*(s16 *)&A = 0;
|
||||
*((s16 *)&A + 1) = 0;
|
||||
*((s16 *)&A + 2) = 0;
|
||||
B = A;
|
||||
C = A;
|
||||
for (i = 0; i < 4; i++) {
|
||||
D = D_8019541C[i];
|
||||
*(s16 *)(param_1 + 0x12) = i + j;
|
||||
func_8017EFB0(param_1, buf, &A, &B, &C, &D, param_1 + 0x10, basep + i);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_033/nonmatchings/ov_SC06_033_jr_8017C24C", func_8017EFB0);
|
||||
|
||||
@@ -3638,13 +3673,213 @@ INCLUDE_ASM("asm/ov_SC06_033/nonmatchings/ov_SC06_033_jr_8017C24C", func_80180A8
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_033/nonmatchings/ov_SC06_033_jr_8017C24C", func_80180C84);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_033/nonmatchings/ov_SC06_033_jr_8017C24C", func_801810CC);
|
||||
|
||||
// @class: struct
|
||||
// @stuck: none — MATCH
|
||||
|
||||
extern int rand(void);
|
||||
extern int func_80143C74(short *, int);
|
||||
extern int func_80047948(int);
|
||||
extern int func_8004787C(int);
|
||||
|
||||
void func_801810CC(short *param_1)
|
||||
{
|
||||
|
||||
extern void (*D_801A7D8C[])(short *);
|
||||
int iVar3;
|
||||
unsigned int uVar2;
|
||||
short v;
|
||||
|
||||
v = param_1[0x81];
|
||||
if (v != 0) {
|
||||
v = v - 1;
|
||||
param_1[0x81] = v;
|
||||
if (v == 0) {
|
||||
*(unsigned short *)(param_1 + 0x2e) &= 0xbfff;
|
||||
}
|
||||
}
|
||||
D_801A7D8C[*(unsigned short *)(param_1 + 1)](param_1);
|
||||
if (*(unsigned short *)param_1 != 0) {
|
||||
if (param_1[0x7e] == 0) {
|
||||
*(int *)(param_1 + 2) = *(int *)(*(int *)(param_1 + 0x32) + 4);
|
||||
*(int *)(param_1 + 4) = *(int *)(*(int *)(param_1 + 0x32) + 8);
|
||||
*(int *)(param_1 + 6) = *(int *)(*(int *)(param_1 + 0x32) + 0xc);
|
||||
*(unsigned short *)(*(int *)(param_1 + 0x10) + 0x10) =
|
||||
*(unsigned short *)(*(int *)(*(int *)(param_1 + 0x32) + 0x20) + 0x10);
|
||||
*(unsigned short *)(*(int *)(param_1 + 0x10) + 0x12) =
|
||||
*(unsigned short *)(*(int *)(*(int *)(param_1 + 0x32) + 0x20) + 0x12);
|
||||
*(unsigned short *)(*(int *)(param_1 + 0x10) + 0x14) =
|
||||
*(unsigned short *)(*(int *)(*(int *)(param_1 + 0x32) + 0x20) + 0x14);
|
||||
}
|
||||
if ((param_1[0x3b] < 5) && ((rand() & 3) == 0) &&
|
||||
((iVar3 = func_80143C74(param_1, 0)) != 0)) {
|
||||
uVar2 = rand();
|
||||
*(int *)(iVar3 + 0x10) = ((uVar2 & 0x7ff) - 0x400) * 0x100;
|
||||
*(unsigned int *)(iVar3 + 0x14) = 0xfff00000;
|
||||
uVar2 = rand();
|
||||
*(int *)(iVar3 + 0x18) = ((uVar2 & 0x7ff) - 0x400) * 0x100;
|
||||
*(int *)(iVar3 + 4) +=
|
||||
func_80047948((int)*(short *)(*(int *)(param_1 + 0x10) + 0x12)) * 0x400;
|
||||
*(int *)(iVar3 + 0xc) -=
|
||||
func_8004787C((int)*(short *)(*(int *)(param_1 + 0x10) + 0x12)) * 0x400;
|
||||
uVar2 = rand();
|
||||
*(short *)(iVar3 + 6) -= 0x20;
|
||||
*(short *)(iVar3 + 6) += (uVar2 & 0x3f);
|
||||
*(short *)(iVar3 + 0xa) -= 0x40;
|
||||
uVar2 = rand();
|
||||
*(short *)(iVar3 + 0xe) -= 0x20;
|
||||
*(short *)(iVar3 + 0xe) += (uVar2 & 0x3f);
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_033/nonmatchings/ov_SC06_033_jr_8017C24C", func_801812DC);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_033/nonmatchings/ov_SC06_033_jr_8017C24C", func_80181720);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_033/nonmatchings/ov_SC06_033_jr_8017C24C", func_80181930);
|
||||
extern s32 rand(void);
|
||||
extern s32 func_80143C74();
|
||||
extern s32 func_80047948(s32 a0);
|
||||
extern s32 func_8004787C(s32 a0);
|
||||
|
||||
void func_80181720(s32 a0) {
|
||||
|
||||
extern void (*D_801A7E04[])(s32);
|
||||
s32 iVar3;
|
||||
s32 iVar4;
|
||||
s32 r;
|
||||
|
||||
{
|
||||
s16 t = *(s16 *)(a0 + 0x102);
|
||||
if (t != 0) {
|
||||
t--;
|
||||
*(s16 *)(a0 + 0x102) = t;
|
||||
if (t == 0) {
|
||||
*(u16 *)(a0 + 0x5C) &= 0xBFFF;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
D_801A7E04[*(u16 *)(a0 + 2)](a0);
|
||||
|
||||
if (*(u16 *)(a0 + 0) != 0) {
|
||||
if (*(s16 *)(a0 + 0xFC) == 0) {
|
||||
*(s32 *)(a0 + 4) = *(s32 *)(*(s32 *)(a0 + 0x64) + 4);
|
||||
*(s32 *)(a0 + 8) = *(s32 *)(*(s32 *)(a0 + 0x64) + 8);
|
||||
*(s32 *)(a0 + 0xC) = *(s32 *)(*(s32 *)(a0 + 0x64) + 0xC);
|
||||
*(s16 *)(*(s32 *)(a0 + 0x20) + 0x10) =
|
||||
*(s16 *)(*(s32 *)(*(s32 *)(a0 + 0x64) + 0x20) + 0x10);
|
||||
*(s16 *)(*(s32 *)(a0 + 0x20) + 0x12) =
|
||||
*(s16 *)(*(s32 *)(*(s32 *)(a0 + 0x64) + 0x20) + 0x12);
|
||||
*(s16 *)(*(s32 *)(a0 + 0x20) + 0x14) =
|
||||
*(s16 *)(*(s32 *)(*(s32 *)(a0 + 0x64) + 0x20) + 0x14);
|
||||
}
|
||||
if (*(s16 *)(a0 + 0x76) < 5 && (rand() & 3) == 0 &&
|
||||
(iVar3 = func_80143C74(a0, 0)) != 0) {
|
||||
*(s32 *)(iVar3 + 0x10) = ((rand() & 0x7FF) - 0x400) << 8;
|
||||
*(s32 *)(iVar3 + 0x14) = 0xFFF00000;
|
||||
*(s32 *)(iVar3 + 0x18) = ((rand() & 0x7FF) - 0x400) << 8;
|
||||
iVar4 = func_80047948((s32) * (s16 *)(*(s32 *)(a0 + 0x20) + 0x12));
|
||||
*(s32 *)(iVar3 + 4) = *(s32 *)(iVar3 + 4) - iVar4 * 0x400;
|
||||
iVar4 = func_8004787C((s32) * (s16 *)(*(s32 *)(a0 + 0x20) + 0x12));
|
||||
*(s32 *)(iVar3 + 0xC) = *(s32 *)(iVar3 + 0xC) + iVar4 * 0x400;
|
||||
r = rand();
|
||||
{
|
||||
s32 m6 = *(u16 *)(iVar3 + 6) - 0x20;
|
||||
*(u16 *)(iVar3 + 6) = m6 + (r & 0x3F);
|
||||
}
|
||||
*(u16 *)(iVar3 + 0xA) = *(u16 *)(iVar3 + 0xA) - 0x40;
|
||||
r = rand();
|
||||
{
|
||||
s32 mE = *(u16 *)(iVar3 + 0xE) - 0x20;
|
||||
*(u16 *)(iVar3 + 0xE) = mE + (r & 0x3F);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
// @class: schedule
|
||||
// @stuck: none — MATCH. Two levers: (1) split rand()-result into its own var (shared iVar1 forced an extra move a0,v0); (2) reorder decrement before sp[0] to group the two lhu loads as target's scheduler does; (3) materialize &D_80126B96 via a local u16* to CSE the address (lui+addiu once) instead of %hi/%lo split-per-access.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
extern void func_80128EA8();
|
||||
extern void func_8012931C();
|
||||
extern int func_80128ED8();
|
||||
extern u8 *func_8012913C();
|
||||
extern void func_801292C8();
|
||||
extern int func_8012D664();
|
||||
|
||||
extern u16 D_801270C0;
|
||||
|
||||
void func_80181930(s32 arg0) {
|
||||
|
||||
extern u8 D_801A7BE8;
|
||||
extern u8 D_801A7BF4;
|
||||
extern u16 D_80126B96;
|
||||
s32 iVar1;
|
||||
s32 rv;
|
||||
u8 *p;
|
||||
u16 sp[3];
|
||||
|
||||
if (*(u16 *)(arg0 + 2) == 0) {
|
||||
*(u8 **)(*(s32 *)(arg0 + 0x20) + 0x20) = &D_801A7BE8;
|
||||
*(u32 *)(*(s32 *)(arg0 + 0x20) + 4) |= 0x50000000;
|
||||
*(u8 *)(*(s32 *)(arg0 + 0x20) + 0x27) = 0x59;
|
||||
func_80128EA8(*(s32 *)(arg0 + 0x20), arg0 + 0x24, (s32)&D_801A7BF4);
|
||||
rv = rand();
|
||||
*(s32 *)(arg0 + 0x1c) = 0x10;
|
||||
*(s32 *)(arg0 + 0x2c) = 0x200;
|
||||
*(s16 *)(arg0 + 0x28) = rv % 15;
|
||||
*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) = 0x1200;
|
||||
*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x1a) = 0x1200;
|
||||
*(u16 *)(arg0 + 2) = *(u16 *)(arg0 + 2) + 1;
|
||||
} else if (*(s16 *)&D_801270C0 == 1) {
|
||||
func_8012931C(arg0);
|
||||
func_80128ED8(*(s32 *)(arg0 + 0x20), arg0 + 0x24);
|
||||
*(s32 *)(arg0 + 0x1c) -= 1;
|
||||
if ((rand() & 7) == 0 && (p = func_8012913C(0x22)) != 0) {
|
||||
*(u16 *)(p + 6) = *(u16 *)(arg0 + 6);
|
||||
*(u16 *)(p + 0xa) = *(u16 *)(arg0 + 0xa);
|
||||
*(u16 *)(p + 0xe) = *(u16 *)(arg0 + 0xe);
|
||||
*(s32 *)(p + 0x10) = *(s32 *)(arg0 + 0x10) >> 3;
|
||||
*(s32 *)(p + 0x14) = *(s32 *)(arg0 + 0x14) >> 3;
|
||||
*(s32 *)(p + 0x18) = *(s32 *)(arg0 + 0x18) >> 3;
|
||||
*(s16 *)(p + 0x34) = *(u16 *)(*(s32 *)(arg0 + 0x20) + 0x18) + 1;
|
||||
*(u16 *)(*(s32 *)(p + 0x20) + 0x2c) = 0xc008;
|
||||
}
|
||||
if (*(s32 *)(arg0 + 0x1c) == 0) {
|
||||
func_801292C8(arg0);
|
||||
} else {
|
||||
*(s32 *)(arg0 + 0x14) = 0xffff0000;
|
||||
iVar1 = *(s32 *)(arg0 + 0x2c) + 0x80;
|
||||
*(s32 *)(arg0 + 0x2c) = iVar1;
|
||||
*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) =
|
||||
*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) + (s16)iVar1;
|
||||
*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x1a) =
|
||||
*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x1a) + (s16)*(s32 *)(arg0 + 0x2c);
|
||||
*(s16 *)(arg0 + 0xa) = *(s16 *)(arg0 + 0xa) - 0x20;
|
||||
sp[0] = *(u16 *)(arg0 + 6);
|
||||
sp[1] = *(u16 *)(arg0 + 0xa);
|
||||
sp[2] = *(u16 *)(arg0 + 0xe);
|
||||
if (func_8012D664(sp, 0x10, 0xb4) == 1) {
|
||||
u16 *q = &D_80126B96;
|
||||
*q |= 0x4200;
|
||||
}
|
||||
*(s16 *)(arg0 + 0xa) = *(s16 *)(arg0 + 0xa) + 0x20;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_033/nonmatchings/ov_SC06_033_jr_8017C24C", func_80181BB4);
|
||||
|
||||
|
||||
@@ -323,7 +323,19 @@ def _run_gate_locked(drafts, binary, src, asm, out, good_sha, propagate, source_
|
||||
|
||||
if _unbanked and _arity_snapshot:
|
||||
try:
|
||||
# RESTORE ONLY src/shared/ (the fleet-shared header). The snapshot also captured
|
||||
# src/<binary>/*.c, but _gate1 SPLICES each banked draft into those files AFTER the
|
||||
# snapshot was taken — so restoring them REVERTS the banks that just landed (and the
|
||||
# re-apply below only re-does arity, not the splice). Bug measured 2026-07-22 (Phase-29
|
||||
# non-jtbl wave): a 9-draft run banked 4, and the 5 unbanked triggered this restore,
|
||||
# silently reverting all 4 back to INCLUDE_ASM. The fleet hazard the snapshot exists for
|
||||
# (a fix_arity edit lingering in engine_core.h for an unbanked fn, all 138 overlays) is
|
||||
# entirely in src/shared/; the binary's own TU arity edits are LOCAL + byte-neutral, so
|
||||
# leaving an unbanked fn's `(void)->()` there is harmless. (R33 — narrow the undo to its
|
||||
# real write scope; §61's law that undo scope must not EXCEED write scope, from below.)
|
||||
for _f, _txt in _arity_snapshot.items():
|
||||
if os.sep + "shared" + os.sep not in _f:
|
||||
continue
|
||||
with open(_f, "w") as _fh:
|
||||
_fh.write(_txt)
|
||||
if verified:
|
||||
|
||||
Reference in New Issue
Block a user