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feat(phase-26): h_seq family sweep — 3 member-matches banked via remap_hseq

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Drew T
2026-08-01 09:10:20 -06:00
parent 98775dd1d5
commit 6123d9e200
3 changed files with 141 additions and 3 deletions
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src/ov_SC04_011/ov_SC04_011_jr_8017D494.c
+47 -1
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@@ -3491,7 +3491,53 @@ INCLUDE_ASM("asm/ov_SC04_011/nonmatchings/ov_SC04_011_jr_8017D494", func_8018022
INCLUDE_ASM("asm/ov_SC04_011/nonmatchings/ov_SC04_011_jr_8017D494", func_80180320);
INCLUDE_ASM("asm/ov_SC04_011/nonmatchings/ov_SC04_011_jr_8017D494", func_801803D8);
// @class: schedule
// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh
// zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1].
/* 0x20: m@0, pad@0x12, t@0x14 */
/* 8 bytes */
extern s32 func_80012C6C(s32 a0, s32 a1, s32 a2);
extern s32 func_80012ABC(s32 a0, s32 a1, s32 a2);
extern void func_80049CAC(s32 a0, s32 a1);
extern void func_8012F14C(s32);
void func_801803D8(s32 param_1, s16 *param_2) {
MATRIX m1;
SVECTOR svec_in;
SVECTOR svec_out;
*(s32 *)(param_1 + 0x8) = (s16)func_80012C6C((s32)*(s16 *)(param_1 + 0x8), (s32)*(s16 *)(param_1 + 0xC), 10);
*(s32 *)(param_1 + 0x10) = (s16)func_80012C6C((s32)*(s16 *)(param_1 + 0x10), (s32)*(s16 *)(param_1 + 0x14), 10);
*(s16 *)(param_1 + 0x18) = func_80012ABC((s32)*(s16 *)(param_1 + 0x18), (s32)*(s16 *)(param_1 + 0x20), 10);
*(s16 *)(param_1 + 0x1A) = func_80012ABC((s32)*(s16 *)(param_1 + 0x1A), (s32)*(s16 *)(param_1 + 0x22), 10);
*(s16 *)(param_1 + 0x1C) = func_80012ABC((s32)*(s16 *)(param_1 + 0x1C), (s32)*(s16 *)(param_1 + 0x24), 10);
*(s16 *)(param_1 + 0x28) = func_80012C6C((s32)*(s16 *)(param_1 + 0x28), (s32)*(s16 *)(param_1 + 0x2E), 0x10);
*(s16 *)(param_1 + 0x2A) = func_80012C6C((s32)*(s16 *)(param_1 + 0x2A), (s32)*(s16 *)(param_1 + 0x30), 0x10);
*(s16 *)(param_1 + 0x2C) = func_80012C6C((s32)*(s16 *)(param_1 + 0x2C), (s32)*(s16 *)(param_1 + 0x32), 0x10);
*(s32 *)(param_1 + 0x48) = (s32)*(s16 *)(param_1 + 0x28) + (s32)param_2[0];
*(s32 *)(param_1 + 0x4C) = (s32)*(s16 *)(param_1 + 0x2A) + (s32)param_2[1];
*(s32 *)(param_1 + 0x50) = (s32)*(s16 *)(param_1 + 0x2C) + (s32)param_2[2];
func_80049CAC(param_1 + 0x18, (s32)&m1);
m1.t[0] = *(s16 *)(param_1 + 0x28) + param_2[0];
m1.t[1] = *(s16 *)(param_1 + 0x2A) + param_2[1];
m1.t[2] = *(s16 *)(param_1 + 0x2C) + param_2[2];
svec_in.vx = 0;
svec_in.vy = 0;
svec_in.vz = *(s32 *)(param_1 + 0x10);
((void (*)(s32, s32, s32))func_8012F14C)((s32)&m1, (s32)&svec_in, (s32)&svec_out);
*(s32 *)(param_1 + 0x3C) = (s32)svec_out.vx;
*(s32 *)(param_1 + 0x40) = (s32)svec_out.vy;
*(s32 *)(param_1 + 0x44) = (s32)svec_out.vz;
}
INCLUDE_ASM("asm/ov_SC04_011/nonmatchings/ov_SC04_011_jr_8017D494", func_80180570);
src/ov_SC05_009/ov_SC05_009_jr_8017BEBC.c
+47 -1
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@@ -3326,7 +3326,53 @@ void func_8017D340(s32 param_1, s16 *param_2) {
}
INCLUDE_ASM("asm/ov_SC05_009/nonmatchings/ov_SC05_009_jr_8017BEBC", func_8017D4D8);
// @class: schedule
// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh
// zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1].
/* 0x20: m@0, pad@0x12, t@0x14 */
/* 8 bytes */
extern s32 func_80012C6C(s32 a0, s32 a1, s32 a2);
extern s32 func_80012ABC(s32 a0, s32 a1, s32 a2);
extern void func_80049CAC(s32 a0, s32 a1);
extern void func_8012F14C(s32);
void func_8017D4D8(s32 param_1, s16 *param_2) {
MATRIX m1;
SVECTOR svec_in;
SVECTOR svec_out;
*(s32 *)(param_1 + 0x8) = (s16)func_80012C6C((s32)*(s16 *)(param_1 + 0x8), (s32)*(s16 *)(param_1 + 0xC), 16);
*(s32 *)(param_1 + 0x10) = (s16)func_80012C6C((s32)*(s16 *)(param_1 + 0x10), (s32)*(s16 *)(param_1 + 0x14), 16);
*(s16 *)(param_1 + 0x18) = func_80012ABC((s32)*(s16 *)(param_1 + 0x18), (s32)*(s16 *)(param_1 + 0x20), 16);
*(s16 *)(param_1 + 0x1A) = func_80012ABC((s32)*(s16 *)(param_1 + 0x1A), (s32)*(s16 *)(param_1 + 0x22), 16);
*(s16 *)(param_1 + 0x1C) = func_80012ABC((s32)*(s16 *)(param_1 + 0x1C), (s32)*(s16 *)(param_1 + 0x24), 16);
*(s16 *)(param_1 + 0x28) = func_80012C6C((s32)*(s16 *)(param_1 + 0x28), (s32)*(s16 *)(param_1 + 0x2E), 0x10);
*(s16 *)(param_1 + 0x2A) = func_80012C6C((s32)*(s16 *)(param_1 + 0x2A), (s32)*(s16 *)(param_1 + 0x30), 0x10);
*(s16 *)(param_1 + 0x2C) = func_80012C6C((s32)*(s16 *)(param_1 + 0x2C), (s32)*(s16 *)(param_1 + 0x32), 0x10);
*(s32 *)(param_1 + 0x48) = (s32)*(s16 *)(param_1 + 0x28) + (s32)param_2[0];
*(s32 *)(param_1 + 0x4C) = (s32)*(s16 *)(param_1 + 0x2A) + (s32)param_2[1];
*(s32 *)(param_1 + 0x50) = (s32)*(s16 *)(param_1 + 0x2C) + (s32)param_2[2];
func_80049CAC(param_1 + 0x18, (s32)&m1);
m1.t[0] = *(s16 *)(param_1 + 0x28) + param_2[0];
m1.t[1] = *(s16 *)(param_1 + 0x2A) + param_2[1];
m1.t[2] = *(s16 *)(param_1 + 0x2C) + param_2[2];
svec_in.vx = 0;
svec_in.vy = 0;
svec_in.vz = *(s32 *)(param_1 + 0x10);
((void (*)(s32, s32, s32))func_8012F14C)((s32)&m1, (s32)&svec_in, (s32)&svec_out);
*(s32 *)(param_1 + 0x3C) = (s32)svec_out.vx;
*(s32 *)(param_1 + 0x40) = (s32)svec_out.vy;
*(s32 *)(param_1 + 0x44) = (s32)svec_out.vz;
}
extern void (*D_80182580[])(void);
src/ov_SC07_001/ov_SC07_001_jr_8017BEBC.c
+47 -1
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@@ -3270,7 +3270,53 @@ INCLUDE_ASM("asm/ov_SC07_001/nonmatchings/ov_SC07_001_jr_8017BEBC", func_8017DC7
INCLUDE_ASM("asm/ov_SC07_001/nonmatchings/ov_SC07_001_jr_8017BEBC", func_8017DDD4);
INCLUDE_ASM("asm/ov_SC07_001/nonmatchings/ov_SC07_001_jr_8017BEBC", func_8017DF14);
// @class: schedule
// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh
// zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1].
/* 0x20: m@0, pad@0x12, t@0x14 */
/* 8 bytes */
extern s32 func_80012C6C(s32 a0, s32 a1, s32 a2);
extern s32 func_80012ABC(s32 a0, s32 a1, s32 a2);
extern void func_80049CAC(s32 a0, s32 a1);
extern void func_8012F14C(s32);
void func_8017DF14(s32 param_1, s16 *param_2) {
MATRIX m1;
SVECTOR svec_in;
SVECTOR svec_out;
*(s32 *)(param_1 + 0x8) = (s16)func_80012C6C((s32)*(s16 *)(param_1 + 0x8), (s32)*(s16 *)(param_1 + 0xC), 8);
*(s32 *)(param_1 + 0x10) = (s16)func_80012C6C((s32)*(s16 *)(param_1 + 0x10), (s32)*(s16 *)(param_1 + 0x14), 8);
*(s16 *)(param_1 + 0x18) = func_80012ABC((s32)*(s16 *)(param_1 + 0x18), (s32)*(s16 *)(param_1 + 0x20), 8);
*(s16 *)(param_1 + 0x1A) = func_80012ABC((s32)*(s16 *)(param_1 + 0x1A), (s32)*(s16 *)(param_1 + 0x22), 8);
*(s16 *)(param_1 + 0x1C) = func_80012ABC((s32)*(s16 *)(param_1 + 0x1C), (s32)*(s16 *)(param_1 + 0x24), 8);
*(s16 *)(param_1 + 0x28) = func_80012C6C((s32)*(s16 *)(param_1 + 0x28), (s32)*(s16 *)(param_1 + 0x2E), 0x10);
*(s16 *)(param_1 + 0x2A) = func_80012C6C((s32)*(s16 *)(param_1 + 0x2A), (s32)*(s16 *)(param_1 + 0x30), 0x10);
*(s16 *)(param_1 + 0x2C) = func_80012C6C((s32)*(s16 *)(param_1 + 0x2C), (s32)*(s16 *)(param_1 + 0x32), 0x10);
*(s32 *)(param_1 + 0x48) = (s32)*(s16 *)(param_1 + 0x28) + (s32)param_2[0];
*(s32 *)(param_1 + 0x4C) = (s32)*(s16 *)(param_1 + 0x2A) + (s32)param_2[1];
*(s32 *)(param_1 + 0x50) = (s32)*(s16 *)(param_1 + 0x2C) + (s32)param_2[2];
func_80049CAC(param_1 + 0x18, (s32)&m1);
m1.t[0] = *(s16 *)(param_1 + 0x28) + param_2[0];
m1.t[1] = *(s16 *)(param_1 + 0x2A) + param_2[1];
m1.t[2] = *(s16 *)(param_1 + 0x2C) + param_2[2];
svec_in.vx = 0;
svec_in.vy = 0;
svec_in.vz = *(s32 *)(param_1 + 0x10);
((void (*)(s32, s32, s32))func_8012F14C)((s32)&m1, (s32)&svec_in, (s32)&svec_out);
*(s32 *)(param_1 + 0x3C) = (s32)svec_out.vx;
*(s32 *)(param_1 + 0x40) = (s32)svec_out.vy;
*(s32 *)(param_1 + 0x44) = (s32)svec_out.vz;
}
INCLUDE_ASM("asm/ov_SC07_001/nonmatchings/ov_SC07_001_jr_8017BEBC", func_8017E0AC);