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https://github.com/Druthulu/BFM-decomp
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feat(decomp): parallel gate — 4 fns across 4 binaries (10 workers)
ov_SC01_084 func_80181310 ov_SC01_080 func_80180D54 ov_SC03_030 func_80181A60 ov_SC06_000 func_80183398
This commit is contained in:
Drew T
@@ -6433,7 +6433,124 @@ void func_801809E4(s32 param_1) {
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}
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INCLUDE_ASM("asm/ov_SC01_080/nonmatchings/ov_SC01_080_jr_8017AE2C", func_80180D54);
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/* func_80180D54 — MATCH (match_one closeness 0, 119/119).
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*
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* Provenance / declarations (all copied from this same TU,
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* src/ov_SC01_080/ov_SC01_080_jr_8017AE2C.c, cookbook §135-8):
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* D_800B99DA (u16) — TU col-0 decl, line 615 / 6703
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* D_801C7540 (s16) — TU col-0 decl, line 6158 / 6507 / 6704
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* D_801C5D40 (u8[]) — TU col-0 decl, line 6273 / 6319 / 6705
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* D_80127188 (s32) — TU col-0 decl, line 5477 / 6274 / 6320
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* func_800D20C0(void*,void*,s32), func_800D23D0(void*) — line 1711/1713, 6161/6162
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* func_8012913C(s32)->u8*, func_801291C0(void)->u8* — line 6317/6318
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* Every symbol re-checked against this .s's own relocation lines (law 1c);
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* jal order in the .s is 800D20C0, 800D23D0, 801291C0, 801291C0, 8012913C, 8012913C,
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* which is the source order below.
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*
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* NOT the same function as the same-address func_80180D54 banked in ov_SC02_035 /
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* ov_SC03_097 — those overlays hold different code at 0x80180D54; discarded.
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*
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* Codegen notes (each closed a residual; twin of func_801815D4 at line 6711 of this TU):
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* - The two `__asm__("" : "=r"(pN) : "0"(pN))` pins are LOAD-BEARING (house idiom, taken
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* verbatim from func_801815D4). Without them gcc CSEs `sp10+4` into one pseudo that is
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* live across func_800D20C0, so it takes a callee-saved register: the arg lands in $s1
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* instead of $s0, an extra `move $a1,$s0` appears in the prologue, and the second call's
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* delay slot holds `move $a0,$s0` instead of `addiu $a0,$sp,0x18`. Measured: removing
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* them costs +1 insn and 118 mismatches.
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* - `cnt` is loaded BEFORE the D_801C7540 store in SOURCE order. The store aliases the
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* load for true_dependence(), so with the natural order sched1 cannot hoist the
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* `lw 0x1C($s0)` into the load-delay nop after `lhu 0x1A($sp)` (costs a nop, §3-T2).
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* - `mask` is pinned to $s3 (§17/§148-C register pin). 0x3FF and 0x19 are both invariants
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* of the do/while; only ONE of the pair gets hoisted by move_movables at this loop's
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* insn_count (§148-A), and whichever is written as an explicit pre-loop local wins the
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* allocno tiebreak and takes the LOWER hard reg. The target wants the opposite pairing
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* ($s2=0x19 hoisted, $s3=0x3FF explicit). Making 0x19 the explicit local instead flips
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* the registers correctly but frees a movable slot, so `&D_801C5D40` then hoists into
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* $s4 as well (+4 insns, frame 0x40). The pin gets the register order with no side
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* effect on the hoist budget. Measured: close 11 -> 3.
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* - `q` must be a SEPARATE local from `p`: sharing one pointer variable makes the
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* func_8012913C result inherit $a0 (the register `p` needs inside the loops), where the
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* target uses $v1 because 1 is being materialized into $v0 for the delay slot.
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* Measured: close 3 -> 0.
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* - The `sll/sra` before the `slti 0xC0` is CSE store-forwarding: the `+= 1` keeps the
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* HImode value, so the signed compare must sign-extend the just-stored register.
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*/
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extern u16 D_800B99DA;
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extern s16 D_801C7540;
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extern u8 D_801C5D40[];
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extern s32 D_80127188;
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extern void func_800D20C0(void *a0, void *a1, s32 a2);
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extern void func_800D23D0(void *a0);
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extern u8 *func_8012913C(s32 a0);
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extern u8 *func_801291C0(void);
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void func_80180D54(s32 param_1) {
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u16 sp10[6];
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u16 *p0;
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u16 *p1;
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register s16 mask __asm__("$19");
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s16 i;
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u8 *p;
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u8 *q;
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s32 cnt;
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sp10[2] = 0;
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sp10[1] = 0;
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sp10[0] = 0;
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p0 = sp10;
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p1 = sp10 + 4;
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__asm__("" : "=r"(p0) : "0"(p0));
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__asm__("" : "=r"(p1) : "0"(p1));
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func_800D20C0(p0, p1, 1);
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func_800D23D0(sp10 + 4);
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cnt = *(s32 *)(param_1 + 0x1C);
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D_801C7540 = sp10[5] - 0x400;
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if (cnt != 0) {
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*(s32 *)(param_1 + 0x1C) = cnt - 1;
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mask = 0x3FF;
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i = 0;
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do {
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p = func_801291C0();
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if (p != 0) {
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*(u16 *)p = 0x19;
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*(u16 *)(p + 0x2C) = mask;
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*(s32 *)(p + 0x34) = (s32)&D_801C5D40 + (*(s16 *)(param_1 + 0xDC) << 5);
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*(u16 *)(param_1 + 0xDC) = *(u16 *)(param_1 + 0xDC) + 1;
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if (*(s16 *)(param_1 + 0xDC) >= 0xC0) {
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*(s16 *)(param_1 + 0xDC) = 0;
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}
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}
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i = i + 1;
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} while (i <= 0);
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} else if (D_80127188 < 4) {
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if ((D_800B99DA & 1) == 0) {
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mask = 0x3FF;
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i = 0;
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do {
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p = func_801291C0();
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if (p != 0) {
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*(u16 *)p = 0x19;
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*(u16 *)(p + 0x2C) = mask;
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*(s32 *)(p + 0x34) = (s32)&D_801C5D40 + (*(s16 *)(param_1 + 0xDC) << 5);
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*(u16 *)(param_1 + 0xDC) = *(u16 *)(param_1 + 0xDC) + 1;
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if (*(s16 *)(param_1 + 0xDC) >= 0xC0) {
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*(s16 *)(param_1 + 0xDC) = 0;
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}
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}
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i = i + 1;
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} while (i <= 0);
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}
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} else {
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func_8012913C(0x1C);
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q = func_8012913C(0x1C);
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if (q != 0) {
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*(u16 *)(q + 0x2C) = 1;
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}
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*(u16 *)(param_1 + 0x2) = *(u16 *)(param_1 + 0x2) + 1;
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}
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}
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extern void (*D_8018A22C[])(void);
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@@ -3833,7 +3833,63 @@ void func_801812F4(void *a0) {
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}
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INCLUDE_ASM("asm/ov_SC01_084/nonmatchings/ov_SC01_084_jr_8017F690", func_80181310);
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extern s16 D_801C7748;
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extern s16 D_801C774C;
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extern s32 D_801270C8;
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extern s32 D_801270D0;
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extern s16 D_8018A9EC[];
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extern s32 D_8018A9F0;
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extern s32 func_8012C658(s32 arg0, s32 arg1, s32 arg2);
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void func_80181310(void) {
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s16 *p;
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s32 *r;
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s32 *u;
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s32 t;
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if (D_801C774C == 1) {
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p = D_8018A9EC;
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r = &D_801270C8;
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*r = 0;
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t = D_801C7748;
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if (D_8018A9F0 != -1) {
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do {
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if (p[0] <= t && t < p[1]) {
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switch (*(s32 *)(p + 2)) {
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case 1:
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u = &D_801270D0;
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if (*u == 0) {
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*u = 1;
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func_8012C658(0x26, 0x100, 0);
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func_8012C658(0x26, 0x101, 0);
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func_8012C658(0x26, 0x102, 0);
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}
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break;
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case 2:
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/* (&D_801270C8)[3] == D_801270D4; written as an offset from the
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D_801270C8 base so gcc reuses the base register ($a0 + 0xC). */
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if ((&D_801270C8)[3] == 0 && D_801C7748 < 0x2501) {
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func_8012C658(0x1D, 0, 0);
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(&D_801270C8)[3]++;
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}
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break;
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case 3:
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if ((&D_801270C8)[3] == 0 && D_801C7748 < 0x2501) {
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func_8012C658(0x1D, 1, 0);
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(&D_801270C8)[3]++;
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}
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break;
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case 4:
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D_801270C8 = 1;
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break;
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}
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}
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p += 4;
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} while (*(s32 *)(p + 2) != -1);
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}
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}
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}
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extern void (*D_8018AA2C[])(void);
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extern s16 D_801C774C;
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@@ -6597,7 +6597,7 @@ void func_801814F4(s32 param_1) {
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extern s32 func_80181824();
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extern void RotTransSV(void *a0, void *a1, void *a2);
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extern void RotMatrixZ(s32 a0, void *a1);
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extern void func_80181A60(void *a0);
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extern void func_80181A60();
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extern u8 D_801869E0[];
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extern u8 D_801869E8[];
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@@ -6761,7 +6761,178 @@ s32 func_80181824(s32 param_1, s32 param_2)
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}
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INCLUDE_ASM("asm/ov_SC03_030/nonmatchings/ov_SC03_030_jr_8017AE2C", func_80181A60);
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/* func_80181A60 — ov_SC03_030 / ov_SC03_030_jr_8017AE2C (106 ins).
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*
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* Build one 0x10-byte white LINE_F2 GPU packet, project the caller's two
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* SVECTORs through the GTE with the D_800AF648 rot/trans matrix, write the two
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* screen (x,y) pairs into the packet, and — only when BOTH rtps calls come back
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* with no flag bits other than 0x1000 — link the packet into the current OT
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* (D_800A651C[D_800B9A02].a) at depth otz>>2 with the open-coded PSY-Q addPrim
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* RMW pair. Sibling idiom: src/800.c func_80015D4C / func_80015F04 (both
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* MATCHED) — same allocator + same addPrim asymmetry (first half inlines the
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* OT-slot address, second half self-accumulates it into the otz*4 register).
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*
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* STATUS: match_one MATCH, 106/106 (S71 fable redraw, recovered from the opus
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* closeness-2 body at .run/S71a_1/opus/scratch_func_80181A60/base.c).
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*
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* THREE ZERO-BYTE LEVERS:
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* 1. `register u32 tag0 __asm__("$5")` — the packet tag word read into its own
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* pinned local (cf. src/800.c func_80015D4C's "$4" pin). Unpinned, tag0
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* steals $v1 and the whole packet/mask/matrix register set shifts by one.
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* 2. `register u32 mFF __asm__("$6")` — mFF and the CSE'd &D_800B9A02 base tie
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* in global-alloc and land swapped ($a3/$a2) without the pin.
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* 3. THE LAST 2 (a sched2 LUID tie): the target block reads lhu(ix), then
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* lw tag0, then lw otz. At sched2 all three loads are priority 1 and the
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* tie falls to LUID = sched1's OUTPUT order. sched1's birthing boost
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* (single-set dest) sinks a boosted load to just before its consumer, so:
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* - tag0 single-set -> boosted -> sinks below the otz load (LUID too high);
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* - tag0 2-set, lhu single-set -> tag0 starves to the block TOP, above the
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* still-boosted lhu (the "overshoot": lw before lhu);
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* - BOTH 2-set -> both priority 1, the final tie is source order, and
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* `ix = lhu; tag0 = lw;` gives exactly lhu < tag0 < otz.
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* The lhu's dest gets its 2nd set from a VOLATILE dead re-tie
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* `__asm__ volatile("" : "=r"(ix) : "0"(ix));` placed AFTER the first
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* addPrim store:
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* - volatile, because a non-volatile re-tie whose output is dead is deleted
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* (vJ1: boost back, 2 off);
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* - after the store, because a re-tie right after the lhu is a reorg
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* stop_search_p wall in the bnez fall-through thread -> nop delay slot
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* (A1: 39 off);
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* - NOT a plain second `ix = *(u16 *)&D_800B9A02;` in the 2nd half: the
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* long-lived 2-set pseudo swaps ix/base ($a3/$v1) in local-alloc (8 off).
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* `u16 ix` cannot work (combine folds lhu+zext into fresh single-set SI
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* temps) and a `register ... __asm__("$3")` ix cannot either (cse
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* forward-substitutes the zero-extend temp past the hard-reg copy).
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*
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* Symbol audit (law 1c — match_one masks jal/HI16/LO16): the .s names exactly
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* four relocated symbols and this draft names those four and no others —
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* `jal func_80010A08` ($a0 = 0x10), `%hi/%lo(D_800AF648)` (address-of, GTE
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* matrix base), `%hi/%lo(D_800B9A02)` (address-of, then `lhu` => u16 read),
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* `%lo(D_800A651C)($at)` x2 (lw, index scaled *20 = sizeof{s32 a; s32 b[4]}).
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* Both bnez targets are .L80181BF4 (the shared epilogue).
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*
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* TU CHECK vs src/ov_SC03_030/ov_SC03_030_jr_8017AE2C.c:
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* - `extern s16 D_800B9A02;` (TU:2469) copied verbatim; `lhu` forced with
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* `*(u16 *)&`, the idiom this TU already uses at line 3708.
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* - `extern u8 D_800AF648[];` (TU:5292) copied verbatim.
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* - `func_80010A08` has no file-scope decl in the TU; fleet decl (void *, (s32)).
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* - D_800A651C declared at BLOCK scope (engine_core.h's DEFINE_ macros declare
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* it scalar in their own bodies) — the src/800.c func_80015D4C dodge.
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* - GTE macro names carry an _A60 suffix (the TU defines unsuffixed
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* gte_SetRotMatrix/gte_stszotz etc. elsewhere).
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* - BANK NOTE: TU:6600 forward-declares `extern void func_80181A60(void *a0);`
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* -> §378 variant 1 (fix_arity_callers/cast_self_callers). Defining the
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* function as `(void *arg0)` with a local `v = arg0` copy is NOT
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* byte-equivalent (+$s1, 109 off) — keep the typed pointer parameter.
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*/
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#include "common.h"
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typedef struct { s16 vx, vy, vz, pad; } SVec_80181A60;
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typedef struct { s32 a; s32 b[4]; } OtBlk_80181A60;
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typedef struct {
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u8 addr[3];
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u8 len;
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u8 r0, g0, b0, code;
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s16 x0, y0;
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s16 x1, y1;
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} LineF2_80181A60;
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/* PSY-Q GTE macros — same forms already used in this TU (func_80181708/func_80181824). */
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#define gte_SetRotTransMatrix_A60(r0) __asm__ volatile ( \
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"lw $12, 0( %0 );" \
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"lw $13, 4( %0 );" \
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"ctc2 $12, $0;" \
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"ctc2 $13, $1;" \
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"lw $12, 8( %0 );" \
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"lw $13, 12( %0 );" \
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"lw $14, 16( %0 );" \
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"ctc2 $12, $2;" \
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"ctc2 $13, $3;" \
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"ctc2 $14, $4;" \
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"lw $12, 20( %0 );" \
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"lw $13, 24( %0 );" \
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"ctc2 $12, $5;" \
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"lw $14, 28( %0 );" \
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"ctc2 $13, $6;" \
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"ctc2 $14, $7" \
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: \
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: "r"( r0 ) \
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: "$12", "$13", "$14" )
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#define gte_ldv0_A60(r0) __asm__ volatile ( \
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"lwc2 $0, 0( %0 );" \
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"lwc2 $1, 4( %0 )" \
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: \
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: "r"( r0 ) )
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#define gte_rtps_A60() __asm__ volatile ("nop;nop;rtps")
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#define gte_stsxy_A60(r0) __asm__ volatile ( \
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"swc2 $14, 0( %0 )" \
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: \
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: "r"( r0 ) \
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: "memory" )
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#define gte_stflg_A60(r0) __asm__ volatile ( \
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"cfc2 $12, $31;" \
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"nop;" \
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"sw $12, 0( %0 )" \
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: \
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: "r"( r0 ) \
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: "$12", "memory" )
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#define gte_stszotz_A60(r0) __asm__ volatile ( \
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"mfc2 $12, $19;" \
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"nop;" \
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"sra $12, $12, 2;" \
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"sw $12, 0( %0 )" \
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: \
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: "r"( r0 ) \
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: "$12", "memory" )
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extern void *func_80010A08(s32);
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void func_80181A60(SVec_80181A60 *v)
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{
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extern OtBlk_80181A60 D_800A651C[];
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LineF2_80181A60 *p;
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u8 *mx;
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u32 m24;
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register u32 mFF __asm__("$6");
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s32 flag;
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s32 otz;
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s32 sh;
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register u32 tag0 __asm__("$5");
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u32 ix;
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p = (LineF2_80181A60 *)func_80010A08(0x10);
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m24 = 0x00FFFFFF;
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p->len = 3;
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mx = D_800AF648;
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*(u32 *)&p->r0 = m24;
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p->code = 0x40;
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gte_SetRotTransMatrix_A60(mx);
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gte_ldv0_A60(v);
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gte_rtps_A60();
|
||||
gte_stsxy_A60(&p->x0);
|
||||
gte_stflg_A60(&flag);
|
||||
gte_stszotz_A60(&otz);
|
||||
if ((flag & ~0x1000) == 0) {
|
||||
v++;
|
||||
gte_ldv0_A60(v);
|
||||
gte_rtps_A60();
|
||||
gte_stsxy_A60(&p->x1);
|
||||
gte_stflg_A60(&flag);
|
||||
if ((flag & ~0x1000) == 0) {
|
||||
mFF = 0xFF000000;
|
||||
ix = *(u16 *)&D_800B9A02;
|
||||
tag0 = *(u32 *)p;
|
||||
tag0 = tag0 & mFF;
|
||||
sh = otz * 4;
|
||||
*(u32 *)p = tag0 | (*(u32 *)(sh + D_800A651C[ix].a) & m24);
|
||||
__asm__ volatile("" : "=r"(ix) : "0"(ix));
|
||||
sh = sh + D_800A651C[*(u16 *)&D_800B9A02].a;
|
||||
*(u32 *)sh = (*(u32 *)sh & mFF) | ((u32)p & m24);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
extern void func_8012C218(void *a0);
|
||||
|
||||
|
||||
@@ -8135,7 +8135,63 @@ void func_80183338(void *a0) {
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC06_000/nonmatchings/ov_SC06_000_jr_8017AE2C", func_80183398);
|
||||
void func_80183398(s32 a0) {
|
||||
extern s32 D_801AECB0;
|
||||
extern s16 func_801825D8(void);
|
||||
extern s32 func_8012BEE8(s32 a0);
|
||||
extern void func_8012B2CC(s32 a0);
|
||||
extern void func_801823BC();
|
||||
extern void func_80182464(s32 a0, s32 a1);
|
||||
s32 ptr;
|
||||
s32 t;
|
||||
u16 v;
|
||||
s32 pad[2];
|
||||
|
||||
if (*(s16 *)(a0 + 0x70) != 0) {
|
||||
if (D_801AECB0 != 0) {
|
||||
if (*(u16 *)(a0 + 0x34) == 0) {
|
||||
v = *(u16 *)(a0 + 0x100) - 4;
|
||||
*(u16 *)(a0 + 0x100) = v;
|
||||
if ((s16)v < -0x27F) {
|
||||
*(u16 *)(a0 + 0x34) = *(u16 *)(a0 + 0x34) + 1;
|
||||
}
|
||||
} else {
|
||||
v = *(u16 *)(a0 + 0x100) + 4;
|
||||
*(u16 *)(a0 + 0x100) = v;
|
||||
if ((s16)v >= 0) {
|
||||
*(u16 *)(a0 + 0x34) = *(u16 *)(a0 + 0x34) - 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
ptr = *(s32 *)(a0 + 0x20);
|
||||
*(u16 *)(ptr + 0x12) = *(u16 *)(ptr + 0x12) - 4;
|
||||
t = ((s32 (*)(void)) func_801825D8)();
|
||||
*(s16 *)(a0 + 0xA) = (*(u16 *)(a0 + 0xFE) + *(u16 *)(a0 + 0x100)) + t - 0x131;
|
||||
func_80182464(*(s16 *)(*(s32 *)(a0 + 0x20) + 0x12), *(s16 *)(a0 + 0xA));
|
||||
} else {
|
||||
if (D_801AECB0 != 0 && func_8012BEE8(a0) != 0) {
|
||||
if (*(u16 *)(a0 + 0x34) == 0) {
|
||||
v = *(u16 *)(a0 + 0x100) - 6;
|
||||
*(u16 *)(a0 + 0x100) = v;
|
||||
if ((s16)v < -0x3BF) {
|
||||
*(u16 *)(a0 + 0x34) = *(u16 *)(a0 + 0x34) + 1;
|
||||
}
|
||||
} else {
|
||||
v = *(u16 *)(a0 + 0x100) + 6;
|
||||
*(u16 *)(a0 + 0x100) = v;
|
||||
if ((s16)v >= 0) {
|
||||
*(u16 *)(a0 + 0x34) = *(u16 *)(a0 + 0x34) - 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
ptr = *(s32 *)(a0 + 0x20);
|
||||
*(u16 *)(ptr + 0x12) = *(u16 *)(ptr + 0x12) + 4;
|
||||
*(s16 *)(a0 + 0xA) = *(u16 *)(a0 + 0xFE) + *(u16 *)(a0 + 0x100);
|
||||
func_801823BC(*(s16 *)(*(s32 *)(a0 + 0x20) + 0x12), *(s16 *)(a0 + 0xA));
|
||||
}
|
||||
func_8012B2CC(a0);
|
||||
}
|
||||
|
||||
|
||||
|
||||
extern void (*D_8018C734[])(void);
|
||||
|
||||
Reference in New Issue
Block a user