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feat(decomp): main lane m12 — 7 banked

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One clean whole-EXE rebuild verified the batch (gate_main), and main re-checked
BYTE-IDENTICAL against config/check.us.sha before anything was credited.

  GsTMDfastF3GNL
  GsTMDfastG4GNL
  SetSXSYfifo
  VM_NO1_OBJ_184
  func_8002F150
  func_80053AD8
  func_800626F0
This commit is contained in:
Drew T
2026-08-25 01:39:08 -06:00
parent 32eafed7b2
commit 6fe90cd9ba
5 changed files with 368 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/800.c
+36 -1
View File
@@ -14086,7 +14086,42 @@ void func_8002F12C(s32 a0) {
func_8002DC68(*(s32 *)(a0 + 4), 0);
}
INCLUDE_ASM("asm/nonmatchings/800", func_8002F150);
extern u8 D_800A4694[];
void func_8002F150(s32 arg0) {
struct F150Rec {
u8 pad[0x0E];
u8 flg[8];
u8 tail[0x3E];
};
struct F150Slot {
u8 pad[0x20];
u32 u20;
u32 u24;
u32 u28;
u32 u2C;
u16 u30;
u8 mid[5];
u8 u37;
u8 u38;
u8 tail[0x1B];
};
struct F150Rec *rec = (struct F150Rec *)D_800A4694 + arg0;
struct F150Slot *slots = (struct F150Slot *)(D_800A4694 + 0x2F4);
s32 i;
s32 val;
for (i = 0, val = -0x18; i < 8; i++) {
if (rec->flg[i]) {
slots[i].u28 = slots[i].u20 - 0x100;
slots[i].u37 |= 1;
slots[i].u30 = 0;
slots[i].u38 = 0;
slots[i].u2C = val;
}
}
}
typedef struct F1ccRec {
u8 pad[0x0E];
src/800b2.c
+225 -2
View File
@@ -297,7 +297,110 @@ void *GsTMDfastF3GL(void *prim, void *vert, void *norm, void *pkt,
);
}
INCLUDE_ASM("asm/nonmatchings/800b2", GsTMDfastF3GNL);
void *GsTMDfastF3GNL(void *prim, void *vert, void *norm, void *pkt,
int n, int shift, void *ot, void *work)
{
__asm__ __volatile__(
".set\tnoreorder\n"
"addiu $sp, $sp, -8\n"
"lw $t6, 24($sp)\n"
"lw $v0, 28($sp)\n"
"lw $v1, 32($sp)\n"
"lw $t0, 36($sp)\n"
"lw $v1, 4($v1)\n"
"addu $t2, $zero, $zero\n"
"sw $v0, 12($t0)\n"
"blez $t6, 2f\n"
" sw $v1, 16($t0)\n"
"lui $t3, 255\n"
"ori $t3, $t3, 65535\n"
"addiu $t5, $t0, 24\n"
"addiu $a2, $a0, 12\n"
"addiu $t1, $a3, 20\n"
"1:\n"
"lhu $a0, 6($a2)\n"
"lhu $v1, 8($a2)\n"
"lhu $v0, 10($a2)\n"
"sll $a0, $a0, 3\n"
"addu $a0, $a1, $a0\n"
"sll $v1, $v1, 3\n"
"addu $v1, $a1, $v1\n"
"sll $v0, $v0, 3\n"
"addu $v0, $a1, $v0\n"
"lwc2 $0, 0($a0)\n"
"lwc2 $1, 4($a0)\n"
"lwc2 $2, 0($v1)\n"
"lwc2 $3, 4($v1)\n"
"lwc2 $4, 0($v0)\n"
"lwc2 $5, 4($v0)\n"
"nop\n"
"nop\n"
"cop2 0x0280030\n" /* rtpt */
"lw $v0, -8($a2)\n"
"nop\n"
"and $v0, $v0, $t3\n"
"sw $v0, -16($t1)\n"
"lbu $v0, -9($a2)\n"
"nop\n"
"ori $v0, $v0, 16\n"
"sb $v0, -13($t1)\n"
"addiu $v0, $t0, 36\n"
"cfc2 $t4, $31\n"
"nop\n"
"sw $t4, 0($v0)\n"
"lw $v0, 36($t0)\n"
"nop\n"
"bltz $v0, 3f\n"
" nop\n"
"nop\n"
"nop\n"
"cop2 0x1400006\n" /* nclip */
"lw $v0, -4($a2)\n"
"nop\n"
"sw $v0, -8($t1)\n"
"swc2 $24, 0($t5)\n"
"lw $v0, 24($t0)\n"
"nop\n"
"blez $v0, 3f\n"
" nop\n"
"swc2 $12, 8($a3)\n"
"swc2 $13, 16($a3)\n"
"swc2 $14, 24($a3)\n"
"nop\n"
"nop\n"
"cop2 0x158002D\n" /* avsz3 */
"lw $v0, 0($a2)\n"
"nop\n"
"sw $v0, 0($t1)\n"
"swc2 $7, 0($t5)\n"
"lw $v1, 24($t0)\n"
"lw $v0, 12($t0)\n"
"addiu $t1, $t1, 28\n"
"srav $v1, $v1, $v0\n"
"lw $v0, 16($t0)\n"
"sll $v1, $v1, 2\n"
"addu $v0, $v0, $v1\n"
"sw $v0, 52($t0)\n"
"lw $v1, 0($v0)\n"
"lui $v0, 1536\n"
"and $v1, $v1, $t3\n"
"or $v1, $v1, $v0\n"
"sw $v1, 0($a3)\n"
"and $v1, $a3, $t3\n"
"lw $v0, 52($t0)\n"
"addiu $a3, $a3, 28\n"
"sw $v1, 0($v0)\n"
"3:\n"
"addiu $t2, $t2, 1\n"
"slt $v0, $t2, $t6\n"
"bnez $v0, 1b\n"
" addiu $a2, $a2, 24\n"
"2:\n"
"addu $v0, $a3, $zero\n"
"addiu $sp, $sp, 8\n"
".set\treorder\n"
);
}
/* GsTMDfastF4GL - handwritten PsyQ libgs assembly (GTE cop2 ops, 12 args,
@@ -818,4 +921,124 @@ void GsTMDfastG4GL(void)
: : : "memory");
}
INCLUDE_ASM("asm/nonmatchings/800b2", GsTMDfastG4GNL);
void GsTMDfastG4GNL(void)
{
__asm__ __volatile__(
".set\tnoreorder\n"
"addiu $sp, $sp, -8\n"
"lw $t8, 24($sp)\n"
"lw $v0, 28($sp)\n"
"lw $v1, 32($sp)\n"
"lw $t0, 36($sp)\n"
"lw $v1, 4($v1)\n"
"addu $t2, $zero, $zero\n"
"sw $v0, 12($t0)\n"
"blez $t8, 2f\n"
"sw $v1, 16($t0)\n"
"addiu $t6, $t0, 40\n"
"lui $t7, 0x8000\n"
"addiu $t5, $t0, 24\n"
"lui $t3, 0xff\n"
"ori $t3, $t3, 0xffff\n"
"addiu $a2, $a0, 16\n"
"addiu $t1, $a3, 28\n"
"1:\n"
"lhu $a0, 6($a2)\n"
"lhu $v1, 10($a2)\n"
"lhu $v0, 14($a2)\n"
"sll $a0, $a0, 3\n"
"addu $a0, $a1, $a0\n"
"sll $v1, $v1, 3\n"
"addu $v1, $a1, $v1\n"
"sll $v0, $v0, 3\n"
"addu $v0, $a1, $v0\n"
"lwc2 $0, 0($a0)\n"
"lwc2 $1, 4($a0)\n"
"lwc2 $2, 0($v1)\n"
"lwc2 $3, 4($v1)\n"
"lwc2 $4, 0($v0)\n"
"lwc2 $5, 4($v0)\n"
"nop\n"
"nop\n"
"rtpt\n"
"lw $v0, -12($a2)\n"
"nop\n"
"sw $v0, -24($t1)\n"
"cfc2 $t4, $31\n"
"nop\n"
"sw $t4, 0($t6)\n"
"lw $v0, 40($t0)\n"
"nop\n"
"and $v0, $v0, $t7\n"
"bne $v0, $zero, 3f\n"
"nop\n"
"nop\n"
"nop\n"
"nclip\n"
"lw $v0, -8($a2)\n"
"nop\n"
"sw $v0, -16($t1)\n"
"swc2 $24, 0($t5)\n"
"lw $v0, 24($t0)\n"
"nop\n"
"blez $v0, 3f\n"
"nop\n"
"swc2 $12, 8($a3)\n"
"swc2 $13, 16($a3)\n"
"swc2 $14, 24($a3)\n"
"lhu $v0, 18($a2)\n"
"nop\n"
"sll $v0, $v0, 3\n"
"addu $v0, $a1, $v0\n"
"lwc2 $0, 0($v0)\n"
"lwc2 $1, 4($v0)\n"
"nop\n"
"nop\n"
"rtps\n"
"lw $v0, -4($a2)\n"
"nop\n"
"sw $v0, -8($t1)\n"
"cfc2 $t4, $31\n"
"nop\n"
"sw $t4, 0($t6)\n"
"lw $v0, 40($t0)\n"
"nop\n"
"and $v0, $v0, $t7\n"
"bne $v0, $zero, 3f\n"
"addiu $v0, $a3, 32\n"
"swc2 $14, 0($v0)\n"
"nop\n"
"nop\n"
"avsz4\n"
"lw $v0, 0($a2)\n"
"nop\n"
"sw $v0, 0($t1)\n"
"swc2 $7, 0($t5)\n"
"lw $v1, 24($t0)\n"
"lw $v0, 12($t0)\n"
"addiu $t1, $t1, 36\n"
"srav $v1, $v1, $v0\n"
"lw $v0, 16($t0)\n"
"sll $v1, $v1, 2\n"
"addu $v0, $v0, $v1\n"
"sw $v0, 56($t0)\n"
"lw $v1, 0($v0)\n"
"lui $v0, 0x800\n"
"and $v1, $v1, $t3\n"
"or $v1, $v1, $v0\n"
"sw $v1, 0($a3)\n"
"and $v1, $a3, $t3\n"
"lw $v0, 56($t0)\n"
"addiu $a3, $a3, 36\n"
"sw $v1, 0($v0)\n"
"3:\n"
"addiu $t2, $t2, 1\n"
"slt $v0, $t2, $t8\n"
"bne $v0, $zero, 1b\n"
"addiu $a2, $a2, 36\n"
"2:\n"
"addu $v0, $a3, $zero\n"
"addiu $sp, $sp, 8\n"
".set\treorder\n"
: : : "memory");
}
src/800c2_3.c
+44 -1
View File
@@ -4,6 +4,49 @@ INCLUDE_ASM("asm/nonmatchings/800c2_3", func_800626C8);
INCLUDE_ASM("asm/nonmatchings/800c2_3", func_800626DC);
INCLUDE_ASM("asm/nonmatchings/800c2_3", func_800626F0);
__asm__(
".text\n"
".align 2\n"
".globl func_800626F0\n"
".ent\tfunc_800626F0\n"
"func_800626F0:\n"
".frame $sp, 0, $31\n"
".mask 0x00000000, 0\n"
".fmask 0x00000000, 0\n"
".set\tnoreorder\n"
"lui $at, %hi(D_80078D18)\n"
"sw $ra, %lo(D_80078D18)($at)\n"
"jal func_8005CF08\n"
"nop\n"
"addiu $t1, $0, 87\n"
"addiu $t2, $0, 176\n"
"jalr $t2\n"
"nop\n"
"lw $v0, 364($v0)\n"
"addiu $t1, $0, 11\n"
"addi $v1, $v0, 2180\n"
"lui $at, %hi(jtbl_80078D20_main)\n"
"sw $v1, %lo(jtbl_80078D20_main)($at)\n"
"addi $v1, $v0, 2196\n"
"lui $at, %hi(jtbl_80078D24_main)\n"
"sw $v1, %lo(jtbl_80078D24_main)($at)\n"
".L80062730:\n"
"sw $0, 1428($v0)\n"
"addiu $v0, $v0, 4\n"
"addiu $t1, $t1, -1\n"
"bnez $t1, .L80062730\n"
"nop\n"
"jal FlushCache\n"
"nop\n"
"lui $ra, %hi(D_80078D18)\n"
"lw $ra, %lo(D_80078D18)($ra)\n"
"nop\n"
"jr $ra\n"
"nop\n"
".set\treorder\n"
".end\tfunc_800626F0\n"
"nop\n"
"nop\n"
);
INCLUDE_ASM("asm/nonmatchings/800c2_3", func_80062768);
src/gsgap5.c
+22 -2
View File
@@ -64,7 +64,15 @@ void SetSZfifo4()
"mtc2 $7, $19\n");
}
INCLUDE_ASM("asm/nonmatchings/gsgap5", SetSXSYfifo);
void SetSXSYfifo(long r0, long r1, long r2)
{
__asm__ __volatile__(
"mtc2 %0, $12\n"
"mtc2 %1, $13\n"
"mtc2 %2, $14"
:
: "r"(r0), "r"(r1), "r"(r2));
}
void SetRii()
{
@@ -84,4 +92,16 @@ INCLUDE_ASM("asm/nonmatchings/gsgap5", SetDQA);
INCLUDE_ASM("asm/nonmatchings/gsgap5", SetDQB);
INCLUDE_ASM("asm/nonmatchings/gsgap5", func_80053AD8);
void func_80053AD8()
{
__asm__ __volatile__(
".set\tnoreorder\n"
"sll $4, $4, 4\n"
"sll $5, $5, 4\n"
"sll $6, $6, 4\n"
"ctc2 $4, $21\n"
"ctc2 $5, $22\n"
"ctc2 $6, $23\n"
".set\treorder\n"
);
}
src/sgap_7.c
+41 -1
View File
@@ -2,7 +2,47 @@
INCLUDE_ASM("asm/nonmatchings/sgap_7", vmNoiseOn);
INCLUDE_ASM("asm/nonmatchings/sgap_7", VM_NO1_OBJ_184);
__asm__(
".text\n"
".align\t2\n"
".globl\tVM_NO1_OBJ_184\n"
".type\tVM_NO1_OBJ_184, @function\n"
".ent\tVM_NO1_OBJ_184\n"
"VM_NO1_OBJ_184:\n"
".set\tnoreorder\n"
"lui $t0, %hi(D_800B9B2B)\n"
"lbu $t0, %lo(D_800B9B2B)($t0)\n"
"nop\n"
"sltiu $v0, $t0, 0x40\n"
"beqz $v0, .L80040568\n"
" mult $a2, $t0\n"
"mflo $v0\n"
"lui $v1, 0x0410\n"
"ori $v1, $v1, 0x4105\n"
"multu $v0, $v1\n"
"mfhi $v1\n"
"subu $v0, $v0, $v1\n"
"srl $v0, $v0, 1\n"
"addu $v1, $v1, $v0\n"
"j VM_NO1_OBJ_1F4\n"
" srl $a2, $v1, 5\n"
".L80040568:\n"
"addiu $v0, $zero, 0x7F\n"
"subu $v0, $v0, $t0\n"
"mult $a1, $v0\n"
"mflo $v0\n"
"lui $v1, 0x0410\n"
"ori $v1, $v1, 0x4105\n"
"multu $v0, $v1\n"
"mfhi $v1\n"
"subu $v0, $v0, $v1\n"
"srl $v0, $v0, 1\n"
"addu $v1, $v1, $v0\n"
"srl $a1, $v1, 5\n"
".set\treorder\n"
".size\tVM_NO1_OBJ_184, . - VM_NO1_OBJ_184\n"
".end\tVM_NO1_OBJ_184\n"
);
__asm__(
".text\n"