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feat(phase-30 S2): func_80176734 BANKED — 371 ins, the largest single item in the frontier
Structure-first crack (agent, 371/371 byte-exact, independently re-verified by match_one before gating). Levers were type- and placement-driven rather than pins: u8 locals produce the andi masks (a QImode result sends the arithmetic arms through force_to_mode while the comparison keeps its zero_extend); cross-BB placement defeats combine (LOG_LINKS are per-BB); a DUPLICATED store keeps the following re-read in a fresh EBB so it stays a real lbu; and a deliberately-unused u8 dum[8] because the target's .frame says vars=8 with no spill in the body — the original had a dead local. Only non-call-spanning pins used, so the body is x137-safe (§44). Family: 371 ins x 138 = 51,198 templatable ins — the single largest item on the board.
This commit is contained in:
Drew T
@@ -3663,7 +3663,346 @@ L63C:
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}
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INCLUDE_ASM("asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_801734BC", func_80176734);
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// @class: regalloc-order + schedule
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// @stuck: none — MATCH (371/371 ins, match_one MATCH)
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//
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// func_80176734 — ov_SC01_077 HUD-state pump, 371 ins. Direct sibling of the already-matched
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// func_80176218 in the same TU: same base quartet
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// $s3 = st = &D_8011F7A8 (int base, NOT u8* — see 80176218's note)
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// $s1 = cach = st + 0x48 (the cached/displayed copy)
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// $s2 = flag = st + 0xE0 (the per-field "changed" flags)
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// $s4 = cur = &D_80078E78 (the live gameplay struct)
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// and the same OFFSET-FIRST index idiom `((param<<16)>>14) + st + 0x28`
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// (a u8* base emits `addu rd,st,off`; the target wants `addu rd,off,st`).
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//
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// CONTROL-FLOW SKELETON (byte-derived from the .s; no loops, one switch, 8 straight-line blocks):
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// A p = st.ptr[param]; q = p+0x3C
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// if (D_801152BA) { triangle-wave pulse byte -> q[4] and p[4]; st[8] += D_80115214 }
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// else { p[0x40] = p[4] = 0x80 }
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// B if (flag[0x48]) { p->[0xD] = anim[flag48]; if (flag48<4) flag48++ else {draw + advance} }
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// C else if (cach[0x48] != cur[0x48]) { seed flag48 (5 or 0); cach48 = cur48; draw; flag48++ }
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// D 0x2E sync (equality-first if/else) + the 0x49 gauge byte
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// E 0x1E sign-bit flip -> one of two func_800183E0 calls
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// F D_800B9A13 mode byte -> chg
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// G switch (cur[0x48]) { 3,4,5 -> amp=0xFF on hit; 6 -> amp=0xBA } (gcc decision tree, no jtbl)
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// H if (amp) { flag[0x47]=1; cach[0x4B]=cur48|0xF0; cach[0x47]=(D_80126D20<<7)/amp; goto tail }
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// I else derive tgt/chg2 from D_80126CE0 or cur[0x47]
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// J if (!chg2 && !chg && !flag[0x47]) goto tail; chg==0 -> flag[0x47]=0 (out-of-line else)
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// K else slew cach[0x47] toward tgt (-3 / -8, clamp, flag[0x47]=1)
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// L tail: st.ptr[param][0x32] = st[0x12]+m+5 ; func_801775E0(ptr+0x64, st[0x12]+m+9)
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// Frame 0x40, $ra at 0x3C, $s0-$s6 saved at 0x20..0x38.
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//
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// LEVERS THAT CLOSED IT (335 -> 206 -> 96 -> 57 -> 36 -> 19 -> 15 -> 5 -> 0):
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//
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// L1 `u8 b` + `u8 v` in block A is what produces the target's `andi $v0,$v1,0xFF`.
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// With `s32 v` combine folds the QI zero_extend straight into the `sltiu` (no andi);
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// with a QImode *result* the arithmetic arms go through force_to_mode (mask dropped ->
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// `addiu $v0,$v1,-0x80` / `nor;addiu` on the RAW lbu reg) while the comparison keeps its
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// zero_extend as a real `andi`. Same idiom for `u8 k` in block C and `u8 m` in block F.
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//
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// L2 `q = p + 0x3C` must be computed in the ENTRY block (before the D_801152BA branch).
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// combine's LOG_LINKS are per-basic-block, so a cross-BB `q` cannot be folded back into
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// `sb v,0x40(p)` — which is exactly why the target keeps a separate `addiu $a0,$a1,0x3C`.
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//
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// L3 THE COPY-TEMP FAMILY (5 of the 7 missing instructions were `move` insns gcc had deleted).
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// `t = (a != b); x = t;` normally collapses to one `sltu x,...`. Two ways to keep the copy:
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// (a) give `t` a second use AND a `register __asm__` pin (block F: `register s32 t $2`);
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// (b) a zero-byte single-set fence `__asm__("" : "=r"(t) : "0"(t));` between the compute
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// and the copy — the copy then links to the asm, which combine cannot substitute.
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// (b) is used for `av = amp` (switch merge), `chg2 = t` (block I) and `c = chg` (block J).
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// The block-J fence does double duty: it re-defines `c` so cse's record_jump_equiv loses
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// `c == 0` on the fall-through path and the target's *second* `beqz $v1` survives.
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//
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// L4 Block K: the store must be DUPLICATED into both arms (`= c-3` / `= c-8`), not written once
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// after a phi. cse runs before cross_jump, so with two stores the following
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// `c = *(u8*)(cach+0x47)` sits in a fresh extended basic block and stays a REAL `lbu`;
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// write it once and cse forwards the stored value into an `andi` (-1 ins). cross_jump then
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// merges the two `sb`s back into the single one at .L80176C3C. (Same lever as 80176218 L1.)
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//
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// L5 `u8 dum[8]` — the target's `.frame` has vars=8 (frame 0x40 vs 0x38 with no stack locals and
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// no spill anywhere in the body). gcc allocates frame space for an aggregate local in
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// expand_decl whether or not it is ever read, so the original had a dead local here.
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//
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// L6 `pv` (a plain copy of the parameter) is what splits the parameter's live range the way the
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// target does: block A indexes off `param_1` (whose pseudo dies in the entry block -> $a0, so
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// `sll $v0,$a0,16` can be scheduled before the save) while blocks B..L index off `pv` -> $s6.
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// `ix` is hoisted out of block A so the `pv = param_1` copy lands after the index chain and
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// before cach/flag/cur — that is the target's prologue interleave (s3, index, s6, s1, s2, s4).
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//
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// L7 Pins that only fix first-fit order (none spans a `jal`, so all are x N-safe per §44):
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// chg=$s5($21), chg2=$s0($16), tgt=$a1($5), p=$a1($5) in block A, pp=$a1($5) in blocks B/C.
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// `p`/`pp` on $a1 is the one that cascades: it frees $a0 for `q` and for the block-B base,
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// and it is what lets reorg steal `sll $a0,$s6,16` into the .L80176C8C delay slot.
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//
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// L8 Block I else-arm: cache cach[0x47] in a `u32 cv` local. Reading it twice through the
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// pointer makes gcc re-mask (`andi $v1,$v1,0xff`, +1 ins); the local keeps both compares on
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// the raw lbu reg like the target. Block K: hoist `sv = (s16)tgt` so the `!= 0` test reuses
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// the sign-extended $a0 instead of emitting `andi $a1,0xffff`.
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//
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// Declaration environment: every extern is block-scoped (§28/§43 zero file-scope footprint).
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// The types match the decls already at file scope in ov_SC01_077_jr_801734BC.c
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// (D_8011F7A8 u8, D_80078E78 u8[], D_8018A238 u16, D_8018A2CC u8[], D_8018A2E4 s32[],
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// D_800D43D4/4414/45D4 u8, D_800B9A13 u8, D_80126D20 s16, D_80126B58 s32,
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// func_800183E0(s32), func_801619D0(void*), func_80161A00/30/60(s32)); func_801775E0 is the
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// shared engine-core DEFINE later in the same TU, so it needs the forward decl below.
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#include "common.h"
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void func_80176734(s32 param_1)
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{
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extern u8 D_8011F7A8; /* st base ($s3) */
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extern u8 D_80078E78[]; /* cur base ($s4) */
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extern s16 D_801152BA;
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extern u8 D_8011F7B0; /* == *(u8 *)(st + 8), read absolutely (mixed addressing) */
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extern u8 D_80115214;
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extern u8 D_8018A2D8[];
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extern u16 D_8018A22A[];
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extern u16 D_8018A238;
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extern u8 D_8018A2CC[];
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extern s32 D_8018A2E4[];
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extern u8 D_800D43D4;
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extern u8 D_800D4414;
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extern u8 D_800D45D4;
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extern u8 D_800B9A13;
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extern s16 D_80126CE0;
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extern s16 D_80126D20;
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extern s32 D_80126B58;
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extern void func_800183E0(s32 a0);
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extern s32 func_801619D0(void *a0);
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extern s32 func_80161A00(s32 a0);
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extern s32 func_80161A30(s32 a0);
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extern s32 func_80161A60(s32 a0);
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extern void func_801775E0(s32 param_1, s32 param_2);
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s32 st, cach, flag, cur;
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register s32 chg __asm__("$21"); /* L7 */
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register s32 chg2 __asm__("$16"); /* L7 */
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s32 amp; /* $s0, disjoint from chg2 */
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register u16 tgt __asm__("$5"); /* L7 */
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s32 pv; /* L6: the param copy that owns $s6 */
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s32 ix; /* L6: block A's index, hoisted out of the block */
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u8 dum[8]; /* L5: dead frame slot (target .frame vars=8) */
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st = (s32)&D_8011F7A8;
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ix = ((param_1 << 16) >> 14) + st;
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pv = param_1;
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cach = st + 0x48;
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flag = st + 0xE0;
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cur = (s32)&(*(u8 *)D_80078E78);
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/* ---- block A: pulse byte ---- */
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{
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register s32 p __asm__("$5"); /* L7 */
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u8 *q;
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p = *(s32 *)(ix + 0x28);
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q = (u8 *)(p + 0x3C); /* L2: must live in the entry BB */
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if (D_801152BA != 0) {
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u8 b = D_8011F7B0; /* L1 */
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u8 v;
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if (b < 0x80) v = b - 0x80;
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else v = ~b - 0x80;
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q[4] = v;
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*(u8 *)(p + 4) = v;
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*(u8 *)(st + 8) = *(u8 *)(st + 8) + D_80115214;
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} else {
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*(u8 *)(p + 0x40) = 0x80;
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*(u8 *)(p + 4) = 0x80;
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}
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}
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/* ---- block B: 0x48 animation already running ---- */
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if (*(u8 *)(flag + 0x48) != 0) {
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register s32 pp __asm__("$5"); /* L7 */
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pp = *(s32 *)(((pv << 16) >> 14) + st + 0x28);
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*(u8 *)(pp + 0xD) = D_8018A2D8[*(u8 *)(flag + 0x48)];
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if (*(u8 *)(flag + 0x48) < 4) {
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*(u8 *)(flag + 0x48) = *(u8 *)(flag + 0x48) + 1;
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} else {
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u8 c = *(u8 *)(cach + 0x48);
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s32 q = *(s32 *)(((pv << 16) >> 14) + st + 0x28);
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s32 arg;
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if (c & 0x80) {
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*(u16 *)(q + 0x20) = D_8018A238;
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arg = (s32)&D_800D45D4;
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} else if (c != 0) {
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*(u16 *)(q + 0x20) = D_8018A22A[c];
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arg = D_8018A2E4[*(u8 *)(cach + 0x48)];
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} else {
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goto Lskip;
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}
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func_800183E0(arg);
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Lskip:
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if (*(u8 *)(flag + 0x48) == 5) {
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if (*(u8 *)(cach + 0x48) == 0) *(u8 *)(flag + 0x48) = 0;
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else *(u8 *)(flag + 0x48) = *(u8 *)(flag + 0x48) + 1;
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} else if (*(u8 *)(flag + 0x48) == 10) {
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*(u8 *)(flag + 0x48) = 0;
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} else {
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*(u8 *)(flag + 0x48) = *(u8 *)(flag + 0x48) + 1;
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}
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}
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/* ---- block C: 0x48 changed -> start the animation ---- */
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} else if (*(u8 *)(cach + 0x48) != *(u8 *)(cur + 0x48)) {
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register s32 pp __asm__("$5"); /* L7 */
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u8 k; /* L1: gives the `andi $v1,$v1,0xFF` index mask */
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if (*(u8 *)(cach + 0x48) == 0 && *(u8 *)(cur + 0x48) != 0)
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*(u8 *)(flag + 0x48) = 5;
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else
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*(u8 *)(flag + 0x48) = 0;
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*(u8 *)(cach + 0x48) = *(u8 *)(cur + 0x48);
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pp = *(s32 *)(((pv << 16) >> 14) + st + 0x28);
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k = *(u8 *)(flag + 0x48);
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*(u8 *)(flag + 0x48) = k + 1;
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*(u8 *)(pp + 0xD) = D_8018A2D8[k];
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}
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/* ---- block D: field 0x2E (equality-first: the ne-arm must be out of line) ---- */
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if (*(s16 *)(cach + 0x2E) == *(s16 *)(cur + 0x2E)) {
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if (*(s16 *)(flag + 0x2E) == 0) goto L9C0;
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*(s16 *)(flag + 0x2E) = 0;
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} else {
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*(s16 *)(cach + 0x2E) = *(s16 *)(cur + 0x2E);
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*(s16 *)(flag + 0x2E) = 1;
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}
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{
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s32 pp = *(s32 *)(((pv << 16) >> 14) + st + 0x28);
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s32 t = (s32)(*(u16 *)(cach + 0x2E) << 16);
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if (t != 0) *(u8 *)(pp + 0x49) = D_8018A2CC[t >> 20];
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else *(u8 *)(pp + 0x49) = 0xA0;
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}
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L9C0:
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/* ---- block E: field 0x1E sign flip ---- */
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{
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s32 fa = *(s16 *)(cach + 0x1E) & 0x8000;
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s32 fb = *(s16 *)(cur + 0x1E) & 0x8000;
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if (fa != fb) {
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s32 arg;
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if (fa != 0) {
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*(s16 *)(cach + 0x1E) = 0;
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arg = (s32)&D_800D43D4;
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} else {
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*(s16 *)(cach + 0x1E) = -0x8000;
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arg = (s32)&D_800D4414;
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}
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func_800183E0(arg);
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}
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}
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/* ---- block F: mode byte -> chg ---- */
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{
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u8 m = D_800B9A13; /* L1 */
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if (m != 3) { /* inverted: `chg = 0` belongs out of line */
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register s32 t __asm__("$2"); /* L3a: pin + 2 uses keeps `chg = t` alive */
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t = (*(u8 *)(st + 7) != m);
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chg = t;
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if (t != 0) *(u8 *)(st + 7) = m;
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} else {
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chg = 0;
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}
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}
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/* ---- block G: switch on cur[0x48] (cases 3/4/5 cross-jump onto one tail) ---- */
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amp = 0;
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switch (*(u8 *)(cur + 0x48)) {
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case 3:
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if (func_801619D0(&D_80126B58) != 0) amp = 0xFF;
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break;
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case 4:
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if (func_80161A00((s32)&D_80126B58) != 0) amp = 0xFF;
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break;
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case 5:
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if (func_80161A30((s32)&D_80126B58) != 0) amp = 0xFF;
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break;
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case 6:
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if (func_80161A60((s32)&D_80126B58) != 0) amp = 0xBA;
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break;
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}
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/* ---- block H: amp != 0 short-circuit ---- */
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{
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s32 av;
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av = amp;
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__asm__("" : "=r"(av) : "0"(av)); /* L3b: keeps the `move $v0,$s0` at the merge */
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if (av != 0) {
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*(u8 *)(flag + 0x47) = 1;
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*(u8 *)(cach + 0x4B) = *(u8 *)(cur + 0x48) | 0xF0;
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*(u8 *)(cach + 0x47) = ((s32)D_80126D20 << 7) / av;
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goto Ltail;
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}
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}
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if (*(u8 *)(cach + 0x4B) >= 0xF0) *(u8 *)(cach + 0x4B) = 0;
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/* ---- block I: target level + change flag. The lhu is unconditional (target loads
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both the signed and the unsigned view of D_80126CE0 up front). ---- */
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tgt = *(u16 *)&D_80126CE0;
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if (D_80126CE0 != 0) {
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u16 v; /* dies at the mask -> destructive `andi $v1,$v1` */
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register s32 t __asm__("$2");
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v = tgt;
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*(u8 *)(cach + 0x4B) = v;
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t = (*(u8 *)(cach + 0x47) != (v & 0xFF));
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__asm__("" : "=r"(t) : "0"(t)); /* L3b */
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chg2 = t;
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} else {
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u32 cv = *(u8 *)(cach + 0x47); /* L8: one load, two compares, no re-mask */
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tgt = *(u8 *)(cur + 0x47);
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chg2 = 0;
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if (cv != tgt || cv == 0x80) chg2 = 1;
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if (*(u8 *)(cur + 0x47) != 0 && *(u8 *)(cach + 0x4B) != 0) {
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*(u8 *)(cach + 0x4B) = 0;
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*(u8 *)(cach + 0x47) = *(u8 *)(cur + 0x47);
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}
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}
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/* ---- block J: nothing-changed fast path. The target re-tests chg after the flag load;
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the fence below is what stops cse from folding that second test away. ---- */
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{
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register s32 c __asm__("$3");
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c = chg;
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if (chg2 != 0) goto Lbig;
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if (c != 0) goto Lbig;
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if (*(u8 *)(flag + 0x47) == 0) goto Ltail;
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__asm__("" : "=r"(c) : "0"(c)); /* L3b */
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if (c == 0) goto Lzero;
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}
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Lbig:
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/* ---- block K: slew cach[0x47] toward tgt ---- */
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{
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u32 c = *(u8 *)(cach + 0x47);
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s32 sv = (s16)tgt; /* L8 */
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if ((s32)c < sv) {
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*(u8 *)(cach + 0x47) = tgt;
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} else {
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if (sv != 0) *(u8 *)(cach + 0x47) = c - 3; /* L4: store in BOTH arms */
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||||
else *(u8 *)(cach + 0x47) = c - 8;
|
||||
c = *(u8 *)(cach + 0x47); /* stays a real lbu because of L4 */
|
||||
if (c == 0 || c > 0x80) {
|
||||
*(u8 *)(cach + 0x47) = 0;
|
||||
*(u8 *)(cach + 0x4B) = 0;
|
||||
} else if ((s32)c < (s16)tgt) { /* fresh EBB -> the sll/sra is recomputed */
|
||||
*(u8 *)(cach + 0x47) = tgt;
|
||||
}
|
||||
}
|
||||
*(u8 *)(flag + 0x47) = 1;
|
||||
}
|
||||
goto Ltail;
|
||||
Lzero:
|
||||
*(u8 *)(flag + 0x47) = 0;
|
||||
Ltail:
|
||||
|
||||
/* ---- block L: tail. m+5 / m+9 are separate temps: `lhu + (m+5)`, not `(lhu + m) + 5`. ---- */
|
||||
{
|
||||
s32 b = ((pv << 16) >> 14) + st;
|
||||
s32 m = (*(u8 *)(st + 7) != 0) << 8;
|
||||
s32 m5 = m + 5;
|
||||
s32 m9 = m + 9;
|
||||
*(u16 *)(*(s32 *)(b + 0x28) + 0x32) = *(u16 *)(st + 0x12) + m5;
|
||||
func_801775E0(*(s32 *)(b + 0x28) + 0x64, (s16)(*(u16 *)(st + 0x12) + m9));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
DEFINE_func_80176D00() /* dedup: shared engine-core @0x80176D00 (src/shared) */
|
||||
|
||||
|
||||
Reference in New Issue
Block a user