mirror/BFM-decomp
1
0
Fork 0
mirror of https://github.com/Druthulu/BFM-decomp synced 2026-10-01 23:52:03 -04:00
Code Issues Packages Projects Releases Wiki Activity

feat(phase-29): func_8016AE5C family probe 3/3 banked

Browse Source
This commit is contained in:
Drew T
2026-07-27 12:21:57 -06:00
parent d4c4a4d563
commit 7804d75230
7 changed files with 159 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files
config/overlays.mk
+3
View File
@@ -146,6 +146,7 @@ build/src/ov_SC01_000/ov_SC01_000_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (
build/src/ov_SC01_000/ov_SC01_000_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28
build/src/ov_SC01_000/ov_SC01_000_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20
build/src/ov_SC01_000/ov_SC01_000_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20
build/src/ov_SC01_000/ov_SC01_000_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20
ov_SC01_000_CHECK_SHA := config/check.ov_SC01_000.sha
ov_SC01_000_SYMBOLS := config/symbols.ov_SC01_000.txt
ov_SC01_000_SIG := .run/sig.ov_SC01_000.jsonl
@@ -175,6 +176,7 @@ build/src/ov_SC01_001/ov_SC01_001_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (
build/src/ov_SC01_001/ov_SC01_001_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28
build/src/ov_SC01_001/ov_SC01_001_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20
build/src/ov_SC01_001/ov_SC01_001_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20
build/src/ov_SC01_001/ov_SC01_001_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20
ov_SC01_001_CHECK_SHA := config/check.ov_SC01_001.sha
ov_SC01_001_SYMBOLS := config/symbols.ov_SC01_001.txt
ov_SC01_001_SIG := .run/sig.ov_SC01_001.jsonl
@@ -494,6 +496,7 @@ build/src/ov_SC01_004/ov_SC01_004_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (
build/src/ov_SC01_004/ov_SC01_004_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28
build/src/ov_SC01_004/ov_SC01_004_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20
build/src/ov_SC01_004/ov_SC01_004_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20
build/src/ov_SC01_004/ov_SC01_004_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20
ov_SC01_004_CHECK_SHA := config/check.ov_SC01_004.sha
ov_SC01_004_SYMBOLS := config/symbols.ov_SC01_004.txt
ov_SC01_004_SIG := .run/sig.ov_SC01_004.jsonl
config/splat.ov_SC01_000.yaml
+1 -1
View File
@@ -149,7 +149,7 @@ segments:
- [0x7bce0, .rodata, ov_SC01_000_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
- [0x7bcfc, data, tail15]
- [0x7bd14, .rodata, ov_SC01_000_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
- [0x7bd34, data, tail16]
- [0x7bd54, data, tail16]
- [0x7bdb4, .rodata, ov_SC01_000_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
- [0x7bdc8, data, tail17]
- [0x7bf70, .rodata, ov_SC01_000_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
config/splat.ov_SC01_001.yaml
+1 -1
View File
@@ -150,7 +150,7 @@ segments:
- [0xc3db8, .rodata, ov_SC01_001_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
- [0xc3dd4, data, tail15]
- [0xc3dec, .rodata, ov_SC01_001_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
- [0xc3e0c, data, tail16]
- [0xc3e2c, data, tail16]
- [0xc3e8c, .rodata, ov_SC01_001_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
- [0xc3ea0, data, tail17]
- [0xc4048, .rodata, ov_SC01_001_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
config/splat.ov_SC01_004.yaml
+1 -1
View File
@@ -149,7 +149,7 @@ segments:
- [0x66198, .rodata, ov_SC01_004_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
- [0x661b4, data, tail15]
- [0x661cc, .rodata, ov_SC01_004_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
- [0x661ec, data, tail16]
- [0x6620c, data, tail16]
- [0x6626c, .rodata, ov_SC01_004_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
- [0x66280, data, tail17]
- [0x66428, .rodata, ov_SC01_004_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
src/ov_SC01_000/ov_SC01_000_jr_8016AB6C.c
+51 -1
View File
@@ -2013,7 +2013,57 @@ lout:
}
INCLUDE_ASM("asm/ov_SC01_000/nonmatchings/ov_SC01_000_jr_8016AB6C", func_8016AE5C);
extern void func_8016B234();
extern void func_800D22E4(s32 a0);
void func_8016AE5C(s32 param_1) {
s32 sp;
sp = *(s32 *)(param_1 + 0x20);
if (*(u32 *)(param_1 + 0x2C) < 6) {
func_8016B234();
}
switch (*(u32 *)(param_1 + 0x2C)) {
case 0:
*(s16 *)(param_1 + 0xA) -= *(s32 *)(param_1 + 0x1C);
*(s32 *)(param_1 + 0x1C) = *(s32 *)(param_1 + 0x1C) - 1;
if (*(s32 *)(param_1 + 0x1C) != 0) {
if ((*(s32 *)(param_1 + 0x1C) & 3) == 1) {
*(s16 *)(param_1 + 0x26) += 1;
}
return;
}
*(s16 *)(param_1 + 0x24) = 0xFF;
*(s32 *)(param_1 + 0x1C) = 8;
*(s16 *)(param_1 + 2) += 1;
return;
case 1:
case 5:
func_800D22E4(param_1);
*(s32 *)(param_1 + 0x14) += 0x18000;
case 2:
case 3:
case 4:
case 6:
case 7:
*(s16 *)(param_1 + 0xA) -= *(s32 *)(param_1 + 0x1C);
*(s32 *)(param_1 + 0x1C) = *(s32 *)(param_1 + 0x1C) - 1;
if (*(s32 *)(param_1 + 0x1C) == 0) {
if (*(u32 *)(param_1 + 0x2C) < 6) {
*(s16 *)(param_1 + 0x24) = 0xC0;
*(s32 *)(param_1 + 0x1C) = 8;
} else {
*(u8 *)(sp + 0x26) = 0xC0;
*(u8 *)(sp + 0x25) = 0xC0;
*(u8 *)(sp + 0x24) = 0xC0;
*(s32 *)(param_1 + 0x1C) = 0xC;
}
*(s16 *)(param_1 + 2) += 1;
}
break;
}
}
DEFINE_func_8016AFB0() /* dedup: shared engine-core @0x8016AFB0 (src/shared) */
src/ov_SC01_001/ov_SC01_001_jr_8016AB6C.c
+51 -1
View File
@@ -2011,7 +2011,57 @@ lout:
}
INCLUDE_ASM("asm/ov_SC01_001/nonmatchings/ov_SC01_001_jr_8016AB6C", func_8016AE5C);
extern void func_8016B234();
extern void func_800D22E4(s32 a0);
void func_8016AE5C(s32 param_1) {
s32 sp;
sp = *(s32 *)(param_1 + 0x20);
if (*(u32 *)(param_1 + 0x2C) < 6) {
func_8016B234();
}
switch (*(u32 *)(param_1 + 0x2C)) {
case 0:
*(s16 *)(param_1 + 0xA) -= *(s32 *)(param_1 + 0x1C);
*(s32 *)(param_1 + 0x1C) = *(s32 *)(param_1 + 0x1C) - 1;
if (*(s32 *)(param_1 + 0x1C) != 0) {
if ((*(s32 *)(param_1 + 0x1C) & 3) == 1) {
*(s16 *)(param_1 + 0x26) += 1;
}
return;
}
*(s16 *)(param_1 + 0x24) = 0xFF;
*(s32 *)(param_1 + 0x1C) = 8;
*(s16 *)(param_1 + 2) += 1;
return;
case 1:
case 5:
func_800D22E4(param_1);
*(s32 *)(param_1 + 0x14) += 0x18000;
case 2:
case 3:
case 4:
case 6:
case 7:
*(s16 *)(param_1 + 0xA) -= *(s32 *)(param_1 + 0x1C);
*(s32 *)(param_1 + 0x1C) = *(s32 *)(param_1 + 0x1C) - 1;
if (*(s32 *)(param_1 + 0x1C) == 0) {
if (*(u32 *)(param_1 + 0x2C) < 6) {
*(s16 *)(param_1 + 0x24) = 0xC0;
*(s32 *)(param_1 + 0x1C) = 8;
} else {
*(u8 *)(sp + 0x26) = 0xC0;
*(u8 *)(sp + 0x25) = 0xC0;
*(u8 *)(sp + 0x24) = 0xC0;
*(s32 *)(param_1 + 0x1C) = 0xC;
}
*(s16 *)(param_1 + 2) += 1;
}
break;
}
}
DEFINE_func_8016AFB0() /* dedup: shared engine-core @0x8016AFB0 (src/shared) */
src/ov_SC01_004/ov_SC01_004_jr_8016AB6C.c
+51 -1
View File
@@ -2011,7 +2011,57 @@ lout:
}
INCLUDE_ASM("asm/ov_SC01_004/nonmatchings/ov_SC01_004_jr_8016AB6C", func_8016AE5C);
extern void func_8016B234();
extern void func_800D22E4(s32 a0);
void func_8016AE5C(s32 param_1) {
s32 sp;
sp = *(s32 *)(param_1 + 0x20);
if (*(u32 *)(param_1 + 0x2C) < 6) {
func_8016B234();
}
switch (*(u32 *)(param_1 + 0x2C)) {
case 0:
*(s16 *)(param_1 + 0xA) -= *(s32 *)(param_1 + 0x1C);
*(s32 *)(param_1 + 0x1C) = *(s32 *)(param_1 + 0x1C) - 1;
if (*(s32 *)(param_1 + 0x1C) != 0) {
if ((*(s32 *)(param_1 + 0x1C) & 3) == 1) {
*(s16 *)(param_1 + 0x26) += 1;
}
return;
}
*(s16 *)(param_1 + 0x24) = 0xFF;
*(s32 *)(param_1 + 0x1C) = 8;
*(s16 *)(param_1 + 2) += 1;
return;
case 1:
case 5:
func_800D22E4(param_1);
*(s32 *)(param_1 + 0x14) += 0x18000;
case 2:
case 3:
case 4:
case 6:
case 7:
*(s16 *)(param_1 + 0xA) -= *(s32 *)(param_1 + 0x1C);
*(s32 *)(param_1 + 0x1C) = *(s32 *)(param_1 + 0x1C) - 1;
if (*(s32 *)(param_1 + 0x1C) == 0) {
if (*(u32 *)(param_1 + 0x2C) < 6) {
*(s16 *)(param_1 + 0x24) = 0xC0;
*(s32 *)(param_1 + 0x1C) = 8;
} else {
*(u8 *)(sp + 0x26) = 0xC0;
*(u8 *)(sp + 0x25) = 0xC0;
*(u8 *)(sp + 0x24) = 0xC0;
*(s32 *)(param_1 + 0x1C) = 0xC;
}
*(s16 *)(param_1 + 2) += 1;
}
break;
}
}
DEFINE_func_8016AFB0() /* dedup: shared engine-core @0x8016AFB0 (src/shared) */