feat(decomp): parallel gate — 2 fns across 2 binaries (6 workers)

ov_SC05_010    func_8017F5B8
  ov_SC03_024    func_801830A8
This commit is contained in:
Drew T
2026-09-02 18:57:20 -06:00
parent 7c2342f87f
commit 7ce27c0d1f
6 changed files with 3464 additions and 144 deletions
+2 -2
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@@ -1657,7 +1657,7 @@ ov_SC03_024_ELF := $(ov_SC03_024_OUT).elf
ov_SC03_024_MAPFILE := $(ov_SC03_024_OUT).map
ov_SC03_024_LD_SCRIPT := $(ov_SC03_024_OUT).ld
ov_SC03_024_SPLAT_YAML := config/splat.ov_SC03_024.yaml
ov_SC03_024_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_024.o,ov_SC03_024_jr_8012ACE0.o,tail2.data.o,ov_SC03_024_jr_80135888.o,tail3.data.o,ov_SC03_024_jr_80135A4C.o,tail4.data.o,ov_SC03_024_jr_80135D20.o,tail5.data.o,ov_SC03_024_jr_801380E0.o,ov_SC03_024_o0c.o,tail6.data.o,ov_SC03_024_jr_8013F350.o,tail7.data.o,ov_SC03_024_jr_8013FFD8.o,tail8.data.o,ov_SC03_024_jr_80140608.o,tail9.data.o,ov_SC03_024_jr_8015444C.o,ov_SC03_024_jr_80154C24.o,ov_SC03_024_jr_801588CC.o,ov_SC03_024_jr_80159C84.o,tail10.data.o,ov_SC03_024_jr_8015A3C8.o,tail11.data.o,ov_SC03_024_jr_8015AE2C.o,tail12.data.o,ov_SC03_024_jr_8015C32C.o,tail13.data.o,ov_SC03_024_jr_8016AB6C.o,tail14.data.o,ov_SC03_024_jr_80171B4C.o,ov_SC03_024_jr_801734BC.o,tail15.data.o,ov_SC03_024_jr_801789AC.o,ov_SC03_024_jr_80178D40.o,tail16.data.o,ov_SC03_024_jr_8017A4AC.o,tail17.data.o,ov_SC03_024_jr_8017AE2C.o,ov_SC03_024_jr_8017DF84.o,tail18.data.o,ov_SC03_024_jr_80183BF8.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve
ov_SC03_024_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_024.o,ov_SC03_024_jr_8012ACE0.o,tail2.data.o,ov_SC03_024_jr_80135888.o,tail3.data.o,ov_SC03_024_jr_80135A4C.o,tail4.data.o,ov_SC03_024_jr_80135D20.o,tail5.data.o,ov_SC03_024_jr_801380E0.o,ov_SC03_024_o0c.o,tail6.data.o,ov_SC03_024_jr_8013F350.o,tail7.data.o,ov_SC03_024_jr_8013FFD8.o,tail8.data.o,ov_SC03_024_jr_80140608.o,tail9.data.o,ov_SC03_024_jr_8015444C.o,ov_SC03_024_jr_80154C24.o,ov_SC03_024_jr_801588CC.o,ov_SC03_024_jr_80159C84.o,tail10.data.o,ov_SC03_024_jr_8015A3C8.o,tail11.data.o,ov_SC03_024_jr_8015AE2C.o,tail12.data.o,ov_SC03_024_jr_8015C32C.o,tail13.data.o,ov_SC03_024_jr_8016AB6C.o,tail14.data.o,ov_SC03_024_jr_80171B4C.o,ov_SC03_024_jr_801734BC.o,tail15.data.o,ov_SC03_024_jr_801789AC.o,ov_SC03_024_jr_80178D40.o,tail16.data.o,ov_SC03_024_jr_8017A4AC.o,tail17.data.o,ov_SC03_024_jr_8017AE2C.o,ov_SC03_024_jr_8017DF84.o,tail18.data.o,ov_SC03_024_jr_801830A8.o,ov_SC03_024_jr_80183BF8.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve
build/src/ov_SC03_024/ov_SC03_024.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14
build/src/ov_SC03_024/ov_SC03_024_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0
build/src/ov_SC03_024/ov_SC03_024_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18
@@ -3903,7 +3903,7 @@ build/src/ov_SC05_010/ov_SC05_010_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (
build/src/ov_SC05_010/ov_SC05_010_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20
build/src/ov_SC05_010/ov_SC05_010_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20
build/src/ov_SC05_010/ov_SC05_010_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178
build/src/ov_SC05_010/ov_SC05_010_jr_8017C8D0.o: JTBL_PADS := 0,0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x48
build/src/ov_SC05_010/ov_SC05_010_jr_8017C8D0.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x48,+0x60
build/src/ov_SC05_010/ov_SC05_010_jr_80181CDC.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18
build/src/ov_SC05_010/ov_SC05_010_o0c.o: JTBL_PADS := 0,4,4,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x38,+0xa8,+0x118
ov_SC05_010_CHECK_SHA := config/check.ov_SC05_010.sha
+2
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@@ -121,6 +121,7 @@ segments:
- [0x52354, c, ov_SC03_024_jr_8017A4AC]
- [0x52cd4, c, ov_SC03_024_jr_8017AE2C]
- [0x55e2c, c, ov_SC03_024_jr_8017DF84]
- [0x5af50, c, ov_SC03_024_jr_801830A8]
- [0x5baa0, c, ov_SC03_024_jr_80183BF8]
- [0x5ed68, data, tail]
- [0x96ab0, .rodata, ov_SC03_024] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
@@ -165,6 +166,7 @@ segments:
- [0x97bd0, .rodata, ov_SC03_024_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
- [0x97c10, .rodata, ov_SC03_024_jr_8017DF84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
- [0x97c30, data, tail18]
- [0x97c3c, .rodata, ov_SC03_024_jr_801830A8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
- [0x97ccc, .rodata, ov_SC03_024_jr_80183BF8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
- [0x97d14, data, tail19]
- [0x996F4, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word)
+1 -1
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@@ -167,7 +167,7 @@ segments:
- [0x9d7f8, .rodata, ov_SC05_010_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
- [0x9d80c, data, tail18]
- [0x9d944, .rodata, ov_SC05_010_jr_8017C8D0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
- [0x9d9a4, data, tail19]
- [0x9d9b8, data, tail19]
- [0x9d9d4, .rodata, ov_SC05_010_jr_80180F84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
- [0x9d9f4, .rodata, ov_SC05_010_jr_80181CDC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
- [0x9da28, data, tail20]
-140
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@@ -6402,143 +6402,3 @@ extern s32 D_801C13A0;
void func_80183094(void) {
D_801C13A0 = 1;
}
INCLUDE_ASM("asm/ov_SC03_024/nonmatchings/ov_SC03_024_jr_8017DF84", func_801830A8);
extern void (*D_8018B740[])(void);
void func_80183890(void *a0) {
D_8018B740[*(u16 *)((s32)a0 + 0x2)]();
}
#define gte_SetRotMatrix(r0) __asm__ volatile ( \
"lw $12, 0( %0 );" \
"lw $13, 4( %0 );" \
"ctc2 $12, $0;" \
"ctc2 $13, $1;" \
"lw $12, 8( %0 );" \
"lw $13, 12( %0 );" \
"lw $14, 16( %0 );" \
"ctc2 $12, $2;" \
"ctc2 $13, $3;" \
"ctc2 $14, $4" \
: \
: "r"( r0 ) \
: "$12", "$13", "$14" )
#define gte_SetTransMatrix(r0) __asm__ volatile ( \
"lw $12, 20( %0 );" \
"lw $13, 24( %0 );" \
"ctc2 $12, $5;" \
"lw $14, 28( %0 );" \
"ctc2 $13, $6;" \
"ctc2 $14, $7" \
: \
: "r"( r0 ) \
: "$12", "$13", "$14" )
extern void (*D_8018B758)(void);
extern u8 D_800AF648;
extern s32 D_800A651C;
extern short D_800B9A02;
extern void *func_80010A08(s32);
extern s32 func_8005A600(s32, s32, s32, s32, s32);
extern s32 GetTPage(s32, s32, s32, s32);
extern void func_8004914C(void *a0);
extern void func_800491AC(void *a0);
extern void RotTransSV(void *a0, void *a1, void *a2);
extern s32 RotTransPers(s32, s32, s32 *, s32 *);
extern s32 AddPrim(s32, void *);
void func_801838CC(s32 a0)
{
s32 v[2];
s32 flg;
s32 sxy;
s32 otz;
s32 m;
s8 *pr;
s32 otp;
u16 *q;
s32 bidx;
s16 w;
s32 t2;
s32 t;
m = *(s32 *)(a0 + 0x20) + 0x34;
gte_SetRotMatrix(m);
gte_SetTransMatrix(m);
RotTransSV(&D_8018B758, v, &flg);
func_8004914C(&D_800AF648);
func_800491AC(&D_800AF648);
if (RotTransPers((s32)v, (s32)&sxy, &otz, &flg) > 0 && flg >= 0) {
bidx = (*(u16 *)&D_800B9A02 << 2) + *(u16 *)&D_800B9A02;
otp = *(s32 *)((u8 *)&D_800A651C + (bidx << 2)) + 4;
pr = (s8 *)func_80010A08(0x20);
if (pr != NULL) {
t = GetTPage(0, 1, 0, 0);
func_8005A600((s32)pr, 0, 0, t & 0xFFFF, 0);
*(u32 *)(pr + 0x10) = 0xFF00;
*(u8 *)(pr + 0xF) = 4;
*(u8 *)(pr + 0x13) = 0x22;
*(u16 *)(pr + 0x14) = *(u16 *)&sxy;
*(u16 *)(pr + 0x16) = *((u16 *)&sxy + 1);
__asm__ ("");
t2 = *(u16 *)(pr + 0x14) + (*(s32 *)(a0 + 0x1C) << 4);
*(u16 *)(pr + 0x18) = t2;
w = t2;
__asm__ ("");
q = (u16 *)(pr + 0xC);
if ((s16)t2 >= 0xB1) {
*(u16 *)(pr + 0x18) = 0xA1;
*(u16 *)(pr + 0x1C) = 0xA1;
*(s32 *)(a0 + 0x1C) -= 1;
} else {
*(u16 *)(pr + 0x1C) = w;
}
q[7] = q[5] - *(s32 *)(a0 + 0x1C);
q[9] = q[5] + ((((*(s32 *)(a0 + 0x1C) << 2) + *(s32 *)(a0 + 0x1C)) << 1));
AddPrim(otp, q);
AddPrim(otp, pr);
}
}
}
void func_80183ACC(s32 a0)
{
s32 s0 = a0;
u16 state;
s16 t;
state = *(u16 *)((s32)s0 + 0x34);
switch (state) {
case 0:
if (*(s16 *)((s32)s0 + 0x98) == 0) {
__asm__ __volatile__("" ::: "memory");
*(u16 *)((s32)s0 + 0x34) = state + 1;
func_8002D4C8(0x948, 0);
func_8012C658(0x383, 0, s0);
}
break;
case 1:
*(s32 *)((s32)s0 + 0x1C) += 1;
t = *(u16 *)((s32)s0 + 0xFC) + 1;
*(u16 *)((s32)s0 + 0xFC) = t;
if (t == 0x28) {
*(s32 *)(*(s32 *)((s32)s0 + 0x64) + 0xCC) = func_8012C588(0x308, s0);
func_8002D4C8(0x9CA, 0);
*(u16 *)((s32)s0 + 0x34) = *(u16 *)((s32)s0 + 0x34) + 1;
}
break;
case 2:
t = *(u16 *)((s32)s0 + 0xFC) - 1;
*(u16 *)((s32)s0 + 0xFC) = t;
if (t == 0) {
*(u16 *)((s32)s0 + 0x34) = *(u16 *)((s32)s0 + 0x34) + 1;
func_8002D4C8(4, 0x948);
}
break;
}
}
File diff suppressed because it is too large Load Diff
+130 -1
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@@ -4419,7 +4419,136 @@ void func_8017F15C(s32 param_1)
}
INCLUDE_ASM("asm/ov_SC05_010/nonmatchings/ov_SC05_010_jr_8017C8D0", func_8017F5B8);
void func_8017F5B8(s32 param_1)
{
extern void func_8002D4C8(s32 a0, s32 a1);
extern void func_8012A828(s32 a0, void *a1);
extern s32 func_8012C588(s32 a0, s32 a1);
extern void func_8012C218(void *a0);
extern s32 func_80135888(s32 a0, s32 a1, s32 a2, s32 a3);
extern void func_8012F568(s32 a0, s32 a1, s32 a2, s32 a3, s32 a4, s32 a5);
extern void func_800599B8(void *a0, void *a1);
extern u8 D_801152A8[];
extern u16 D_80126B66;
extern s32 *D_80126B78;
extern s32 *D_80126B90;
extern u8 D_80192480[];
extern u8 D_80192488[];
extern u8 D_80192480_b[] __asm__("D_80192480");
extern u8 D_80192488_b[] __asm__("D_80192488");
extern s32 D_801A33AC;
extern u8 D_801A35FC[];
extern u16 D_801A3C44;
extern s32 D_801A3D94;
extern u8 D_801A3E2C[];
extern void *D_801C39FC[];
extern u8 *D_801C7E60[];
extern s32 D_801C7E64;
extern s32 D_801C7E64_b __asm__("D_801C7E64");
extern s32 D_801C7E78;
u16 sv0[4];
u16 sv1[4];
s32 q;
s32 r;
s32 bx;
s32 z;
s32 t2;
s32 by;
s16 c;
u8 t;
switch (*(u16 *)(param_1 + 0x34)) {
case 0:
c = *(u16 *)(param_1 + 0x84) - 1;
*(s16 *)(param_1 + 0x84) = c;
if (c == 0) {
func_8002D4C8(0x89B, 0);
}
if (*(s16 *)(param_1 + 0x98) == 0) {
func_8012A828(param_1, &D_801A35FC);
*(s16 *)(param_1 + 0x34) = 1;
D_801C7E64 = func_8012C588(0x2EC, param_1);
if (D_801C7E64 != 0) {
*(s16 *)(D_801C7E64_b + 6) = sv0[0] + 0x10;
}
func_8002D4C8(0x89C, 0);
}
break;
case 1:
if (*(u16 *)(param_1 + 0x72) & 0x4000) {
func_8012A828(param_1, &D_801A3C44);
t2 = D_801C7E78;
*(s16 *)(param_1 + 0x34) = 2;
*(u8 *)(param_1 + 0xC2) = 0;
*(s32 *)(param_1 + 0x1C) = 3 - t2;
if (D_801C7E64 != 0) {
func_8012C218((void *)D_801C7E64);
}
} else {
q = *(s32 *)(*(s32 *)(param_1 + 0x20) + 0x20);
q += 0x24;
bx = *(u16 *)(param_1 + 0x6) + *(u16 *)(q + 0x0);
z = D_80126B66;
sv0[0] = bx + 0x20;
by = *(u16 *)(param_1 + 0xA) + *(u16 *)(q + 0x2);
sv1[0] = bx + 0x10;
sv1[2] = z;
sv0[2] = z;
sv0[1] = by;
sv1[1] = by;
if (D_801C7E64 != 0) {
*(s16 *)(D_801C7E64_b + 6) = bx + 0x30;
}
*(s32 *)(param_1 + 0x1C) = *(s32 *)(param_1 + 0x1C) + 1;
if ((*(s32 *)(param_1 + 0x1C) & 1) == 0) {
r = func_8012C588(0x2EB, param_1);
if (r != 0) {
*(s16 *)(r + 0x6) = *(u16 *)(param_1 + 0x6) + *(u16 *)(q + 0x0);
*(s16 *)(r + 0xA) = *(u16 *)(param_1 + 0xA) + *(u16 *)(q + 0x2);
*(s16 *)(r + 0xE) = *(u16 *)(param_1 + 0xE) + *(u16 *)(q + 0x4);
*(s16 *)(*(s32 *)(r + 0x20) + 0x10) = *(u16 *)(q + 0x6);
*(s16 *)(*(s32 *)(r + 0x20) + 0x12) = *(u16 *)(q + 0x8);
*(s16 *)(*(s32 *)(r + 0x20) + 0x14) = *(u16 *)(q + 0xA);
}
}
if (func_80135888((s32)D_80126B78, (s32)D_80126B90, (s32)sv0, (s32)sv1) != 0) {
func_8012F568(1, 0x4004, 0x400, 0x30, (s32)sv1, (s32)D_801152A8);
}
}
break;
case 2:
if (*(s16 *)(param_1 + 0x98) == 0) {
func_8012A828(param_1, &D_801A3E2C);
*(s16 *)(param_1 + 0x34) = 3;
}
break;
case 3:
t = (*(u8 *)(param_1 + 0xC2) + 2) & 0xF;
*(u8 *)(param_1 + 0xC2) = t;
func_800599B8(D_80192480, D_801C39FC[t]);
func_800599B8(D_80192488, D_801C39FC[*(u8 *)(param_1 + 0xC2) + 1]);
if (*(u16 *)(param_1 + 0x72) & 0x4000) {
if (--*(s32 *)(param_1 + 0x1C) == 0) {
*(s16 *)(param_1 + 0x34) = 4;
func_8012A828(param_1, &D_801A3D94);
*(u8 *)(param_1 + 0xC2) = 0;
func_800599B8(D_80192480_b, D_801C39FC[*(u8 *)(param_1 + 0xC2)]);
func_800599B8(D_80192488_b, D_801C39FC[*(u8 *)(param_1 + 0xC2) + 1]);
}
}
break;
case 4:
if (*(s16 *)(param_1 + 0x98) == 0) {
func_8012A828(param_1, &D_801A33AC);
*(s16 *)(param_1 + 0x2) = 1;
*(s32 *)(param_1 + 0x1C) = 0x3C;
*(s16 *)(D_801C7E60[0] + 0xAE) = -1;
}
break;
}
}
#include "common.h"