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feat(decomp): main lane m15 — 16 banked

Browse Source 
One clean whole-EXE rebuild verified the batch (gate_main), and main re-checked
BYTE-IDENTICAL against config/check.us.sha before anything was credited.

  FGO_05_OBJ_64
  SYS_OBJ_1FF4
  VM_NOWON_OBJ_1C0
  func_800123F0
  func_8001404C
  func_80016ED4
  func_8001739C
  func_800178C8
  func_8001BFF8
  func_80028FDC
  func_8002A748
  func_80038308
  func_80041400
  func_8005D538
  func_8005E3AC
  func_8005EA34
This commit is contained in:
Drew T
2026-08-25 03:18:47 -06:00
parent 10dadb6c1c
commit 8a5760450a
5 changed files with 410 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/800.c
+147 -9
View File
@@ -230,7 +230,105 @@ typedef struct {
s32 unk0C;
} Rsc16; /* 0x10 */
INCLUDE_ASM("asm/nonmatchings/800", func_800123F0);
extern s32 func_8004787C(s32 angle);
extern s32 func_80047948(s32 angle);
extern void func_8001282C();
void func_800123F0(s32 param_1, s32 param_2)
{
s32 s0;
s32 s1;
s32 cos_val;
s32 sin_val;
register s32 v1 __asm__("$3");
s16 matrix[16];
s1 = (s32)param_1;
s0 = param_2;
sin_val = func_8004787C(s0);
cos_val = func_80047948(s0);
/* Build Z-rotation matrix on stack */
v1 = -sin_val;
*(s16 *)((s32)matrix + 0x00) = cos_val;
*(s16 *)((s32)matrix + 0x08) = cos_val;
*(s16 *)((s32)matrix + 0x02) = v1;
*(s16 *)((s32)matrix + 0x04) = 0;
*(s16 *)((s32)matrix + 0x06) = sin_val;
*(s16 *)((s32)matrix + 0x0A) = 0;
*(s16 *)((s32)matrix + 0x0C) = 0;
*(s16 *)((s32)matrix + 0x0E) = 0;
*(s16 *)((s32)matrix + 0x10) = 0x1000;
__asm__ __volatile__ (
"lw $12, 0(%0);"
"lw $13, 4(%0);"
"ctc2 $12, $0;"
"ctc2 $13, $1;"
"lw $12, 8(%0);"
"lw $13, 12(%0);"
"lw $14, 16(%0);"
"ctc2 $12, $2;"
"ctc2 $13, $3;"
"ctc2 $14, $4;"
"addiu $2, $sp, 16;"
"lhu $12, 0($2);"
"lhu $13, 6($2);"
"lhu $14, 12($2);"
"mtc2 $12, $9;"
"mtc2 $13, $10;"
"mtc2 $14, $11;"
"nop;"
"nop;"
"mvmva 1, 0, 3, 3, 0;"
"mfc2 $12, $9;"
"mfc2 $13, $10;"
"mfc2 $14, $11;"
"sh $12, 0(%0);"
"sh $13, 6(%0);"
"sh $14, 12(%0);"
"addiu $2, $sp, 18;"
"lhu $12, 0($2);"
"lhu $13, 6($2);"
"lhu $14, 12($2);"
"mtc2 $12, $9;"
"mtc2 $13, $10;"
"mtc2 $14, $11;"
"nop;"
"nop;"
"mvmva 1, 0, 3, 3, 0;"
"addiu $2, %0, 2;"
"mfc2 $12, $9;"
"mfc2 $13, $10;"
"mfc2 $14, $11;"
"sh $12, 0($2);"
"sh $13, 6($2);"
"sh $14, 12($2);"
"addiu $2, $sp, 20;"
"lhu $12, 0($2);"
"lhu $13, 6($2);"
"lhu $14, 12($2);"
"mtc2 $12, $9;"
"mtc2 $13, $10;"
"mtc2 $14, $11;"
"nop;"
"nop;"
"mvmva 1, 0, 3, 3, 0;"
"addiu $2, %0, 4;"
"mfc2 $12, $9;"
"mfc2 $13, $10;"
"mfc2 $14, $11;"
"sh $12, 0($2);"
"sh $13, 6($2);"
"sh $14, 12($2)"
:
: "r"(s1)
: "$12", "$13", "$14", "$2"
);
func_8001282C(s1);
}
extern s32 func_8004787C(s32 angle);
extern s32 func_80047948(s32 angle);
@@ -717,7 +815,11 @@ INCLUDE_ASM("asm/nonmatchings/800", func_80014004);
INCLUDE_ASM("asm/nonmatchings/800", func_80014028);
INCLUDE_ASM("asm/nonmatchings/800", func_8001404C);
void func_8001404C(s32 *a0, s32 *a1) {
*(u16 *)((s32)a0 + 0x4) = *(u16 *)((s32)a1 + 0x0);
*(u16 *)((s32)a0 + 0xA) = *(u16 *)((s32)a1 + 0x2);
*(u16 *)((s32)a0 + 0x10) = *(u16 *)((s32)a1 + 0x4);
}
void func_80014070(void* a0, void* a1)
{
@@ -3203,7 +3305,10 @@ void func_80016D78(S16D78 *arg0, s32 arg1)
INCLUDE_ASM("asm/nonmatchings/800", func_80016EB0);
INCLUDE_ASM("asm/nonmatchings/800", func_80016ED4);
void func_80016ED4(void *arg0)
{
func_80016F18(arg0, 0, 0);
}
INCLUDE_ASM("asm/nonmatchings/800", func_80016EF8);
@@ -3518,7 +3623,10 @@ void func_80017294(Src_80017294 *arg0, s32 arg1)
}
}
INCLUDE_ASM("asm/nonmatchings/800", func_8001739C);
void func_8001739C(void *arg0)
{
func_800173DC(arg0, 0);
}
INCLUDE_ASM("asm/nonmatchings/800", func_800173BC);
@@ -3801,7 +3909,10 @@ void func_80017778(Src_80017778 *arg0, s32 arg1, s32 arg2)
}
}
INCLUDE_ASM("asm/nonmatchings/800", func_800178C8);
void func_800178C8(void *arg0)
{
func_80017930(arg0, 0, 1);
}
void func_800178EC(s32 a0) {
func_80017930(a0, 0, 0);
@@ -7041,7 +7152,11 @@ s32 func_8001BFE8(void) {
return D_800747D8;
}
INCLUDE_ASM("asm/nonmatchings/800", func_8001BFF8);
extern s32 D_800747D8;
s32 func_8001BFF8(void) {
return D_800747D8 = 1;
}
extern u8 D_800B9A11;
@@ -12472,7 +12587,11 @@ INCLUDE_ASM("asm/nonmatchings/800", func_80028F98);
INCLUDE_ASM("asm/nonmatchings/800", func_80028FBC);
INCLUDE_ASM("asm/nonmatchings/800", func_80028FDC);
extern void func_800291A0(s32, s32);
void func_80028FDC(s32 a0) {
func_800291A0(0x2C, a0 & 0xFF);
}
INCLUDE_ASM("asm/nonmatchings/800", func_80029000);
@@ -13162,7 +13281,12 @@ s32 func_8002A738(void) {
return D_80078F00;
}
INCLUDE_ASM("asm/nonmatchings/800", func_8002A748);
extern s32 D_80078EFC;
extern u16 D_80063900[][8];
s32 func_8002A748(void) {
return D_80063900[D_80078EFC][0];
}
extern s32 D_80078EFC;
extern u16 D_80063902[][8];
@@ -18659,7 +18783,21 @@ s32 func_80038210(s32 a0, s16 a1, s32 a2)
return -1;
}
INCLUDE_ASM("asm/nonmatchings/800", func_80038308);
extern u8 D_800B9ED2[];
extern u8 D_800B9CD8[];
typedef s32 a32;
void func_80038308(s16 a0)
{
register a32 arg0 asm("$4");
s32 offset;
offset = arg0 * 127;
offset = offset * 4;
D_800B9ED2[offset] = 1;
func_80038908(&D_800B9CD8[offset]);
}
extern u8 D_800B9ECA[];
src/800b_5.c
+83 -1
View File
@@ -30,7 +30,89 @@ INCLUDE_ASM("asm/nonmatchings/800b_5", FGO_04_OBJ_64);
INCLUDE_ASM("asm/nonmatchings/800b_5", RotMatrixY);
INCLUDE_ASM("asm/nonmatchings/800b_5", FGO_05_OBJ_64);
__asm__(".text\n.align 2\n.globl FGO_05_OBJ_64\n.ent\tFGO_05_OBJ_64\n"
"FGO_05_OBJ_64:\n.frame $sp,0,$31\n"
".set\tnoreorder\n"
"lh $t2, 0($a1)\n"
"lh $t5, 12($a1)\n"
"multu $t0, $t2\n"
"lh $t3, 2($a1)\n"
"lh $t6, 14($a1)\n"
"mflo $t8\n"
"lh $t4, 4($a1)\n"
"lh $t7, 16($a1)\n"
"multu $t1, $t5\n"
"nop\n"
"nop\n"
"mflo $t9\n"
"subu $t9, $t8, $t9\n"
"sra $t8, $t9, 12\n"
"multu $t0, $t3\n"
"sh $t8, 0($a1)\n"
"nop\n"
"mflo $t8\n"
"nop\n"
"nop\n"
"multu $t1, $t6\n"
"nop\n"
"nop\n"
"mflo $t9\n"
"subu $t9, $t8, $t9\n"
"sra $t8, $t9, 12\n"
"multu $t0, $t4\n"
"sh $t8, 2($a1)\n"
"nop\n"
"mflo $t8\n"
"nop\n"
"nop\n"
"multu $t1, $t7\n"
"nop\n"
"nop\n"
"mflo $t9\n"
"subu $t9, $t8, $t9\n"
"sra $t8, $t9, 12\n"
"multu $t1, $t2\n"
"sh $t8, 4($a1)\n"
"nop\n"
"mflo $t8\n"
"nop\n"
"nop\n"
"multu $t0, $t5\n"
"nop\n"
"nop\n"
"mflo $t9\n"
"addu $t9, $t8, $t9\n"
"sra $t8, $t9, 12\n"
"multu $t1, $t3\n"
"sh $t8, 12($a1)\n"
"nop\n"
"mflo $t8\n"
"nop\n"
"nop\n"
"multu $t0, $t6\n"
"nop\n"
"nop\n"
"mflo $t9\n"
"addu $t9, $t8, $t9\n"
"sra $t8, $t9, 12\n"
"multu $t1, $t4\n"
"sh $t8, 14($a1)\n"
"nop\n"
"mflo $t8\n"
"nop\n"
"nop\n"
"multu $t0, $t7\n"
"nop\n"
"nop\n"
"mflo $t9\n"
"addu $t9, $t8, $t9\n"
"sra $t8, $t9, 12\n"
"sh $t8, 16($a1)\n"
"jr $ra\n"
"nop\n"
".set\treorder\n.end\tFGO_05_OBJ_64\n");
__asm__(".word 0");
__asm__(".word 0");
INCLUDE_ASM("asm/nonmatchings/800b_5", RotMatrixZ);
src/800c.c
+25 -1
View File
@@ -1991,7 +1991,31 @@ __asm__(
".end\t_dws\n"
);
INCLUDE_ASM("asm/nonmatchings/800c", SYS_OBJ_1FF4);
__asm__(
".text\n"
".align\t2\n"
".globl\tSYS_OBJ_1FF4\n"
".ent\tSYS_OBJ_1FF4\n"
"SYS_OBJ_1FF4:\n"
".set\tnoreorder\n"
"lh $a1, 6($s1)\n"
"sh $v1, 4($s1)\n"
"bltz $a1, .L8005B25C\n"
"addu $v1, $a1, $zero\n"
"lui $v0, %hi(D_8007278E)\n"
"lh $v0, %lo(D_8007278E)($v0)\n"
"addu $a0, $v1, $zero\n"
"addu $v1, $v0, $zero\n"
"slt $v0, $v0, $a1\n"
"beqz $v0, .L8005B264\n"
"sll $v0, $a0, 16\n"
"j SYS_OBJ_202C\n"
"addu $a0, $v1, $zero\n"
".L8005B25C:\n"
"addu $a0, $zero, $zero\n"
".set\treorder\n"
".end\tSYS_OBJ_1FF4\n"
);
INCLUDE_ASM("asm/nonmatchings/800c", SYS_OBJ_202C);
src/800c3.c
+98 -3
View File
@@ -301,7 +301,33 @@ __asm__(
INCLUDE_ASM("asm/nonmatchings/800c3", func_8005D4F0);
INCLUDE_ASM("asm/nonmatchings/800c3", func_8005D538);
__asm__(
"\t.set\tnoreorder\n"
".set noreorder\n"
"\t.globl\tfunc_8005D538\n"
"func_8005D538:\n"
"lui $v0, %hi(D_80072970)\n"
"lw $v0, %lo(D_80072970)($v0)\n"
"addiu $sp, $sp, -32\n"
"sw $s0, 16($sp)\n"
"addu $s0, $a1, $zero\n"
"sw $s1, 20($sp)\n"
"sw $ra, 24($sp)\n"
"jalr $v0\n"
"addu $s1, $a2, $zero\n"
"addu $a0, $v0, $zero\n"
"addu $a1, $s0, $zero\n"
"jal func_8005E188\n"
"addu $a2, $s1, $zero\n"
"lw $ra, 24($sp)\n"
"lw $s1, 20($sp)\n"
"lw $s0, 16($sp)\n"
"jr $ra\n"
"addiu $sp, $sp, 32\n"
"nop\n"
"nop\n"
".set reorder\n"
);
INCLUDE_ASM("asm/nonmatchings/800c3", func_8005D588);
@@ -465,7 +491,69 @@ s32 func_8005E374(u8 *a0) {
return t + m + *(u32 *)(a0 + 0xEC);
}
INCLUDE_ASM("asm/nonmatchings/800c3", func_8005E3AC);
__asm__(
"\t.set\tnoreorder\n"
".set noreorder\n"
"\t.globl\tfunc_8005E3AC\n"
"func_8005E3AC:\n"
"addiu $sp, $sp, -32\n"
"sw $s0, 16($sp)\n"
"addu $s0, $a0, $zero\n"
"sw $s1, 20($sp)\n"
"addu $s1, $a1, $zero\n"
"beqz $s1, .L8005E3F4\n"
"sw $ra, 24($sp)\n"
"lw $v0, 4($s0)\n"
"nop\n"
"bnez $v0, .L8005E46C\n"
"addu $v0, $zero, $zero\n"
"lui $v0, %hi(D_80072978)\n"
"lw $v0, %lo(D_80072978)($v0)\n"
"nop\n"
"jalr $v0\n"
"nop\n"
"beqz $v0, .L8005E3FC\n"
"addiu $v0, $zero, 1\n"
".L8005E3F4:\n"
"j .L8005E46C\n"
"addu $v0, $zero, $zero\n"
".L8005E3FC:\n"
"addiu $v1, $zero, 4\n"
"addiu $a1, $s1, 3\n"
"sra $a1, $a1, 2\n"
"sb $v1, 73($s0)\n"
"addiu $v1, $zero, 1\n"
"sb $v1, 70($s0)\n"
"lui $v1, %hi(func_8005E480)\n"
"addiu $v1, $v1, %lo(func_8005E480)\n"
"sw $v1, 20($s0)\n"
"lbu $v1, 227($s0)\n"
"lui $a0, %hi(func_8005E528)\n"
"addiu $a0, $a0, %lo(func_8005E528)\n"
"sw $a0, 24($s0)\n"
"lbu $a0, 233($s0)\n"
"sll $a1, $a1, 2\n"
"sw $a1, 0($s0)\n"
"sb $zero, 71($s0)\n"
"addiu $v1, $v1, 1\n"
"sra $v1, $v1, 1\n"
"sll $v1, $v1, 2\n"
"addu $a1, $a1, $v1\n"
"sll $v1, $a0, 2\n"
"addu $v1, $v1, $a0\n"
"addiu $v1, $v1, 3\n"
"andi $v1, $v1, 0xFFC\n"
"sw $a1, 4($s0)\n"
"addu $a1, $a1, $v1\n"
"sw $a1, 8($s0)\n"
".L8005E46C:\n"
"lw $ra, 24($sp)\n"
"lw $s1, 20($sp)\n"
"lw $s0, 16($sp)\n"
"jr $ra\n"
"addiu $sp, $sp, 32\n"
".set reorder\n"
);
extern void func_8005EA68(void *arg0, s32 arg1);
extern void func_8005EA88(void *arg0, s32 arg1);
@@ -710,7 +798,14 @@ s32 func_8005E9D4(s32 a0)
return 0;
}
INCLUDE_ASM("asm/nonmatchings/800c3", func_8005EA34);
extern void func_8005EA34(void *arg0, s32 arg1);
void func_8005EA34(void *arg0, s32 arg1) {
*(u8 *)((u8 *)arg0 + 0x36) = 0x43;
*(s32 *)((u8 *)arg0 + 0x2C) = (s32)((u8 *)arg0 + 0x24);
*(u8 *)((u8 *)arg0 + 0x24) = arg1;
*(u8 *)((u8 *)arg0 + 0x35) = 1;
}
void func_8005EA54(void *arg0) {
src/sgap_8.c
+57 -2
View File
@@ -2,7 +2,47 @@
INCLUDE_ASM("asm/nonmatchings/sgap_8", _SsVmKeyOnNow);
INCLUDE_ASM("asm/nonmatchings/sgap_8", VM_NOWON_OBJ_1C0);
__asm__(
".text\n"
".align\t2\n"
".globl\tVM_NOWON_OBJ_1C0\n"
".type\tVM_NOWON_OBJ_1C0, @function\n"
".ent\tVM_NOWON_OBJ_1C0\n"
"VM_NOWON_OBJ_1C0:\n"
".set\tnoreorder\n"
"lui $v1, %hi(D_800B9B2B)\n"
"lbu $v1, %lo(D_800B9B2B)($v1)\n"
"nop\n"
"sltiu $v0, $v1, 0x40\n"
"beqz $v0, .L80040B38\n"
" mult $a2, $v1\n"
"mflo $v0\n"
"lui $v1, 0x410\n"
"ori $v1, $v1, 0x4105\n"
"multu $v0, $v1\n"
"mfhi $v1\n"
"subu $v0, $v0, $v1\n"
"srl $v0, $v0, 1\n"
"addu $v1, $v1, $v0\n"
"j VM_NOWON_OBJ_230\n"
" srl $a2, $v1, 5\n"
".L80040B38:\n"
"addiu $v0, $zero, 0x7F\n"
"subu $v0, $v0, $v1\n"
"mult $a1, $v0\n"
"mflo $v0\n"
"lui $v1, 0x410\n"
"ori $v1, $v1, 0x4105\n"
"multu $v0, $v1\n"
"mfhi $v1\n"
"subu $v0, $v0, $v1\n"
"srl $v0, $v0, 1\n"
"addu $v1, $v1, $v0\n"
"srl $a1, $v1, 5\n"
".set\treorder\n"
".size\tVM_NOWON_OBJ_1C0, . - VM_NOWON_OBJ_1C0\n"
".end\tVM_NOWON_OBJ_1C0\n"
);
__asm__(
".text\n"
@@ -278,6 +318,21 @@ s32 func_80041354(s32 param_1, u16 *param_2, u16 *param_3)
INCLUDE_ASM("asm/nonmatchings/sgap_8", func_800413B8);
INCLUDE_ASM("asm/nonmatchings/sgap_8", func_80041400);
extern s32 D_800C73D8[];
extern s16 D_800B9B36;
s32 func_80041400(s32 param_1)
{
s32 base;
s32 vab;
base = D_800C73D8[param_1 & 0xFF];
__asm__ __volatile__("" ::: "memory");
D_800B9B36 = param_1;
vab = (param_1 & 0xFF00) >> 8;
base += vab * 0xB0;
return *(s16 *)(base + 0x5A);
}
INCLUDE_ASM("asm/nonmatchings/sgap_8", func_80041448);