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feat(phase-32): T4b hand pass — md_MAIN_007:func_800CF408 (178 ins) BANKED byte-identical: the banked sibling func_800CD92C's spelling ported (libgpu P_TAG shape, u32 array view of the OT symbol via the fleet's asm-label alias); zero pins, zero asm bodies (S84)

Browse Source 
- func_800CF408: draft .run/P32/t4c/bank/func_800CF408.c (hand agent, agent MATCH re-verified by coordinator rtu_match in the real TU)
- one build for the same-TU batch: make build BINARY=md_MAIN_007 -j8 rc 0; sha1 2ff702b605ab5cfc18474c464c4c07e5f8ffd48c == config/check.md_MAIN_007.sha (BYTE-IDENTICAL)
- src/md_MAIN_007/md_MAIN_007.c: 0 INCLUDE_ASM left
This commit is contained in:
Drew T
2026-09-06 12:06:00 -06:00
parent b6fd3fff28
commit 8fa12bc226
1 changed files with 112 additions and 1 deletions
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src/md_MAIN_007/md_MAIN_007.c
+112 -1
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@@ -272,7 +272,118 @@ s32 func_800CF3B0(void *a0, void *a1, void *a2) {
}
INCLUDE_ASM("asm/md_MAIN_007/nonmatchings/md_MAIN_007", func_800CF408);
extern u8 *D_800A5E60;
extern u32 wD_800AA60C[] __asm__("D_800AA60C");
extern s16 D_800B9A02;
void func_800CF408(s32 x, s32 y) {
u8 *p;
u32 m24;
p = D_800A5E60;
x -= 0xA0;
y -= 0x78;
*(u8 *)(p + 0x3) = 5;
*(u32 *)(p + 0x4) = 0xE1000086;
*(u8 *)(p + 0xB) = 0x64;
*(u16 *)(p + 0x12) = 0x7980;
*(u8 *)(p + 0x8) = *(u8 *)(p + 0x9) = *(u8 *)(p + 0xA) = 0x80;
*(s16 *)(p + 0xC) = x;
*(s16 *)(p + 0xE) = y;
*(u8 *)(p + 0x10) = 0x20;
*(u8 *)(p + 0x11) = 0;
*(s16 *)(p + 0x14) = 0xA0;
*(s16 *)(p + 0x16) = 0x100;
m24 = 0x00FFFFFF;
{
u32 v = (wD_800AA60C[(u16)D_800B9A02 * 0x1000] & m24) & m24;
u32 t = *(u32 *)p;
t &= 0xFF000000;
t |= v;
*(u32 *)p = t;
}
{
s32 oi = (u16)D_800B9A02 * 0x1000;
wD_800AA60C[oi] = (wD_800AA60C[oi] & 0xFF000000) | ((u32)p & m24);
}
p += 0x18;
*(u8 *)(p + 0x3) = 5;
*(u32 *)(p + 0x4) = 0xE1000087;
*(u8 *)(p + 0xB) = 0x64;
*(u16 *)(p + 0x12) = 0x7980;
*(u8 *)(p + 0x8) = *(u8 *)(p + 0x9) = *(u8 *)(p + 0xA) = 0x80;
*(s16 *)(p + 0xC) = x + 0xA0;
*(s16 *)(p + 0xE) = y;
*(u8 *)(p + 0x10) = 0x40;
*(u8 *)(p + 0x11) = 0;
*(s16 *)(p + 0x14) = 0xA0;
*(s16 *)(p + 0x16) = 0x100;
{
u32 v = (wD_800AA60C[(u16)D_800B9A02 * 0x1000] & m24) & m24;
u32 t = *(u32 *)p;
t &= 0xFF000000;
t |= v;
*(u32 *)p = t;
}
{
s32 oi = (u16)D_800B9A02 * 0x1000;
wD_800AA60C[oi] = (wD_800AA60C[oi] & 0xFF000000) | ((u32)p & m24);
}
p += 0x18;
*(u8 *)(p + 0x3) = 5;
*(u32 *)(p + 0x4) = 0xE1000096;
*(u8 *)(p + 0xB) = 0x64;
*(u16 *)(p + 0x12) = 0x7980;
*(u8 *)(p + 0x8) = *(u8 *)(p + 0x9) = *(u8 *)(p + 0xA) = 0x80;
*(s16 *)(p + 0xC) = x;
*(s16 *)(p + 0xE) = y + 0x100;
*(u8 *)(p + 0x10) = 0x20;
*(u8 *)(p + 0x11) = 0;
*(s16 *)(p + 0x14) = 0xA0;
*(s16 *)(p + 0x16) = 0x100;
{
u32 v = (wD_800AA60C[(u16)D_800B9A02 * 0x1000] & m24) & m24;
u32 t = *(u32 *)p;
t &= 0xFF000000;
t |= v;
*(u32 *)p = t;
}
{
s32 oi = (u16)D_800B9A02 * 0x1000;
wD_800AA60C[oi] = (wD_800AA60C[oi] & 0xFF000000) | ((u32)p & m24);
}
p += 0x18;
*(u8 *)(p + 0x3) = 5;
*(u32 *)(p + 0x4) = 0xE1000097;
*(u8 *)(p + 0xB) = 0x64;
*(u16 *)(p + 0x12) = 0x7980;
*(u8 *)(p + 0x8) = *(u8 *)(p + 0x9) = *(u8 *)(p + 0xA) = 0x80;
*(s16 *)(p + 0xC) = x + 0xA0;
*(s16 *)(p + 0xE) = y + 0x100;
*(u8 *)(p + 0x10) = 0x40;
*(u8 *)(p + 0x11) = 0;
*(s16 *)(p + 0x14) = 0xA0;
*(s16 *)(p + 0x16) = 0x100;
{
u32 v = (wD_800AA60C[(u16)D_800B9A02 * 0x1000] & m24) & m24;
u32 t = *(u32 *)p;
t &= 0xFF000000;
t |= v;
*(u32 *)p = t;
}
{
s32 oi = (u16)D_800B9A02 * 0x1000;
wD_800AA60C[oi] = (wD_800AA60C[oi] & 0xFF000000) | ((u32)p & m24);
}
p += 0x18;
D_800A5E60 = p;
}
/* func_800CF6D0 — md_MAIN_007 (-O2). Builds six 0x18-byte "SPRT with its own tpage" primitives
* (tag / 0xE10000xx draw-mode word / rgb+code 0x64 / xy / uv+clut / wh) at the D_800A5E60 prim