mirror of
https://github.com/Druthulu/BFM-decomp
synced 2026-10-01 15:43:06 -04:00
feat(phase-30 S38): the free-sweep "wall" was a TYPE-SCOPE parse error — 0/6 becomes 6/6
family_sweep --hseq returned 0/6 on 0x801833f0 (328 ins, PURE, matched exemplar) and I recorded it as evidence that h_seq families do not template. It was a C PARSE ERROR: the remapped member body carries the EXEMPLAR's TU-local type names (PTag_801833F0 / Ft4_801833F0 / Drm_801833F0), which are declared only in ov_SC02_028's TUs. Undeclared type -> gcc-2.7.2 parses the declarator as an expression -> "parse error before `vtx'" two lines later. Never reached codegen. Lifting the three types to src/shared/engine_types.h (lift_types --apply; each had ONE canonical definition, no variants) turns the same sweep into 6/6 banked. R22 clean-fleet 140/140. This is the §20 propagation cap resurfacing on the h_seq sweep path, where nobody had checked for it. MY ERROR, RECORDED (R37/R14): I claimed in the S38 checkpoint and in commit commit:1410 that "family_sweep reports banked/failed WITHOUT the per-member build error". That is FALSE. There are 23,211 .run/hseq_failed.*.classified.txt files on disk; the diagnosis for BOTH of today's zeros was written by the sweep itself at probe time (0x80128c98's says "PLUMBING: conflicting types for `cdFileLocTable'"). I asserted a tool limitation without checking for it, and then spent two probes plus a manual --stage-only round rediscovering what was already in a file. Probe before costing.
This commit is contained in:
Drew T
@@ -4433,32 +4433,8 @@ void func_80182FD4(void *a0, void *a1)
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*/
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#include "common.h"
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typedef struct {
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u32 addr : 24;
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u32 len : 8;
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} PTag_801833F0;
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typedef struct {
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PTag_801833F0 tag;
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u8 r0, g0, b0, code;
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u16 x0, y0;
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u8 u0, v0;
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u16 clut;
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u16 x1, y1;
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u8 u1, v1;
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u16 tpage;
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u16 x2, y2;
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u8 u2, v2;
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u16 pad2;
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u16 x3, y3;
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u8 u3, v3;
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u16 pad3;
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} Ft4_801833F0;
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typedef struct {
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PTag_801833F0 tag;
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u32 code0;
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} Drm_801833F0;
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#define ADDPRIM_801833F0(o, p) \
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(((PTag_801833F0 *)(p))->addr = ((PTag_801833F0 *)(o))->addr, \
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@@ -23,30 +23,6 @@ typedef struct {
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typedef struct {
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s16 v[4];
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} Blk8_80126940_8017D6D0_8017F844;
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typedef struct {
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u32 addr : 24;
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u32 len : 8;
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} PTag_801833F0;
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typedef struct {
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PTag_801833F0 tag;
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u8 r0, g0, b0, code;
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u16 x0, y0;
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u8 u0, v0;
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u16 clut;
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u16 x1, y1;
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u8 u1, v1;
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u16 tpage;
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u16 x2, y2;
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u8 u2, v2;
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u16 pad2;
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u16 x3, y3;
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u8 u3, v3;
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u16 pad3;
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} Ft4_801833F0;
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typedef struct {
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PTag_801833F0 tag;
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u32 code0;
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} Drm_801833F0;
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typedef struct {
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s16 unk0;
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s16 unk2;
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@@ -4147,7 +4147,140 @@ void func_80180F98(void *a0, void *a1)
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}
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INCLUDE_ASM("asm/ov_SC03_097/nonmatchings/ov_SC03_097_jr_8017D898", func_801813B4);
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#define ADDPRIM_801833F0(o, p) \
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(((PTag_801833F0 *)(p))->addr = ((PTag_801833F0 *)(o))->addr, \
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((PTag_801833F0 *)(o))->addr = (u32)(p))
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#define SR3_801833F0(a) (((s32)(*(u16 *)(a) << 16)) >> 19)
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void func_801813B4(void *ent, void *spr, u32 *q, u32 *ot)
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{
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extern u8 *D_800A5E60;
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register s32 zr __asm__("$0");
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Ft4_801833F0 *poly;
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Drm_801833F0 *dm;
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s32 vtx;
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u32 flags;
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s32 tp, abr, code, shift;
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u16 x;
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u32 y;
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s32 tpage, clut, cy;
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s32 su, sv, uu, vv;
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u16 fl;
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s32 i, m;
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u32 b;
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poly = (Ft4_801833F0 *)D_800A5E60;
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fl = *(u16 *)((s32)ent + 0x1E) & 0x8000;
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flags = *(u32 *)((s32)ent + 4);
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tp = (flags >> 24) & 3;
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shift = 2 - tp;
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x = *(u16 *)((s32)ent + 0x28) + (*(s16 *)((s32)spr + 4) >> shift);
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y = *(u16 *)((s32)ent + 0x2A) + *(u16 *)((s32)spr + 6);
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vtx = *(s32 *)((s32)ent + 0x20);
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D_800A5E60 += 0xF0;
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if (flags & 0x40000000) {
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code = 0x2E;
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abr = (flags >> 28) & 3;
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} else {
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code = 0x2C;
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abr = 1;
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}
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tpage = (tp << 7) | (abr << 5) | ((y & 0x100) >> 4) | ((x & 0x3C0) >> 6) |
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((y & 0x200) << 2);
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b = *(u8 *)((s32)ent + 0x27);
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cy = (b + 0x100) << 6;
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if (b < 0xE0) {
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clut = cy | 0x16;
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} else {
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clut = cy | 0x10;
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}
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{
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s32 t = ((x - ((tpage & 0xF) << 6)) << shift) +
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(*(u16 *)((s32)spr + 4) & ((1 << shift) - 1));
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su = t + zr;
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__asm__ __volatile__("" ::"r"(t + *(u8 *)((s32)spr + 2) - 1));
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__asm__ __volatile__("" ::"r"(t));
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}
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y = y & 0xFFFF;
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if (tpage & 0x10) {
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sv = y - 0x100;
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} else {
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sv = y + zr;
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}
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__asm__ __volatile__("" ::"r"(sv + *(u8 *)((s32)spr + 3) - 1));
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i = 1;
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uu = su;
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vv = sv;
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for (; i < 13; i += 2, poly++) {
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s32 k = (i - 1) * 4;
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__asm__ __volatile__("" ::"r"(i));
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poly->tag.len = 9;
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poly->code = code;
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poly->tpage = tpage;
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poly->u2 = su;
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poly->v2 = sv;
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poly->u0 = SR3_801833F0(vtx + k + 0x10) + uu;
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poly->v0 = SR3_801833F0(vtx + k + 0x12) + vv;
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poly->u1 = SR3_801833F0(vtx + i * 4 + 0x10) + uu;
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poly->v1 = SR3_801833F0(vtx + i * 4 + 0x12) + vv;
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/* k2 is recorded as a giv HERE, AFTER the u1/v1 mem giv - see (1). */
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{
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s32 k2 = (i + 1) * 4;
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poly->u3 = SR3_801833F0(vtx + k2 + 0x10) + uu;
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poly->v3 = SR3_801833F0(vtx + k2 + 0x12) + vv;
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}
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poly->clut = clut;
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__asm__ __volatile__("" ::"r"(i), "r"(i));
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poly->r0 = *(u8 *)((s32)ent + 0x24);
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poly->g0 = *(u8 *)((s32)ent + 0x25);
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poly->b0 = *(u8 *)((s32)ent + 0x26);
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poly->x0 = ((u16 *)q)[i * 2];
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poly->y0 = ((u16 *)q)[i * 2 + 1];
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poly->x1 = ((u16 *)q)[i * 2 + 2];
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poly->y1 = ((u16 *)q)[i * 2 + 3];
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poly->x2 = ((u16 *)q)[0];
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poly->y2 = ((u16 *)q)[1];
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poly->x3 = ((u16 *)q)[i * 2 + 4];
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poly->y3 = ((u16 *)q)[i * 2 + 5];
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if (fl != 0) {
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ADDPRIM_801833F0(&ot[*(s32 *)((s32)q + 0x34 + (i >> 1) * 4)], poly);
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} else {
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ADDPRIM_801833F0(ot, poly);
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}
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}
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poly[-1].x3 = ((u16 *)q)[2];
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poly[-1].y3 = ((u16 *)q)[3];
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poly[-1].u3 = su + SR3_801833F0(vtx + 0x10);
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poly[-1].v3 = sv + SR3_801833F0(vtx + 0x12);
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if (flags & 0x40000000) {
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dm = (Drm_801833F0 *)poly;
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if (fl != 0) {
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m = 0;
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D_800A5E60 += 0x30;
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do {
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m++;
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dm->tag.len = 1;
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dm->code0 = (abr << 5) | 0xE100000A;
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ADDPRIM_801833F0(&ot[*(volatile s32 *)((s32)q + 0x34)], dm);
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q = (u32 *)((s32)q + 4);
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dm++;
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} while (m < 6);
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} else {
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dm->code0 = (abr << 5) | 0xE100000A;
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D_800A5E60 += 8;
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dm->tag.len = 1;
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ADDPRIM_801833F0(ot, dm);
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/* Zero-byte live-range stretch: puts vtx's allocno priority at
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* 1232, inside the (1228, 1296) window - see (2). Placement is
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* load-bearing; do not move this statement. */
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__asm__ __volatile__("" ::"r"(vtx));
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}
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}
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}
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void func_801818D4(void) {
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}
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@@ -4817,7 +4817,140 @@ INCLUDE_ASM("asm/ov_SC03_101/nonmatchings/ov_SC03_101_jr_8017CA80", func_801814A
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INCLUDE_ASM("asm/ov_SC03_101/nonmatchings/ov_SC03_101_jr_8017CA80", func_801814F8);
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INCLUDE_ASM("asm/ov_SC03_101/nonmatchings/ov_SC03_101_jr_8017CA80", func_80181914);
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#define ADDPRIM_801833F0(o, p) \
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(((PTag_801833F0 *)(p))->addr = ((PTag_801833F0 *)(o))->addr, \
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((PTag_801833F0 *)(o))->addr = (u32)(p))
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#define SR3_801833F0(a) (((s32)(*(u16 *)(a) << 16)) >> 19)
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void func_80181914(void *ent, void *spr, u32 *q, u32 *ot)
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{
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extern u8 *D_800A5E60;
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register s32 zr __asm__("$0");
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Ft4_801833F0 *poly;
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Drm_801833F0 *dm;
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s32 vtx;
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u32 flags;
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s32 tp, abr, code, shift;
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u16 x;
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u32 y;
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s32 tpage, clut, cy;
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s32 su, sv, uu, vv;
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u16 fl;
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s32 i, m;
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u32 b;
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poly = (Ft4_801833F0 *)D_800A5E60;
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fl = *(u16 *)((s32)ent + 0x1E) & 0x8000;
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flags = *(u32 *)((s32)ent + 4);
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tp = (flags >> 24) & 3;
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shift = 2 - tp;
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x = *(u16 *)((s32)ent + 0x28) + (*(s16 *)((s32)spr + 4) >> shift);
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y = *(u16 *)((s32)ent + 0x2A) + *(u16 *)((s32)spr + 6);
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vtx = *(s32 *)((s32)ent + 0x20);
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D_800A5E60 += 0xF0;
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if (flags & 0x40000000) {
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code = 0x2E;
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abr = (flags >> 28) & 3;
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} else {
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code = 0x2C;
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abr = 1;
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}
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tpage = (tp << 7) | (abr << 5) | ((y & 0x100) >> 4) | ((x & 0x3C0) >> 6) |
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((y & 0x200) << 2);
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b = *(u8 *)((s32)ent + 0x27);
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cy = (b + 0x100) << 6;
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if (b < 0xE0) {
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clut = cy | 0x16;
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} else {
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clut = cy | 0x10;
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}
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{
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s32 t = ((x - ((tpage & 0xF) << 6)) << shift) +
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(*(u16 *)((s32)spr + 4) & ((1 << shift) - 1));
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su = t + zr;
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__asm__ __volatile__("" ::"r"(t + *(u8 *)((s32)spr + 2) - 1));
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__asm__ __volatile__("" ::"r"(t));
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}
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y = y & 0xFFFF;
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if (tpage & 0x10) {
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sv = y - 0x100;
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} else {
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sv = y + zr;
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}
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__asm__ __volatile__("" ::"r"(sv + *(u8 *)((s32)spr + 3) - 1));
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i = 1;
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uu = su;
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vv = sv;
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for (; i < 13; i += 2, poly++) {
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s32 k = (i - 1) * 4;
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__asm__ __volatile__("" ::"r"(i));
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poly->tag.len = 9;
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poly->code = code;
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poly->tpage = tpage;
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poly->u2 = su;
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poly->v2 = sv;
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poly->u0 = SR3_801833F0(vtx + k + 0x10) + uu;
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poly->v0 = SR3_801833F0(vtx + k + 0x12) + vv;
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poly->u1 = SR3_801833F0(vtx + i * 4 + 0x10) + uu;
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poly->v1 = SR3_801833F0(vtx + i * 4 + 0x12) + vv;
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/* k2 is recorded as a giv HERE, AFTER the u1/v1 mem giv - see (1). */
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{
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s32 k2 = (i + 1) * 4;
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poly->u3 = SR3_801833F0(vtx + k2 + 0x10) + uu;
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poly->v3 = SR3_801833F0(vtx + k2 + 0x12) + vv;
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}
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poly->clut = clut;
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__asm__ __volatile__("" ::"r"(i), "r"(i));
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poly->r0 = *(u8 *)((s32)ent + 0x24);
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poly->g0 = *(u8 *)((s32)ent + 0x25);
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poly->b0 = *(u8 *)((s32)ent + 0x26);
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poly->x0 = ((u16 *)q)[i * 2];
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poly->y0 = ((u16 *)q)[i * 2 + 1];
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poly->x1 = ((u16 *)q)[i * 2 + 2];
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poly->y1 = ((u16 *)q)[i * 2 + 3];
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poly->x2 = ((u16 *)q)[0];
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poly->y2 = ((u16 *)q)[1];
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poly->x3 = ((u16 *)q)[i * 2 + 4];
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poly->y3 = ((u16 *)q)[i * 2 + 5];
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if (fl != 0) {
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ADDPRIM_801833F0(&ot[*(s32 *)((s32)q + 0x34 + (i >> 1) * 4)], poly);
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} else {
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ADDPRIM_801833F0(ot, poly);
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}
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}
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poly[-1].x3 = ((u16 *)q)[2];
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poly[-1].y3 = ((u16 *)q)[3];
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poly[-1].u3 = su + SR3_801833F0(vtx + 0x10);
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poly[-1].v3 = sv + SR3_801833F0(vtx + 0x12);
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if (flags & 0x40000000) {
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dm = (Drm_801833F0 *)poly;
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if (fl != 0) {
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m = 0;
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D_800A5E60 += 0x30;
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do {
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m++;
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dm->tag.len = 1;
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dm->code0 = (abr << 5) | 0xE100000A;
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ADDPRIM_801833F0(&ot[*(volatile s32 *)((s32)q + 0x34)], dm);
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q = (u32 *)((s32)q + 4);
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dm++;
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} while (m < 6);
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} else {
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dm->code0 = (abr << 5) | 0xE100000A;
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D_800A5E60 += 8;
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dm->tag.len = 1;
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ADDPRIM_801833F0(ot, dm);
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/* Zero-byte live-range stretch: puts vtx's allocno priority at
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* 1232, inside the (1228, 1296) window - see (2). Placement is
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* load-bearing; do not move this statement. */
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__asm__ __volatile__("" ::"r"(vtx));
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}
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}
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}
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void func_80181E34(void) {
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}
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@@ -4721,7 +4721,140 @@ INCLUDE_ASM("asm/ov_SC03_104/nonmatchings/ov_SC03_104_jr_8017CA80", func_801848E
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INCLUDE_ASM("asm/ov_SC03_104/nonmatchings/ov_SC03_104_jr_8017CA80", func_80184934);
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INCLUDE_ASM("asm/ov_SC03_104/nonmatchings/ov_SC03_104_jr_8017CA80", func_80184D50);
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#define ADDPRIM_801833F0(o, p) \
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(((PTag_801833F0 *)(p))->addr = ((PTag_801833F0 *)(o))->addr, \
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((PTag_801833F0 *)(o))->addr = (u32)(p))
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#define SR3_801833F0(a) (((s32)(*(u16 *)(a) << 16)) >> 19)
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void func_80184D50(void *ent, void *spr, u32 *q, u32 *ot)
|
||||
{
|
||||
extern u8 *D_800A5E60;
|
||||
register s32 zr __asm__("$0");
|
||||
|
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Ft4_801833F0 *poly;
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Drm_801833F0 *dm;
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s32 vtx;
|
||||
u32 flags;
|
||||
s32 tp, abr, code, shift;
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||||
u16 x;
|
||||
u32 y;
|
||||
s32 tpage, clut, cy;
|
||||
s32 su, sv, uu, vv;
|
||||
u16 fl;
|
||||
s32 i, m;
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||||
u32 b;
|
||||
|
||||
poly = (Ft4_801833F0 *)D_800A5E60;
|
||||
fl = *(u16 *)((s32)ent + 0x1E) & 0x8000;
|
||||
flags = *(u32 *)((s32)ent + 4);
|
||||
tp = (flags >> 24) & 3;
|
||||
shift = 2 - tp;
|
||||
x = *(u16 *)((s32)ent + 0x28) + (*(s16 *)((s32)spr + 4) >> shift);
|
||||
y = *(u16 *)((s32)ent + 0x2A) + *(u16 *)((s32)spr + 6);
|
||||
vtx = *(s32 *)((s32)ent + 0x20);
|
||||
D_800A5E60 += 0xF0;
|
||||
if (flags & 0x40000000) {
|
||||
code = 0x2E;
|
||||
abr = (flags >> 28) & 3;
|
||||
} else {
|
||||
code = 0x2C;
|
||||
abr = 1;
|
||||
}
|
||||
tpage = (tp << 7) | (abr << 5) | ((y & 0x100) >> 4) | ((x & 0x3C0) >> 6) |
|
||||
((y & 0x200) << 2);
|
||||
b = *(u8 *)((s32)ent + 0x27);
|
||||
cy = (b + 0x100) << 6;
|
||||
if (b < 0xE0) {
|
||||
clut = cy | 0x16;
|
||||
} else {
|
||||
clut = cy | 0x10;
|
||||
}
|
||||
{
|
||||
s32 t = ((x - ((tpage & 0xF) << 6)) << shift) +
|
||||
(*(u16 *)((s32)spr + 4) & ((1 << shift) - 1));
|
||||
su = t + zr;
|
||||
__asm__ __volatile__("" ::"r"(t + *(u8 *)((s32)spr + 2) - 1));
|
||||
__asm__ __volatile__("" ::"r"(t));
|
||||
}
|
||||
y = y & 0xFFFF;
|
||||
if (tpage & 0x10) {
|
||||
sv = y - 0x100;
|
||||
} else {
|
||||
sv = y + zr;
|
||||
}
|
||||
__asm__ __volatile__("" ::"r"(sv + *(u8 *)((s32)spr + 3) - 1));
|
||||
|
||||
i = 1;
|
||||
uu = su;
|
||||
vv = sv;
|
||||
for (; i < 13; i += 2, poly++) {
|
||||
s32 k = (i - 1) * 4;
|
||||
__asm__ __volatile__("" ::"r"(i));
|
||||
poly->tag.len = 9;
|
||||
poly->code = code;
|
||||
poly->tpage = tpage;
|
||||
poly->u2 = su;
|
||||
poly->v2 = sv;
|
||||
poly->u0 = SR3_801833F0(vtx + k + 0x10) + uu;
|
||||
poly->v0 = SR3_801833F0(vtx + k + 0x12) + vv;
|
||||
poly->u1 = SR3_801833F0(vtx + i * 4 + 0x10) + uu;
|
||||
poly->v1 = SR3_801833F0(vtx + i * 4 + 0x12) + vv;
|
||||
/* k2 is recorded as a giv HERE, AFTER the u1/v1 mem giv - see (1). */
|
||||
{
|
||||
s32 k2 = (i + 1) * 4;
|
||||
poly->u3 = SR3_801833F0(vtx + k2 + 0x10) + uu;
|
||||
poly->v3 = SR3_801833F0(vtx + k2 + 0x12) + vv;
|
||||
}
|
||||
poly->clut = clut;
|
||||
__asm__ __volatile__("" ::"r"(i), "r"(i));
|
||||
poly->r0 = *(u8 *)((s32)ent + 0x24);
|
||||
poly->g0 = *(u8 *)((s32)ent + 0x25);
|
||||
poly->b0 = *(u8 *)((s32)ent + 0x26);
|
||||
poly->x0 = ((u16 *)q)[i * 2];
|
||||
poly->y0 = ((u16 *)q)[i * 2 + 1];
|
||||
poly->x1 = ((u16 *)q)[i * 2 + 2];
|
||||
poly->y1 = ((u16 *)q)[i * 2 + 3];
|
||||
poly->x2 = ((u16 *)q)[0];
|
||||
poly->y2 = ((u16 *)q)[1];
|
||||
poly->x3 = ((u16 *)q)[i * 2 + 4];
|
||||
poly->y3 = ((u16 *)q)[i * 2 + 5];
|
||||
if (fl != 0) {
|
||||
ADDPRIM_801833F0(&ot[*(s32 *)((s32)q + 0x34 + (i >> 1) * 4)], poly);
|
||||
} else {
|
||||
ADDPRIM_801833F0(ot, poly);
|
||||
}
|
||||
}
|
||||
poly[-1].x3 = ((u16 *)q)[2];
|
||||
poly[-1].y3 = ((u16 *)q)[3];
|
||||
poly[-1].u3 = su + SR3_801833F0(vtx + 0x10);
|
||||
poly[-1].v3 = sv + SR3_801833F0(vtx + 0x12);
|
||||
|
||||
if (flags & 0x40000000) {
|
||||
dm = (Drm_801833F0 *)poly;
|
||||
if (fl != 0) {
|
||||
m = 0;
|
||||
D_800A5E60 += 0x30;
|
||||
do {
|
||||
m++;
|
||||
dm->tag.len = 1;
|
||||
dm->code0 = (abr << 5) | 0xE100000A;
|
||||
ADDPRIM_801833F0(&ot[*(volatile s32 *)((s32)q + 0x34)], dm);
|
||||
q = (u32 *)((s32)q + 4);
|
||||
dm++;
|
||||
} while (m < 6);
|
||||
} else {
|
||||
dm->code0 = (abr << 5) | 0xE100000A;
|
||||
D_800A5E60 += 8;
|
||||
dm->tag.len = 1;
|
||||
ADDPRIM_801833F0(ot, dm);
|
||||
/* Zero-byte live-range stretch: puts vtx's allocno priority at
|
||||
* 1232, inside the (1228, 1296) window - see (2). Placement is
|
||||
* load-bearing; do not move this statement. */
|
||||
__asm__ __volatile__("" ::"r"(vtx));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void func_80185270(void) {
|
||||
}
|
||||
|
||||
@@ -3866,7 +3866,140 @@ INCLUDE_ASM("asm/ov_SC04_003/nonmatchings/ov_SC04_003_jr_8017BEBC", func_8017E49
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC04_003/nonmatchings/ov_SC04_003_jr_8017BEBC", func_8017E4F4);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC04_003/nonmatchings/ov_SC04_003_jr_8017BEBC", func_8017E910);
|
||||
#define ADDPRIM_801833F0(o, p) \
|
||||
(((PTag_801833F0 *)(p))->addr = ((PTag_801833F0 *)(o))->addr, \
|
||||
((PTag_801833F0 *)(o))->addr = (u32)(p))
|
||||
#define SR3_801833F0(a) (((s32)(*(u16 *)(a) << 16)) >> 19)
|
||||
|
||||
void func_8017E910(void *ent, void *spr, u32 *q, u32 *ot)
|
||||
{
|
||||
extern u8 *D_800A5E60;
|
||||
register s32 zr __asm__("$0");
|
||||
|
||||
Ft4_801833F0 *poly;
|
||||
Drm_801833F0 *dm;
|
||||
s32 vtx;
|
||||
u32 flags;
|
||||
s32 tp, abr, code, shift;
|
||||
u16 x;
|
||||
u32 y;
|
||||
s32 tpage, clut, cy;
|
||||
s32 su, sv, uu, vv;
|
||||
u16 fl;
|
||||
s32 i, m;
|
||||
u32 b;
|
||||
|
||||
poly = (Ft4_801833F0 *)D_800A5E60;
|
||||
fl = *(u16 *)((s32)ent + 0x1E) & 0x8000;
|
||||
flags = *(u32 *)((s32)ent + 4);
|
||||
tp = (flags >> 24) & 3;
|
||||
shift = 2 - tp;
|
||||
x = *(u16 *)((s32)ent + 0x28) + (*(s16 *)((s32)spr + 4) >> shift);
|
||||
y = *(u16 *)((s32)ent + 0x2A) + *(u16 *)((s32)spr + 6);
|
||||
vtx = *(s32 *)((s32)ent + 0x20);
|
||||
D_800A5E60 += 0xF0;
|
||||
if (flags & 0x40000000) {
|
||||
code = 0x2E;
|
||||
abr = (flags >> 28) & 3;
|
||||
} else {
|
||||
code = 0x2C;
|
||||
abr = 1;
|
||||
}
|
||||
tpage = (tp << 7) | (abr << 5) | ((y & 0x100) >> 4) | ((x & 0x3C0) >> 6) |
|
||||
((y & 0x200) << 2);
|
||||
b = *(u8 *)((s32)ent + 0x27);
|
||||
cy = (b + 0x100) << 6;
|
||||
if (b < 0xE0) {
|
||||
clut = cy | 0x16;
|
||||
} else {
|
||||
clut = cy | 0x10;
|
||||
}
|
||||
{
|
||||
s32 t = ((x - ((tpage & 0xF) << 6)) << shift) +
|
||||
(*(u16 *)((s32)spr + 4) & ((1 << shift) - 1));
|
||||
su = t + zr;
|
||||
__asm__ __volatile__("" ::"r"(t + *(u8 *)((s32)spr + 2) - 1));
|
||||
__asm__ __volatile__("" ::"r"(t));
|
||||
}
|
||||
y = y & 0xFFFF;
|
||||
if (tpage & 0x10) {
|
||||
sv = y - 0x100;
|
||||
} else {
|
||||
sv = y + zr;
|
||||
}
|
||||
__asm__ __volatile__("" ::"r"(sv + *(u8 *)((s32)spr + 3) - 1));
|
||||
|
||||
i = 1;
|
||||
uu = su;
|
||||
vv = sv;
|
||||
for (; i < 13; i += 2, poly++) {
|
||||
s32 k = (i - 1) * 4;
|
||||
__asm__ __volatile__("" ::"r"(i));
|
||||
poly->tag.len = 9;
|
||||
poly->code = code;
|
||||
poly->tpage = tpage;
|
||||
poly->u2 = su;
|
||||
poly->v2 = sv;
|
||||
poly->u0 = SR3_801833F0(vtx + k + 0x10) + uu;
|
||||
poly->v0 = SR3_801833F0(vtx + k + 0x12) + vv;
|
||||
poly->u1 = SR3_801833F0(vtx + i * 4 + 0x10) + uu;
|
||||
poly->v1 = SR3_801833F0(vtx + i * 4 + 0x12) + vv;
|
||||
/* k2 is recorded as a giv HERE, AFTER the u1/v1 mem giv - see (1). */
|
||||
{
|
||||
s32 k2 = (i + 1) * 4;
|
||||
poly->u3 = SR3_801833F0(vtx + k2 + 0x10) + uu;
|
||||
poly->v3 = SR3_801833F0(vtx + k2 + 0x12) + vv;
|
||||
}
|
||||
poly->clut = clut;
|
||||
__asm__ __volatile__("" ::"r"(i), "r"(i));
|
||||
poly->r0 = *(u8 *)((s32)ent + 0x24);
|
||||
poly->g0 = *(u8 *)((s32)ent + 0x25);
|
||||
poly->b0 = *(u8 *)((s32)ent + 0x26);
|
||||
poly->x0 = ((u16 *)q)[i * 2];
|
||||
poly->y0 = ((u16 *)q)[i * 2 + 1];
|
||||
poly->x1 = ((u16 *)q)[i * 2 + 2];
|
||||
poly->y1 = ((u16 *)q)[i * 2 + 3];
|
||||
poly->x2 = ((u16 *)q)[0];
|
||||
poly->y2 = ((u16 *)q)[1];
|
||||
poly->x3 = ((u16 *)q)[i * 2 + 4];
|
||||
poly->y3 = ((u16 *)q)[i * 2 + 5];
|
||||
if (fl != 0) {
|
||||
ADDPRIM_801833F0(&ot[*(s32 *)((s32)q + 0x34 + (i >> 1) * 4)], poly);
|
||||
} else {
|
||||
ADDPRIM_801833F0(ot, poly);
|
||||
}
|
||||
}
|
||||
poly[-1].x3 = ((u16 *)q)[2];
|
||||
poly[-1].y3 = ((u16 *)q)[3];
|
||||
poly[-1].u3 = su + SR3_801833F0(vtx + 0x10);
|
||||
poly[-1].v3 = sv + SR3_801833F0(vtx + 0x12);
|
||||
|
||||
if (flags & 0x40000000) {
|
||||
dm = (Drm_801833F0 *)poly;
|
||||
if (fl != 0) {
|
||||
m = 0;
|
||||
D_800A5E60 += 0x30;
|
||||
do {
|
||||
m++;
|
||||
dm->tag.len = 1;
|
||||
dm->code0 = (abr << 5) | 0xE100000A;
|
||||
ADDPRIM_801833F0(&ot[*(volatile s32 *)((s32)q + 0x34)], dm);
|
||||
q = (u32 *)((s32)q + 4);
|
||||
dm++;
|
||||
} while (m < 6);
|
||||
} else {
|
||||
dm->code0 = (abr << 5) | 0xE100000A;
|
||||
D_800A5E60 += 8;
|
||||
dm->tag.len = 1;
|
||||
ADDPRIM_801833F0(ot, dm);
|
||||
/* Zero-byte live-range stretch: puts vtx's allocno priority at
|
||||
* 1232, inside the (1228, 1296) window - see (2). Placement is
|
||||
* load-bearing; do not move this statement. */
|
||||
__asm__ __volatile__("" ::"r"(vtx));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void func_8017EE30(void) {
|
||||
}
|
||||
|
||||
@@ -5686,7 +5686,140 @@ INCLUDE_ASM("asm/ov_SC04_005/nonmatchings/ov_SC04_005_jr_8017BEBC", func_80180FF
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC04_005/nonmatchings/ov_SC04_005_jr_8017BEBC", func_80181054);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC04_005/nonmatchings/ov_SC04_005_jr_8017BEBC", func_80181470);
|
||||
#define ADDPRIM_801833F0(o, p) \
|
||||
(((PTag_801833F0 *)(p))->addr = ((PTag_801833F0 *)(o))->addr, \
|
||||
((PTag_801833F0 *)(o))->addr = (u32)(p))
|
||||
#define SR3_801833F0(a) (((s32)(*(u16 *)(a) << 16)) >> 19)
|
||||
|
||||
void func_80181470(void *ent, void *spr, u32 *q, u32 *ot)
|
||||
{
|
||||
extern u8 *D_800A5E60;
|
||||
register s32 zr __asm__("$0");
|
||||
|
||||
Ft4_801833F0 *poly;
|
||||
Drm_801833F0 *dm;
|
||||
s32 vtx;
|
||||
u32 flags;
|
||||
s32 tp, abr, code, shift;
|
||||
u16 x;
|
||||
u32 y;
|
||||
s32 tpage, clut, cy;
|
||||
s32 su, sv, uu, vv;
|
||||
u16 fl;
|
||||
s32 i, m;
|
||||
u32 b;
|
||||
|
||||
poly = (Ft4_801833F0 *)D_800A5E60;
|
||||
fl = *(u16 *)((s32)ent + 0x1E) & 0x8000;
|
||||
flags = *(u32 *)((s32)ent + 4);
|
||||
tp = (flags >> 24) & 3;
|
||||
shift = 2 - tp;
|
||||
x = *(u16 *)((s32)ent + 0x28) + (*(s16 *)((s32)spr + 4) >> shift);
|
||||
y = *(u16 *)((s32)ent + 0x2A) + *(u16 *)((s32)spr + 6);
|
||||
vtx = *(s32 *)((s32)ent + 0x20);
|
||||
D_800A5E60 += 0xF0;
|
||||
if (flags & 0x40000000) {
|
||||
code = 0x2E;
|
||||
abr = (flags >> 28) & 3;
|
||||
} else {
|
||||
code = 0x2C;
|
||||
abr = 1;
|
||||
}
|
||||
tpage = (tp << 7) | (abr << 5) | ((y & 0x100) >> 4) | ((x & 0x3C0) >> 6) |
|
||||
((y & 0x200) << 2);
|
||||
b = *(u8 *)((s32)ent + 0x27);
|
||||
cy = (b + 0x100) << 6;
|
||||
if (b < 0xE0) {
|
||||
clut = cy | 0x16;
|
||||
} else {
|
||||
clut = cy | 0x10;
|
||||
}
|
||||
{
|
||||
s32 t = ((x - ((tpage & 0xF) << 6)) << shift) +
|
||||
(*(u16 *)((s32)spr + 4) & ((1 << shift) - 1));
|
||||
su = t + zr;
|
||||
__asm__ __volatile__("" ::"r"(t + *(u8 *)((s32)spr + 2) - 1));
|
||||
__asm__ __volatile__("" ::"r"(t));
|
||||
}
|
||||
y = y & 0xFFFF;
|
||||
if (tpage & 0x10) {
|
||||
sv = y - 0x100;
|
||||
} else {
|
||||
sv = y + zr;
|
||||
}
|
||||
__asm__ __volatile__("" ::"r"(sv + *(u8 *)((s32)spr + 3) - 1));
|
||||
|
||||
i = 1;
|
||||
uu = su;
|
||||
vv = sv;
|
||||
for (; i < 13; i += 2, poly++) {
|
||||
s32 k = (i - 1) * 4;
|
||||
__asm__ __volatile__("" ::"r"(i));
|
||||
poly->tag.len = 9;
|
||||
poly->code = code;
|
||||
poly->tpage = tpage;
|
||||
poly->u2 = su;
|
||||
poly->v2 = sv;
|
||||
poly->u0 = SR3_801833F0(vtx + k + 0x10) + uu;
|
||||
poly->v0 = SR3_801833F0(vtx + k + 0x12) + vv;
|
||||
poly->u1 = SR3_801833F0(vtx + i * 4 + 0x10) + uu;
|
||||
poly->v1 = SR3_801833F0(vtx + i * 4 + 0x12) + vv;
|
||||
/* k2 is recorded as a giv HERE, AFTER the u1/v1 mem giv - see (1). */
|
||||
{
|
||||
s32 k2 = (i + 1) * 4;
|
||||
poly->u3 = SR3_801833F0(vtx + k2 + 0x10) + uu;
|
||||
poly->v3 = SR3_801833F0(vtx + k2 + 0x12) + vv;
|
||||
}
|
||||
poly->clut = clut;
|
||||
__asm__ __volatile__("" ::"r"(i), "r"(i));
|
||||
poly->r0 = *(u8 *)((s32)ent + 0x24);
|
||||
poly->g0 = *(u8 *)((s32)ent + 0x25);
|
||||
poly->b0 = *(u8 *)((s32)ent + 0x26);
|
||||
poly->x0 = ((u16 *)q)[i * 2];
|
||||
poly->y0 = ((u16 *)q)[i * 2 + 1];
|
||||
poly->x1 = ((u16 *)q)[i * 2 + 2];
|
||||
poly->y1 = ((u16 *)q)[i * 2 + 3];
|
||||
poly->x2 = ((u16 *)q)[0];
|
||||
poly->y2 = ((u16 *)q)[1];
|
||||
poly->x3 = ((u16 *)q)[i * 2 + 4];
|
||||
poly->y3 = ((u16 *)q)[i * 2 + 5];
|
||||
if (fl != 0) {
|
||||
ADDPRIM_801833F0(&ot[*(s32 *)((s32)q + 0x34 + (i >> 1) * 4)], poly);
|
||||
} else {
|
||||
ADDPRIM_801833F0(ot, poly);
|
||||
}
|
||||
}
|
||||
poly[-1].x3 = ((u16 *)q)[2];
|
||||
poly[-1].y3 = ((u16 *)q)[3];
|
||||
poly[-1].u3 = su + SR3_801833F0(vtx + 0x10);
|
||||
poly[-1].v3 = sv + SR3_801833F0(vtx + 0x12);
|
||||
|
||||
if (flags & 0x40000000) {
|
||||
dm = (Drm_801833F0 *)poly;
|
||||
if (fl != 0) {
|
||||
m = 0;
|
||||
D_800A5E60 += 0x30;
|
||||
do {
|
||||
m++;
|
||||
dm->tag.len = 1;
|
||||
dm->code0 = (abr << 5) | 0xE100000A;
|
||||
ADDPRIM_801833F0(&ot[*(volatile s32 *)((s32)q + 0x34)], dm);
|
||||
q = (u32 *)((s32)q + 4);
|
||||
dm++;
|
||||
} while (m < 6);
|
||||
} else {
|
||||
dm->code0 = (abr << 5) | 0xE100000A;
|
||||
D_800A5E60 += 8;
|
||||
dm->tag.len = 1;
|
||||
ADDPRIM_801833F0(ot, dm);
|
||||
/* Zero-byte live-range stretch: puts vtx's allocno priority at
|
||||
* 1232, inside the (1228, 1296) window - see (2). Placement is
|
||||
* load-bearing; do not move this statement. */
|
||||
__asm__ __volatile__("" ::"r"(vtx));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void func_80181990(void) {
|
||||
}
|
||||
|
||||
@@ -5169,7 +5169,140 @@ INCLUDE_ASM("asm/ov_SC04_007/nonmatchings/ov_SC04_007_jr_8017BEBC", func_8017FEA
|
||||
INCLUDE_ASM("asm/ov_SC04_007/nonmatchings/ov_SC04_007_jr_8017BEBC", func_8017FF08);
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC04_007/nonmatchings/ov_SC04_007_jr_8017BEBC", func_80180324);
|
||||
#define ADDPRIM_801833F0(o, p) \
|
||||
(((PTag_801833F0 *)(p))->addr = ((PTag_801833F0 *)(o))->addr, \
|
||||
((PTag_801833F0 *)(o))->addr = (u32)(p))
|
||||
#define SR3_801833F0(a) (((s32)(*(u16 *)(a) << 16)) >> 19)
|
||||
|
||||
void func_80180324(void *ent, void *spr, u32 *q, u32 *ot)
|
||||
{
|
||||
extern u8 *D_800A5E60;
|
||||
register s32 zr __asm__("$0");
|
||||
|
||||
Ft4_801833F0 *poly;
|
||||
Drm_801833F0 *dm;
|
||||
s32 vtx;
|
||||
u32 flags;
|
||||
s32 tp, abr, code, shift;
|
||||
u16 x;
|
||||
u32 y;
|
||||
s32 tpage, clut, cy;
|
||||
s32 su, sv, uu, vv;
|
||||
u16 fl;
|
||||
s32 i, m;
|
||||
u32 b;
|
||||
|
||||
poly = (Ft4_801833F0 *)D_800A5E60;
|
||||
fl = *(u16 *)((s32)ent + 0x1E) & 0x8000;
|
||||
flags = *(u32 *)((s32)ent + 4);
|
||||
tp = (flags >> 24) & 3;
|
||||
shift = 2 - tp;
|
||||
x = *(u16 *)((s32)ent + 0x28) + (*(s16 *)((s32)spr + 4) >> shift);
|
||||
y = *(u16 *)((s32)ent + 0x2A) + *(u16 *)((s32)spr + 6);
|
||||
vtx = *(s32 *)((s32)ent + 0x20);
|
||||
D_800A5E60 += 0xF0;
|
||||
if (flags & 0x40000000) {
|
||||
code = 0x2E;
|
||||
abr = (flags >> 28) & 3;
|
||||
} else {
|
||||
code = 0x2C;
|
||||
abr = 1;
|
||||
}
|
||||
tpage = (tp << 7) | (abr << 5) | ((y & 0x100) >> 4) | ((x & 0x3C0) >> 6) |
|
||||
((y & 0x200) << 2);
|
||||
b = *(u8 *)((s32)ent + 0x27);
|
||||
cy = (b + 0x100) << 6;
|
||||
if (b < 0xE0) {
|
||||
clut = cy | 0x16;
|
||||
} else {
|
||||
clut = cy | 0x10;
|
||||
}
|
||||
{
|
||||
s32 t = ((x - ((tpage & 0xF) << 6)) << shift) +
|
||||
(*(u16 *)((s32)spr + 4) & ((1 << shift) - 1));
|
||||
su = t + zr;
|
||||
__asm__ __volatile__("" ::"r"(t + *(u8 *)((s32)spr + 2) - 1));
|
||||
__asm__ __volatile__("" ::"r"(t));
|
||||
}
|
||||
y = y & 0xFFFF;
|
||||
if (tpage & 0x10) {
|
||||
sv = y - 0x100;
|
||||
} else {
|
||||
sv = y + zr;
|
||||
}
|
||||
__asm__ __volatile__("" ::"r"(sv + *(u8 *)((s32)spr + 3) - 1));
|
||||
|
||||
i = 1;
|
||||
uu = su;
|
||||
vv = sv;
|
||||
for (; i < 13; i += 2, poly++) {
|
||||
s32 k = (i - 1) * 4;
|
||||
__asm__ __volatile__("" ::"r"(i));
|
||||
poly->tag.len = 9;
|
||||
poly->code = code;
|
||||
poly->tpage = tpage;
|
||||
poly->u2 = su;
|
||||
poly->v2 = sv;
|
||||
poly->u0 = SR3_801833F0(vtx + k + 0x10) + uu;
|
||||
poly->v0 = SR3_801833F0(vtx + k + 0x12) + vv;
|
||||
poly->u1 = SR3_801833F0(vtx + i * 4 + 0x10) + uu;
|
||||
poly->v1 = SR3_801833F0(vtx + i * 4 + 0x12) + vv;
|
||||
/* k2 is recorded as a giv HERE, AFTER the u1/v1 mem giv - see (1). */
|
||||
{
|
||||
s32 k2 = (i + 1) * 4;
|
||||
poly->u3 = SR3_801833F0(vtx + k2 + 0x10) + uu;
|
||||
poly->v3 = SR3_801833F0(vtx + k2 + 0x12) + vv;
|
||||
}
|
||||
poly->clut = clut;
|
||||
__asm__ __volatile__("" ::"r"(i), "r"(i));
|
||||
poly->r0 = *(u8 *)((s32)ent + 0x24);
|
||||
poly->g0 = *(u8 *)((s32)ent + 0x25);
|
||||
poly->b0 = *(u8 *)((s32)ent + 0x26);
|
||||
poly->x0 = ((u16 *)q)[i * 2];
|
||||
poly->y0 = ((u16 *)q)[i * 2 + 1];
|
||||
poly->x1 = ((u16 *)q)[i * 2 + 2];
|
||||
poly->y1 = ((u16 *)q)[i * 2 + 3];
|
||||
poly->x2 = ((u16 *)q)[0];
|
||||
poly->y2 = ((u16 *)q)[1];
|
||||
poly->x3 = ((u16 *)q)[i * 2 + 4];
|
||||
poly->y3 = ((u16 *)q)[i * 2 + 5];
|
||||
if (fl != 0) {
|
||||
ADDPRIM_801833F0(&ot[*(s32 *)((s32)q + 0x34 + (i >> 1) * 4)], poly);
|
||||
} else {
|
||||
ADDPRIM_801833F0(ot, poly);
|
||||
}
|
||||
}
|
||||
poly[-1].x3 = ((u16 *)q)[2];
|
||||
poly[-1].y3 = ((u16 *)q)[3];
|
||||
poly[-1].u3 = su + SR3_801833F0(vtx + 0x10);
|
||||
poly[-1].v3 = sv + SR3_801833F0(vtx + 0x12);
|
||||
|
||||
if (flags & 0x40000000) {
|
||||
dm = (Drm_801833F0 *)poly;
|
||||
if (fl != 0) {
|
||||
m = 0;
|
||||
D_800A5E60 += 0x30;
|
||||
do {
|
||||
m++;
|
||||
dm->tag.len = 1;
|
||||
dm->code0 = (abr << 5) | 0xE100000A;
|
||||
ADDPRIM_801833F0(&ot[*(volatile s32 *)((s32)q + 0x34)], dm);
|
||||
q = (u32 *)((s32)q + 4);
|
||||
dm++;
|
||||
} while (m < 6);
|
||||
} else {
|
||||
dm->code0 = (abr << 5) | 0xE100000A;
|
||||
D_800A5E60 += 8;
|
||||
dm->tag.len = 1;
|
||||
ADDPRIM_801833F0(ot, dm);
|
||||
/* Zero-byte live-range stretch: puts vtx's allocno priority at
|
||||
* 1232, inside the (1228, 1296) window - see (2). Placement is
|
||||
* load-bearing; do not move this statement. */
|
||||
__asm__ __volatile__("" ::"r"(vtx));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void func_80180844(void) {
|
||||
}
|
||||
|
||||
@@ -1294,6 +1294,32 @@ typedef struct Rec801466F0 {
|
||||
s32 unkC; /* +0x0C */
|
||||
s32 unk10; /* +0x10 */
|
||||
} Rec801466F0;
|
||||
|
||||
/* --- lift_types.py fleet lift --- */
|
||||
typedef struct {
|
||||
u32 addr : 24;
|
||||
u32 len : 8;
|
||||
} PTag_801833F0;
|
||||
typedef struct {
|
||||
PTag_801833F0 tag;
|
||||
u32 code0;
|
||||
} Drm_801833F0;
|
||||
typedef struct {
|
||||
PTag_801833F0 tag;
|
||||
u8 r0, g0, b0, code;
|
||||
u16 x0, y0;
|
||||
u8 u0, v0;
|
||||
u16 clut;
|
||||
u16 x1, y1;
|
||||
u8 u1, v1;
|
||||
u16 tpage;
|
||||
u16 x2, y2;
|
||||
u8 u2, v2;
|
||||
u16 pad2;
|
||||
u16 x3, y3;
|
||||
u8 u3, v3;
|
||||
u16 pad3;
|
||||
} Ft4_801833F0;
|
||||
#endif /* BFM_ENGINE_TYPES_H */ /* SESSION-19: moved here — 11 typedefs (the
|
||||
* Phase-29 crack-wave lift onward) were sitting OUTSIDE the guard, so any TU that
|
||||
* included this header twice re-declared them. gcc-2.7.2 rejects a repeated typedef
|
||||
|
||||
Reference in New Issue
Block a user