mirror of
https://github.com/Druthulu/BFM-decomp
synced 2026-09-27 05:56:00 -04:00
feat(decomp): ox wave cl overlays — 3 banked
Committed before the main batch: gate_main reverts on failure and would take these with it.
This commit is contained in:
Drew T
+1
-1
@@ -321,7 +321,7 @@ ov_SC03_002_ELF := $(ov_SC03_002_OUT).elf
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ov_SC03_002_MAPFILE := $(ov_SC03_002_OUT).map
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ov_SC03_002_LD_SCRIPT := $(ov_SC03_002_OUT).ld
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ov_SC03_002_SPLAT_YAML := config/splat.ov_SC03_002.yaml
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ov_SC03_002_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_002.o,ov_SC03_002_jr_8012ACE0.o,tail2.data.o,ov_SC03_002_jr_80135888.o,tail3.data.o,ov_SC03_002_jr_80135A4C.o,tail4.data.o,ov_SC03_002_jr_80135D20.o,tail5.data.o,ov_SC03_002_jr_801380E0.o,ov_SC03_002_o0c.o,tail6.data.o,ov_SC03_002_jr_8013F350.o,tail7.data.o,ov_SC03_002_jr_8013FFD8.o,tail8.data.o,ov_SC03_002_jr_80140608.o,tail9.data.o,ov_SC03_002_jr_8015444C.o,ov_SC03_002_jr_80154C24.o,ov_SC03_002_jr_801588CC.o,ov_SC03_002_jr_80159C84.o,tail10.data.o,ov_SC03_002_jr_8015A3C8.o,tail11.data.o,ov_SC03_002_jr_8015AE2C.o,tail12.data.o,ov_SC03_002_jr_8015C32C.o,tail13.data.o,ov_SC03_002_jr_8016AB6C.o,tail14.data.o,ov_SC03_002_jr_80171B4C.o,ov_SC03_002_jr_801734BC.o,tail15.data.o,ov_SC03_002_jr_801789AC.o,ov_SC03_002_jr_80178D40.o,tail16.data.o,ov_SC03_002_jr_8017A4AC.o,tail17.data.o,ov_SC03_002_jr_8017AE2C.o,ov_SC03_002_jr_8017D604.o,tail18.data.o,ov_SC03_002_jr_8018431C.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve
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ov_SC03_002_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_002.o,ov_SC03_002_jr_8012ACE0.o,tail2.data.o,ov_SC03_002_jr_80135888.o,tail3.data.o,ov_SC03_002_jr_80135A4C.o,tail4.data.o,ov_SC03_002_jr_80135D20.o,tail5.data.o,ov_SC03_002_jr_801380E0.o,ov_SC03_002_o0c.o,tail6.data.o,ov_SC03_002_jr_8013F350.o,tail7.data.o,ov_SC03_002_jr_8013FFD8.o,tail8.data.o,ov_SC03_002_jr_80140608.o,tail9.data.o,ov_SC03_002_jr_8015444C.o,ov_SC03_002_jr_80154C24.o,ov_SC03_002_jr_801588CC.o,ov_SC03_002_jr_80159C84.o,tail10.data.o,ov_SC03_002_jr_8015A3C8.o,tail11.data.o,ov_SC03_002_jr_8015AE2C.o,tail12.data.o,ov_SC03_002_jr_8015C32C.o,tail13.data.o,ov_SC03_002_jr_8016AB6C.o,tail14.data.o,ov_SC03_002_jr_80171B4C.o,ov_SC03_002_jr_801734BC.o,tail15.data.o,ov_SC03_002_jr_801789AC.o,ov_SC03_002_jr_80178D40.o,tail16.data.o,ov_SC03_002_jr_8017A4AC.o,tail17.data.o,ov_SC03_002_jr_8017AE2C.o,ov_SC03_002_jr_8017D604.o,tail18.data.o,ov_SC03_002_jr_80181D78.o,ov_SC03_002_jr_8018431C.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve
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build/src/ov_SC03_002/ov_SC03_002.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14
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build/src/ov_SC03_002/ov_SC03_002_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0
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build/src/ov_SC03_002/ov_SC03_002_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18
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@@ -121,6 +121,7 @@ segments:
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- [0x52354, c, ov_SC03_002_jr_8017A4AC]
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- [0x52cd4, c, ov_SC03_002_jr_8017AE2C]
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- [0x554ac, c, ov_SC03_002_jr_8017D604]
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- [0x59c20, c, ov_SC03_002_jr_80181D78]
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- [0x5c1c4, c, ov_SC03_002_jr_8018431C]
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- [0x5d358, data, tail]
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- [0xa1078, .rodata, ov_SC03_002] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
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@@ -165,6 +166,7 @@ segments:
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- [0xa2198, .rodata, ov_SC03_002_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
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- [0xa21ac, .rodata, ov_SC03_002_jr_8017D604] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
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- [0xa21cc, data, tail18]
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- [0xa2210, .rodata, ov_SC03_002_jr_80181D78] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
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- [0xa2234, .rodata, ov_SC03_002_jr_8018431C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
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- [0xa2268, data, tail19]
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- [0xA39F4, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word)
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -3531,7 +3531,287 @@ extern s32 D_801A6B40;
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INCLUDE_ASM("asm/ov_SC04_016/nonmatchings/ov_SC04_016_jr_8017BEBC", func_8017DF8C);
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INCLUDE_ASM("asm/ov_SC04_016/nonmatchings/ov_SC04_016_jr_8017BEBC", func_8017E26C);
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void func_8017E26C() {
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__asm__ __volatile__(".set\tnoreorder\n"
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"addiu $sp, $sp, -88\n"
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"lui $a0, %hi(D_801AC280)\n"
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"addiu $a0, $a0, %lo(D_801AC280)\n"
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"sw $ra, 80($sp)\n"
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"jal func_800547D8\n"
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" addiu $a1, $sp, 16\n"
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"jal func_80052E38\n"
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" addiu $a0, $sp, 16\n"
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"addiu $t9, $sp, 48\n"
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"addiu $t3, $sp, 56\n"
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"addiu $t8, $sp, 68\n"
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"addiu $t6, $zero, 32\n"
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"lui $t2, 255\n"
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"ori $t2, $t2, 65535\n"
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"lui $t5, 65280\n"
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"lui $t1, %hi(D_801A6B40)\n"
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"addiu $t1, $t1, %lo(D_801A6B40)\n"
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"addu $a2, $zero, $zero\n"
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"lui $v1, %hi(D_800A6610)\n"
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"addiu $v1, $v1, %lo(D_800A6610)\n"
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"lui $v0, %hi(D_800B9A02)\n"
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"lhu $v0, %lo(D_800B9A02)($v0)\n"
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"lui $t0, %hi(D_800A5E60)\n"
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"lw $t0, %lo(D_800A5E60)($t0)\n"
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"sll $v0, $v0, 14\n"
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"addu $t7, $v0, $v1\n"
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"addiu $a3, $t0, 18\n"
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".L8017E2D8:\n"
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"lw $v0, 0($t1)\n"
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"nop\n"
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"beqz $v0, .L8017E670\n"
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" nop\n"
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"lui $at, %hi(D_801A6B4A)\n"
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"addu $at, $at, $a2\n"
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"lhu $v0, %lo(D_801A6B4A)($at)\n"
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"nop\n"
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"sh $v0, 48($sp)\n"
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"lui $at, %hi(D_801A6B4E)\n"
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"addu $at, $at, $a2\n"
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"lhu $v0, %lo(D_801A6B4E)($at)\n"
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"nop\n"
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"sh $v0, 50($sp)\n"
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"lui $at, %hi(D_801A6B52)\n"
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"addu $at, $at, $a2\n"
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"lhu $v0, %lo(D_801A6B52)($at)\n"
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"nop\n"
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"sh $v0, 52($sp)\n"
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"lui $at, %hi(D_801A6B6E)\n"
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"addu $at, $at, $a2\n"
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"lhu $v0, %lo(D_801A6B6E)($at)\n"
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"nop\n"
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"sh $v0, 56($sp)\n"
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"lui $at, %hi(D_801A6B72)\n"
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"addu $at, $at, $a2\n"
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"lhu $v0, %lo(D_801A6B72)($at)\n"
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"nop\n"
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"sh $v0, 58($sp)\n"
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"lui $at, %hi(D_801A6B76)\n"
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"addu $at, $at, $a2\n"
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"lhu $v0, %lo(D_801A6B76)($at)\n"
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"nop\n"
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"sh $v0, 60($sp)\n"
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"lui $at, %hi(D_801A6B48)\n"
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"addu $at, $at, $a2\n"
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"lw $v0, %lo(D_801A6B48)($at)\n"
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"lui $at, %hi(D_801A6B78)\n"
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"addu $at, $at, $a2\n"
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"lw $a0, %lo(D_801A6B78)($at)\n"
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"lui $at, %hi(D_801A6B4C)\n"
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"addu $at, $at, $a2\n"
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"lw $v1, %lo(D_801A6B4C)($at)\n"
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"lui $at, %hi(D_801A6B7C)\n"
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"addu $at, $at, $a2\n"
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"lw $a1, %lo(D_801A6B7C)($at)\n"
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"addu $v0, $v0, $a0\n"
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"lui $at, %hi(D_801A6B48)\n"
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"addu $at, $at, $a2\n"
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"sw $v0, %lo(D_801A6B48)($at)\n"
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"lui $at, %hi(D_801A6B50)\n"
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"addu $at, $at, $a2\n"
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"lw $v0, %lo(D_801A6B50)($at)\n"
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"addu $v1, $v1, $a1\n"
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"lui $at, %hi(D_801A6B4C)\n"
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"addu $at, $at, $a2\n"
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"sw $v1, %lo(D_801A6B4C)($at)\n"
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"lui $at, %hi(D_801A6B80)\n"
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"addu $at, $at, $a2\n"
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"lw $v1, %lo(D_801A6B80)($at)\n"
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"lui $at, %hi(D_801A6B44)\n"
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"addu $at, $at, $a2\n"
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"lw $a0, %lo(D_801A6B44)($at)\n"
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"addu $v0, $v0, $v1\n"
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"lui $at, %hi(D_801A6B50)\n"
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"addu $at, $at, $a2\n"
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"sw $v0, %lo(D_801A6B50)($at)\n"
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"bnez $a0, .L8017E46C\n"
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" addiu $v0, $a0, -1\n"
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"lui $at, %hi(D_801A6B6C)\n"
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"addu $at, $at, $a2\n"
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"lw $v0, %lo(D_801A6B6C)($at)\n"
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"lui $at, %hi(D_801A6B78)\n"
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"addu $at, $at, $a2\n"
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"lw $v1, %lo(D_801A6B78)($at)\n"
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"lui $at, %hi(D_801A6B7C)\n"
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"addu $at, $at, $a2\n"
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"lw $a0, %lo(D_801A6B7C)($at)\n"
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"lui $at, %hi(D_801A6B80)\n"
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"addu $at, $at, $a2\n"
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"lw $a1, %lo(D_801A6B80)($at)\n"
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"addu $v0, $v0, $v1\n"
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"lui $at, %hi(D_801A6B6C)\n"
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"addu $at, $at, $a2\n"
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"sw $v0, %lo(D_801A6B6C)($at)\n"
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"lui $at, %hi(D_801A6B70)\n"
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"addu $at, $at, $a2\n"
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"lw $v0, %lo(D_801A6B70)($at)\n"
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"lui $at, %hi(D_801A6B74)\n"
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"addu $at, $at, $a2\n"
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"lw $v1, %lo(D_801A6B74)($at)\n"
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"addu $v0, $v0, $a0\n"
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"addu $v1, $v1, $a1\n"
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"lui $at, %hi(D_801A6B70)\n"
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"addu $at, $at, $a2\n"
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"sw $v0, %lo(D_801A6B70)($at)\n"
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"lui $at, %hi(D_801A6B74)\n"
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"addu $at, $at, $a2\n"
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"sw $v1, %lo(D_801A6B74)($at)\n"
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"j .L8017E478\n"
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" nop\n"
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".L8017E46C:\n"
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"lui $at, %hi(D_801A6B44)\n"
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"addu $at, $at, $a2\n"
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"sw $v0, %lo(D_801A6B44)($at)\n"
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".L8017E478:\n"
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"lui $at, %hi(D_801A6B78)\n"
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"addu $at, $at, $a2\n"
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"lw $v0, %lo(D_801A6B78)($at)\n"
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"lui $at, %hi(D_801A6B84)\n"
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"addu $at, $at, $a2\n"
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"lw $a0, %lo(D_801A6B84)($at)\n"
|
||||
"lui $at, %hi(D_801A6B7C)\n"
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||||
"addu $at, $at, $a2\n"
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||||
"lw $v1, %lo(D_801A6B7C)($at)\n"
|
||||
"lui $at, %hi(D_801A6B88)\n"
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||||
"addu $at, $at, $a2\n"
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||||
"lw $a1, %lo(D_801A6B88)($at)\n"
|
||||
"addu $v0, $v0, $a0\n"
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"lui $at, %hi(D_801A6B78)\n"
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||||
"addu $at, $at, $a2\n"
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"sw $v0, %lo(D_801A6B78)($at)\n"
|
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"lui $at, %hi(D_801A6B80)\n"
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||||
"addu $at, $at, $a2\n"
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||||
"lw $v0, %lo(D_801A6B80)($at)\n"
|
||||
"addu $v1, $v1, $a1\n"
|
||||
"lui $at, %hi(D_801A6B7C)\n"
|
||||
"addu $at, $at, $a2\n"
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||||
"sw $v1, %lo(D_801A6B7C)($at)\n"
|
||||
"lui $at, %hi(D_801A6B8C)\n"
|
||||
"addu $at, $at, $a2\n"
|
||||
"lw $v1, %lo(D_801A6B8C)($at)\n"
|
||||
"lui $at, %hi(D_801A6B78)\n"
|
||||
"addu $at, $at, $a2\n"
|
||||
"lw $a0, %lo(D_801A6B78)($at)\n"
|
||||
"addu $v0, $v0, $v1\n"
|
||||
"lui $at, %hi(D_801A6B80)\n"
|
||||
"addu $at, $at, $a2\n"
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||||
"sw $v0, %lo(D_801A6B80)($at)\n"
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"blez $a0, .L8017E524\n"
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" nop\n"
|
||||
"lui $at, %hi(D_801A6B48)\n"
|
||||
"addu $at, $at, $a2\n"
|
||||
"lw $v1, %lo(D_801A6B48)($at)\n"
|
||||
"lui $at, %hi(D_801A6B54)\n"
|
||||
"addu $at, $at, $a2\n"
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||||
"lw $v0, %lo(D_801A6B54)($at)\n"
|
||||
"j .L8017E544\n"
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" slt $v0, $v0, $v1\n"
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".L8017E524:\n"
|
||||
"lui $at, %hi(D_801A6B48)\n"
|
||||
"addu $at, $at, $a2\n"
|
||||
"lw $v0, %lo(D_801A6B48)($at)\n"
|
||||
"lui $at, %hi(D_801A6B54)\n"
|
||||
"addu $at, $at, $a2\n"
|
||||
"lw $v1, %lo(D_801A6B54)($at)\n"
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||||
"nop\n"
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||||
"slt $v0, $v0, $v1\n"
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".L8017E544:\n"
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"beqz $v0, .L8017E558\n"
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" nop\n"
|
||||
"lui $at, %hi(D_801A6B40)\n"
|
||||
"addu $at, $at, $a2\n"
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||||
"sw $zero, %lo(D_801A6B40)($at)\n"
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||||
".L8017E558:\n"
|
||||
"lw $v0, 0($t1)\n"
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||||
"nop\n"
|
||||
"beqz $v0, .L8017E670\n"
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||||
" nop\n"
|
||||
"lwc2 $0, 0($t9)\n"
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||||
"lwc2 $1, 4($t9)\n"
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||||
"lwc2 $2, 0($t3)\n"
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||||
"lwc2 $3, 4($t3)\n"
|
||||
"lwc2 $4, 0($t3)\n"
|
||||
"lwc2 $5, 4($t3)\n"
|
||||
"nop\n"
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||||
"nop\n"
|
||||
"rtpt\n"
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||||
"addiu $v0, $sp, 64\n"
|
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"cfc2 $t4, $31\n"
|
||||
"nop\n"
|
||||
"sw $t4, 0($v0)\n"
|
||||
"lui $v1, 32645\n"
|
||||
"lw $v0, 64($sp)\n"
|
||||
"ori $v1, $v1, 57344\n"
|
||||
"and $v0, $v0, $v1\n"
|
||||
"bnez $v0, .L8017E670\n"
|
||||
" addiu $v1, $t0, 12\n"
|
||||
"addiu $v0, $t0, 20\n"
|
||||
"swc2 $12, 0($v1)\n"
|
||||
"swc2 $13, 0($v0)\n"
|
||||
"addiu $v1, $sp, 72\n"
|
||||
"addiu $v0, $sp, 76\n"
|
||||
"swc2 $17, 0($t8)\n"
|
||||
"swc2 $18, 0($v1)\n"
|
||||
"swc2 $19, 0($v0)\n"
|
||||
"lw $v1, 68($sp)\n"
|
||||
"lw $v0, 72($sp)\n"
|
||||
"nop\n"
|
||||
"addu $a1, $v1, $v0\n"
|
||||
"bgez $a1, .L8017E5F0\n"
|
||||
" lui $v1, 57600\n"
|
||||
"addiu $a1, $a1, 7\n"
|
||||
".L8017E5F0:\n"
|
||||
"ori $v1, $v1, 32\n"
|
||||
"addiu $v0, $zero, 5\n"
|
||||
"sb $v0, -15($a3)\n"
|
||||
"addiu $v0, $zero, 82\n"
|
||||
"sb $v0, -7($a3)\n"
|
||||
"addiu $v0, $zero, 224\n"
|
||||
"sb $v0, -9($a3)\n"
|
||||
"addiu $v0, $zero, 128\n"
|
||||
"sb $v0, -8($a3)\n"
|
||||
"addiu $v0, $zero, 8\n"
|
||||
"sb $v0, -2($a3)\n"
|
||||
"addiu $v0, $zero, 64\n"
|
||||
"sw $v1, -14($a3)\n"
|
||||
"sb $t6, -10($a3)\n"
|
||||
"sb $v0, -1($a3)\n"
|
||||
"sb $t6, 0($a3)\n"
|
||||
"addiu $a3, $a3, 24\n"
|
||||
"sra $v1, $a1, 3\n"
|
||||
"sll $v1, $v1, 2\n"
|
||||
"addu $v1, $v1, $t7\n"
|
||||
"lw $a0, 0($t0)\n"
|
||||
"lw $v0, 0($v1)\n"
|
||||
"and $a0, $a0, $t5\n"
|
||||
"and $v0, $v0, $t2\n"
|
||||
"or $a0, $a0, $v0\n"
|
||||
"sw $a0, 0($t0)\n"
|
||||
"and $a0, $t0, $t2\n"
|
||||
"lw $v0, 0($v1)\n"
|
||||
"addiu $t0, $t0, 24\n"
|
||||
"and $v0, $v0, $t5\n"
|
||||
"or $v0, $v0, $a0\n"
|
||||
"sw $v0, 0($v1)\n"
|
||||
".L8017E670:\n"
|
||||
"addiu $t1, $t1, 80\n"
|
||||
"lui $v0, %hi(D_801ABB40)\n"
|
||||
"addiu $v0, $v0, %lo(D_801ABB40)\n"
|
||||
"slt $v0, $t1, $v0\n"
|
||||
"bnez $v0, .L8017E2D8\n"
|
||||
" addiu $a2, $a2, 80\n"
|
||||
"lui $at, %hi(D_800A5E60)\n"
|
||||
"sw $t0, %lo(D_800A5E60)($at)\n"
|
||||
"lw $ra, 80($sp)\n"
|
||||
"addiu $sp, $sp, 88\n"
|
||||
".set\treorder\n"
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC04_016/nonmatchings/ov_SC04_016_jr_8017BEBC", func_8017E6A0);
|
||||
|
||||
|
||||
@@ -4346,7 +4346,71 @@ void func_801805E0(void)
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC05_018/nonmatchings/ov_SC05_018_jr_8017D604", func_80180644);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC05_018/nonmatchings/ov_SC05_018_jr_8017D604", func_8018069C);
|
||||
typedef struct {
|
||||
u8 pad0[0x18];
|
||||
u16 f18;
|
||||
u16 f1A;
|
||||
u16 f1C;
|
||||
u8 pad1[0xE];
|
||||
u16 f2C;
|
||||
} Act_8018069C;
|
||||
|
||||
void func_8018069C(s32 a0) {
|
||||
extern s32 D_801E6748;
|
||||
extern s32 D_801AA594;
|
||||
extern u16 D_8018A960[];
|
||||
extern s32 D_801B3DC4;
|
||||
extern s32 D_801BBAB8[];
|
||||
extern s32 D_801C29C4[];
|
||||
extern void func_8012C1B8(void);
|
||||
extern void func_8012CAE4(void *a0);
|
||||
extern void func_8001C214(s32, s32);
|
||||
extern void func_8001D0E8(s32, s32, s32);
|
||||
extern void func_801812FC(void);
|
||||
|
||||
s32 s1;
|
||||
s32 t;
|
||||
u16 v;
|
||||
|
||||
s1 = func_80029504();
|
||||
if ((u32)(s1 - 0x44C) >= 0x46) {
|
||||
goto FAIL;
|
||||
}
|
||||
t = ((s32 (*)(void))func_8012C1B8)();
|
||||
*(s32 *)(a0 + 0x20) = t;
|
||||
if (t == 0) {
|
||||
FAIL:
|
||||
func_8012CAE4((void *)a0);
|
||||
return;
|
||||
}
|
||||
func_8001C214(*(s32 *)(a0 + 0x20), (s32)&D_801AA594);
|
||||
func_8001D0E8(*(s32 *)(a0 + 0x20), 0x7FFF, 0x7FFF);
|
||||
*(u16 *)(*(s32 *)(a0 + 0x20) + 0x2C) =
|
||||
(v = *(u16 *)(*(s32 *)(a0 + 0x20) + 0x2C), D_801E6748 = 0, v | 0x10);
|
||||
*(u16 *)(*(s32 *)(a0 + 0x20) + 0x18) =
|
||||
*(u16 *)(*(s32 *)(a0 + 0x20) + 0x1A) =
|
||||
*(u16 *)(*(s32 *)(a0 + 0x20) + 0x1C) = 0x3000;
|
||||
*(u16 *)(*(s32 *)(a0 + 0x68) + 0xC) = 0x7FFF;
|
||||
if (s1 == 0x488) {
|
||||
*(u16 *)(a0 + 2) = 2;
|
||||
func_8012E8E0(a0, (s32)D_8018A960);
|
||||
((void (*)(s32, s32))func_801812FC)(a0, (s32)&D_801B3DC4);
|
||||
*(s32 *)(a0 + 0x1C) = 0;
|
||||
*(u16 *)(a0 + 0x34) = 0;
|
||||
return;
|
||||
}
|
||||
*(u16 *)(a0 + 2) = 1;
|
||||
func_8012E8E0(a0, (s32)D_8018A960);
|
||||
v = *(u16 *)(a0 + 0xFC) ^ 1;
|
||||
*(u16 *)(a0 + 0xFC) = v;
|
||||
if (v != 0) {
|
||||
((void (*)(s32, s32))func_801812FC)(a0, (s32)D_801BBAB8);
|
||||
} else {
|
||||
((void (*)(s32, s32))func_801812FC)(a0, (s32)D_801C29C4);
|
||||
}
|
||||
*(s32 *)(a0 + 0x1C) = 0;
|
||||
}
|
||||
|
||||
|
||||
void func_801807E8(void *arg0) {
|
||||
extern void (*D_8018A97C[])(void);
|
||||
|
||||
Reference in New Issue
Block a user