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feat(phase-30 S48-T6): propagate func_80181500 to its zero-crack siblings
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Drew T
@@ -3730,7 +3730,156 @@ s32 func_80189D4C(s32 a0, s16 a1, s16 a2) {
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}
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INCLUDE_ASM("asm/ov_SC03_124/nonmatchings/ov_SC03_124_jr_80188544", func_80189F00);
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typedef struct { s16 vx, vy; } DVEC2_C974_8017BA3C_80189F00;
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typedef struct { s16 vx, vy, vz, pad; } SVEC2_C974_8017BA3C_80189F00;
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typedef struct { s16 m[3][3]; s32 t[3]; } MTX_C974_80189F00;
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/* func_80189F00 -- ov_SC03_107 / ov_SC03_107_jr_801789AC (212 ins)
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*
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* Decls chosen to agree VERBATIM with the destination TU
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* (src/ov_SC03_107/ov_SC03_107_jr_801789AC.c):
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* func_8002D4C8 TU:168/3781/5786/5823/6444/8084 `extern void (s32,s32)` (also `(int,int)` @999)
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* func_8012B030 TU:357/4991 `extern s32 (u8 *)`
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* func_8012CBCC TU:452 `extern void (s32)`, TU:631 `extern void (s32)`
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* -> VOID in the TU, so the return value is read through the
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* §161c function-pointer cast, never through a re-decl.
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* func_80131C78 TU:565 `extern void (s32)`
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* func_80143B6C TU:581/1143 `extern s32 (s32,s32)`
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* func_800291C8 TU:983 `extern void (s32,s32)`
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* func_80189D4C DEFINED at TU:7981 as `s32 func_80189D4C(s32,s16,s16)` --
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* the definition is above this slot, so the decl below agrees.
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* D_801E2440 / D_801E2444 are declared nowhere in the TU (free choice).
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*/
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extern void func_8002D4C8(s32 a0, s32 a1);
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extern s32 func_8012B030(u8 *a0);
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extern void func_8012CBCC(s32);
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extern void func_80131C78(s32 a0);
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extern s32 func_80143B6C(s32 a0, s32 a1);
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extern void func_800291C8(s32, s32);
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extern s32 func_80189D4C(s32 a0, s16 a1, s16 a2);
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void func_80189F00(s32 a0) {
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extern s32 D_801E2440;
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extern s32 D_801E2444;
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/* §162i1 dead-local pad: target frame 0x28 = args 0x10 + vars 0x10 + 4*2 regs;
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* the raw draft compiles vars=0. Never read, never &-taken, >=2 elements. */
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s32 pad[4];
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if (*(s16 *)(a0 + 0xA) >= 0x10) {
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func_80131C78(a0);
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*(s16 *)(a0 + 0x2) = 2;
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*(s32 *)(a0 + 0x1C) = 1;
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}
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switch (*(u8 *)(a0 + 0xC2)) {
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case 0:
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D_801E2440 = ((s32 (*)(s32))func_8012CBCC)(a0);
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if (D_801E2440 & 0x6000) {
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if (D_801E2440 & 0x1000) {
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*(s16 *)(a0 + 0x2) = 2;
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*(u8 *)(a0 + 0xC1) = 0;
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*(s16 *)(a0 + 0x5E) = 0;
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*(s32 *)(a0 + 0x1C) = 0x30;
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func_8002D4C8(0x531, 0);
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func_800291C8(0xA, *(s16 *)(a0 + 0xFE));
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return;
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}
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func_80143B6C(a0, 1);
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func_8002D4C8(0x754, 0);
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*(u8 *)(a0 + 0xC2) = 1;
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*(s32 *)(a0 + 0x14) = 0xFFF30000;
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*(s32 *)(a0 + 0x1C) = 0;
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*(s32 *)(a0 + 0x10) = *(s32 *)(a0 + 0x10) >> 2;
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*(s32 *)(a0 + 0x18) = *(s32 *)(a0 + 0x18) >> 2;
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}
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*(s32 *)(a0 + 0x1C) += 1;
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if (*(s32 *)(a0 + 0x1C) >= 0x78) {
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func_80131C78(a0);
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*(s16 *)(a0 + 0x2) = 2;
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*(s32 *)(a0 + 0x1C) = 1;
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}
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break;
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case 1:
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D_801E2444 = *(s32 *)(a0 + 0x14);
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D_801E2440 = ((s32 (*)(s32))func_8012CBCC)(a0);
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if (D_801E2440 & 0x6000) {
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if (D_801E2440 & 0x1000) {
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*(s16 *)(a0 + 0x2) = 2;
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*(u8 *)(a0 + 0xC1) = 0;
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*(s16 *)(a0 + 0x5E) = 0;
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*(s32 *)(a0 + 0x1C) = 0x30;
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func_8002D4C8(0x531, 0);
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func_800291C8(0xA, *(s16 *)(a0 + 0xFE));
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return;
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}
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{
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/* The read of D_801E2444 MUST precede the two pointer stores in the
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* source: gcc-2.7.2's scheduler cannot hoist a symbol_ref load above a
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* store through a register base (may-alias), so writing it inline in the
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* `-D_801E2444` expression leaves the load-delay slot unfilled -> a nop,
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* and the function is 1 instruction long. */
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s32 t;
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func_8002D4C8(0x754, 0);
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func_80143B6C(a0, 1);
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t = D_801E2444;
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*(u8 *)(a0 + 0xC2) = 2;
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*(s32 *)(a0 + 0x1C) = 0;
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*(s32 *)(a0 + 0x14) = -t;
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}
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}
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*(s32 *)(a0 + 0x1C) += 1;
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if (*(s32 *)(a0 + 0x1C) >= 0x28) {
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func_80131C78(a0);
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*(s16 *)(a0 + 0x2) = 2;
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*(s32 *)(a0 + 0x1C) = 1;
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}
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break;
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case 2:
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*(s32 *)(a0 + 0x10) = *(s32 *)(a0 + 0x10) * 15 / 16;
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*(s32 *)(a0 + 0x18) = *(s32 *)(a0 + 0x18) * 15 / 16;
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D_801E2440 = ((s32 (*)(s32))func_8012CBCC)(a0);
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if (D_801E2440 & 0x6000) {
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*(s32 *)(a0 + 0x14) = 0;
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if (D_801E2440 & 0x1000) {
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*(s16 *)(a0 + 0x2) = 2;
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*(u8 *)(a0 + 0xC1) = 0;
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*(s16 *)(a0 + 0x5E) = 0;
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*(s32 *)(a0 + 0x1C) = 0x30;
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func_8002D4C8(0x531, 0);
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func_800291C8(0xA, *(s16 *)(a0 + 0xFE));
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return;
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}
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if (!(*(u16 *)(a0 + 0x84) & 1)) {
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*(u16 *)(a0 + 0x84) |= 1;
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func_8002D4C8(0x754, 0);
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}
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if ((*(s32 *)(a0 + 0x1C) & 3) == 3) {
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func_80143B6C(a0, 1);
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}
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*(s32 *)(a0 + 0x1C) += 1;
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if (*(s32 *)(a0 + 0x1C) >= 0x11) {
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func_80131C78(a0);
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func_8012B030((u8 *)a0);
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*(s16 *)(a0 + 0x2) = 1;
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*(u16 *)(a0 + 0x84) &= 0xFFFE;
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}
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}
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break;
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}
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func_80189D4C(a0, -0x28, 1);
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*(s16 *)(a0 + 0x108) = *(u16 *)(a0 + 0x108) - 1;
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if (*(s16 *)(a0 + 0x108) == 0) {
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func_800291C8(0xA, *(s16 *)(a0 + 0xFE));
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}
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}
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INCLUDE_ASM("asm/ov_SC03_124/nonmatchings/ov_SC03_124_jr_80188544", func_8018A250);
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