mirror of
https://github.com/Druthulu/BFM-decomp
synced 2026-09-27 05:56:00 -04:00
feat(phase-21): worker gate — +6 fns x0 propagated (fleet 63.18%)
This commit is contained in:
Drew T
@@ -225,7 +225,70 @@ void func_8013D330(void) {
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}
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INCLUDE_ASM("asm/ov_SC01_077/nonmatchings/ov_SC01_077", func_8013D3D4);
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// @class: regalloc-order
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// @stuck: none — MATCH (match_one 90/90); base &D_80078E78 cached in a pointer local so gcc pins it into callee-saved $s1 and hoists the addr to the prologue (live across all 4 calls); direct array access D_80078E78[0x37] instead folds %lo per use (no $s1, frame 0x18 not 0x20)
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extern u8 D_80078E78[];
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extern void *D_801D9570;
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extern void *D_801D9574;
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extern void *D_801D9578;
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extern s32 D_801D95A0;
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extern s32 D_801D95A4;
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extern s32 D_801D95A8;
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extern s32 D_801DAA14[];
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extern u8 D_8018735C[];
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extern u8 D_80187404[];
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extern u8 D_801872B4[];
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extern u8 D_801873B0[];
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extern u8 D_80187430[];
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extern u8 D_80187308[];
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extern void func_8013D53C(void);
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extern void func_8013DD68(void);
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extern void func_8013D8FC(void);
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extern void func_8013CF68(void);
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void func_8013D3D4(int param_1, int param_2)
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{
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u8 *p = D_80078E78;
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D_801D95A0 = param_2;
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D_801D95A4 = (param_2 >> 2) & 3;
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D_801D95A8 = (param_2 >> 4) & 1;
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if (((param_2 >> 2) & 3) == 0) {
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D_801D9570 = D_8018735C;
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D_801D9574 = D_80187404;
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D_801D9578 = D_801872B4;
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} else {
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D_801D9570 = D_801873B0;
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D_801D9574 = D_80187430;
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D_801D9578 = D_80187308;
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}
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func_8013D53C();
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if ((param_2 & 1) != 0) {
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if (D_801D95A8 != 0) {
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func_8013DD68();
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} else {
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func_8013D8FC();
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}
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func_8013CF68();
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if ((D_801D95A0 & 2) != 0) {
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D_801DAA14[0] = 0x140;
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D_801DAA14[3] = 0x80;
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if (p[0x37] == 4) {
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D_801DAA14[0] = 0x140;
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D_801DAA14[3] = 0;
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}
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if (p[0x37] == 0) {
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D_801DAA14[0] = 0x140;
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D_801DAA14[3] = 0x80;
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}
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}
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}
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}
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INCLUDE_ASM("asm/ov_SC01_077/nonmatchings/ov_SC01_077", func_8013D53C);
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@@ -269,7 +332,92 @@ void func_8013D8FC(void)
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INCLUDE_ASM("asm/ov_SC01_077/nonmatchings/ov_SC01_077", func_8013D9B0);
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INCLUDE_ASM("asm/ov_SC01_077/nonmatchings/ov_SC01_077", func_8013DBE4);
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// @class: struct
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// @stuck: none — MATCH (match_one 97/97). Two levers: (1) offset-first pointer arith
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// `(int*)(param_1*12 + (int)D_801D9578)` makes the addu `offset+base` (dest=v0) so x/y/z
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// load into a0/a1/a2 and each global loads LATE into v1 (base-first gave addu dest=v1 →
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// global hoisted into a0, shifting x/y/z to a1/a2/a3). (2) the clamp must be NESTED
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// if/else (slti dup'd inside each <,>= branch), NOT a merged `if(diff<5)` after the
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// branch — gcc cross-jumps the identical `G=x` and `G=t` store tails into the two shared
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// sites; the merged form emits one slti + unconditional store and diverges.
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extern void *D_801D9578;
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extern s16 *D_801D957C;
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extern s32 D_801D958C;
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extern s32 D_801D95AC;
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extern s32 D_801D95B0;
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extern s32 D_801D95B4;
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extern void func_8013DD68(void);
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void func_8013DBE4(int param_1)
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{
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int *p;
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int x, y, z;
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int flag;
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if (D_801D957C != 0) {
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D_801D958C = 0;
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p = (int *)(param_1 * 12 + (int)D_801D9578);
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x = p[0];
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y = p[1];
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z = p[2];
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flag = 0;
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if (D_801D95AC != x) {
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flag = 1;
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if (D_801D95AC < x) {
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if (x - D_801D95AC < 5) {
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D_801D95AC = x;
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} else {
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D_801D95AC = D_801D95AC + 4;
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}
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} else {
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if (D_801D95AC - x < 5) {
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D_801D95AC = x;
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} else {
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D_801D95AC = D_801D95AC - 4;
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}
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}
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}
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if (D_801D95B0 != y) {
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flag = 1;
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if (D_801D95B0 < y) {
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if (y - D_801D95B0 < 5) {
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D_801D95B0 = y;
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} else {
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D_801D95B0 = D_801D95B0 + 4;
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}
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} else {
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if (D_801D95B0 - y < 5) {
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D_801D95B0 = y;
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} else {
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D_801D95B0 = D_801D95B0 - 4;
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}
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}
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}
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if (D_801D95B4 != z) {
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flag = 1;
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if (D_801D95B4 < z) {
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if (z - D_801D95B4 < 5) {
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D_801D95B4 = z;
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} else {
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D_801D95B4 = D_801D95B4 + 4;
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}
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} else {
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if (D_801D95B4 - z < 5) {
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D_801D95B4 = z;
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} else {
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D_801D95B4 = D_801D95B4 - 4;
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}
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}
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}
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if (flag != 0) {
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func_8013DD68();
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}
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D_801D958C = flag;
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}
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}
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INCLUDE_ASM("asm/ov_SC01_077/nonmatchings/ov_SC01_077", func_8013DD68);
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@@ -383,7 +531,60 @@ void func_8013E5E8(void)
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DEFINE_func_8013E67C() /* dedup: shared engine-core @0x8013E67C (src/shared) */
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INCLUDE_ASM("asm/ov_SC01_077/nonmatchings/ov_SC01_077", func_8013E6AC);
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// @class: regalloc-order
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// @stuck: none — MATCH (90 ins, relocation-masked)
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extern u8 D_80078EC0;
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extern u16 D_8011511A;
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extern u16 D_80115124;
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extern u8 D_80115148[];
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extern u8 D_80115140[];
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extern s32 D_80187EBC;
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extern u16 D_80115110;
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extern s32 D_80115188;
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extern s16 currentLocationId;
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extern s16 D_80187E94;
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extern s16 D_80187E96;
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extern unsigned short D_80115112;
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extern void func_8013E83C(void);
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extern s32 func_80029504(void);
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void func_8013E6AC(void) {
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short i;
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func_8013E83C();
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D_8011511A = 0;
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D_80115124 = D_80078EC0;
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for (i = 0; i < 8; i++) {
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*(s16 *)((char *)&D_80115148 + (i << 1)) = 0;
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D_80115140[i] = 0;
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}
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if (!((u32)func_80029504() < 5 || currentLocationId == 0x302A || currentLocationId == 0x3073)) {
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register s32 *ep __asm__("$8");
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register s32 *fp __asm__("$9");
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fp = (s32 *)&D_80115110;
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ep = (s32 *)&D_80187EBC;
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for (i = 0; i < 5; i++) {
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register s32 *fa __asm__("$6");
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s32 v;
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fa = (s32 *)(i * 4 + (s32)fp);
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v = ep[i] * 3 >> 2;
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fa[0x16] = v;
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*(s32 *)((char *)&D_80115188 + (i << 2)) = v;
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}
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D_80187E94 = 2;
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D_80187E96 = 1;
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{ u16 *q = &D_80115112; *q += 1; }
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} else {
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func_8013E83C();
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D_8011511A = 7;
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D_80187E96 = 0;
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D_80187E94 = 0;
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D_80115112 = 6;
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}
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}
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DEFINE_func_8013E814() /* dedup: shared engine-core @0x8013E814 (src/shared) */
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@@ -447,7 +648,63 @@ INCLUDE_ASM("asm/ov_SC01_077/nonmatchings/ov_SC01_077", func_8014032C);
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INCLUDE_ASM("asm/ov_SC01_077/nonmatchings/ov_SC01_077", func_80140608);
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INCLUDE_ASM("asm/ov_SC01_077/nonmatchings/ov_SC01_077", func_801407F4);
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// @class: iv-combine
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// @stuck: none — MATCH (89 ins). Sequential struct fields fed from a running source
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// pointer compile to fixed offsets when written base[0..n]; the target advances
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// the pointer, so use post-increment `*p++` for EVERY field (gcc drops the dead
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// final increment, yielding the "increment N-2 then offset 0/2" tail).
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extern u8 *D_80187B74;
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extern u8 *D_80187B78;
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extern u8 *D_80187B7C;
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extern u8 *D_80187B80;
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extern u8 *D_80187B84;
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extern u16 *D_80187B88[];
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extern u16 *D_80187B90[];
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extern u16 *D_80187BB0[];
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extern s32 func_80028D58(void);
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extern s32 func_80028DE0(void);
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extern s32 func_80028FBC(void);
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extern s32 func_80029000(void);
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extern s32 func_80028D9C(void);
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void func_801407F4(void)
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{
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u8 *puVar1;
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s32 iVar2;
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u16 *puVar3;
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puVar1 = D_80187B74;
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iVar2 = func_80028D58();
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puVar3 = D_80187B88[iVar2];
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*(s16 *)(puVar1 + 0x16) = *puVar3++;
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*(s16 *)(puVar1 + 0x18) = *puVar3++;
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*(s16 *)(puVar1 + 0x1a) = *puVar3++;
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puVar1 = D_80187B78;
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iVar2 = func_80028DE0();
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puVar3 = D_80187B88[iVar2];
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*(s16 *)(puVar1 + 0x16) = *puVar3++;
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*(s16 *)(puVar1 + 0x18) = *puVar3++;
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*(s16 *)(puVar1 + 0x1a) = *puVar3++;
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iVar2 = func_80028FBC();
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*(s16 *)(D_80187B7C + 0x18) = *D_80187B90[iVar2];
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iVar2 = func_80029000();
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*(s16 *)(D_80187B80 + 0x18) = *D_80187B90[iVar2];
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puVar1 = D_80187B84;
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iVar2 = func_80028D9C();
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puVar3 = D_80187BB0[iVar2];
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*(s16 *)(puVar1 + 0x12) = *puVar3++;
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*(s16 *)(puVar1 + 0x14) = *puVar3++;
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*(s16 *)(puVar1 + 0x16) = *puVar3++;
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*(s16 *)(puVar1 + 0x18) = *puVar3++;
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*(s16 *)(puVar1 + 0x1a) = *puVar3++;
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*(s16 *)(puVar1 + 0x1c) = *puVar3++;
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}
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INCLUDE_ASM("asm/ov_SC01_077/nonmatchings/ov_SC01_077", func_80140958);
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@@ -11393,7 +11650,56 @@ s32 func_8017F424(s16 *a0) {
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return D_8018A89C[(u16)a0[1]]();
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}
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INCLUDE_ASM("asm/ov_SC01_077/nonmatchings/ov_SC01_077", func_8017F460);
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// @class: remat
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// @stuck: none — MATCH (match_one 87/87). Levers: (1) block-scoped `s32 *pCC=&D_801270CC;` INSIDE
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// the ==4 branch forces gcc to CSE/HOLD the symbol address in a reg for the load+conditional store
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// (target: lui;addiu;lw 0($v1) ... sw 0($v1)) instead of %lo-folding each access; declaring it at
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// function top materializes it too early (before the bne) — must be block-scoped so it builds lazily.
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// (2) (s16)D_80126B66 on the u16 canonical folds to lh. (3) extern short D_8018A8FC[]; D_8018A8FC[idx]
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// %lo-folds the indexed s16 load.
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extern s32 D_801270CC;
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extern s32 D_801270D4;
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extern short D_8018A8FC[];
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extern int D_8018A8F8;
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extern u16 D_80126B66;
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extern void func_8017F5BC(int param_1);
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extern void func_8002D4C8(s32 a0, s32 a1);
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void func_8017F460(int param_1)
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{
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int iVar1;
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if (*(unsigned char *)(param_1 + 0x70) == 4) {
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s32 *pCC = &D_801270CC;
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if (*pCC == 0 && (*(unsigned short *)(param_1 + 0x5c) & 1) != 0) {
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if (D_801270D4 == 0) {
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D_801270D4 = 1;
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}
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*pCC = 3;
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*(unsigned short *)(param_1 + 0x5c) = 0;
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}
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if (1 < D_801270CC) {
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if ((*(unsigned short *)(param_1 + 0x5c) & 1) != 0 && D_801270D4 == 0) {
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D_801270D4 = 1;
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}
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if (D_8018A8FC[(int)((unsigned int)*(unsigned short *)(param_1 + 0x70) << 0x10) >> 0x18] <= D_801270D4) {
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func_8017F5BC(param_1);
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func_8002D4C8(0x495, 0);
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}
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}
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} else {
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iVar1 = (int)(s16)D_80126B66 - (int)*(short *)(param_1 + 0xe);
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if (iVar1 < 0) {
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iVar1 = -iVar1;
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}
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if (iVar1 < D_8018A8F8) {
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func_8017F5BC(param_1);
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}
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}
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}
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// @class: regalloc-order
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// @stuck: none — MATCH (54 ins, relocation-masked)
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@@ -12495,7 +12801,77 @@ void func_801846F8(s32 a0) {
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*(s32 *)(a0 + 0x1C) = 0x14;
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}
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INCLUDE_ASM("asm/ov_SC01_077/nonmatchings/ov_SC01_077", func_8018470C);
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||||
// @class: regalloc-order
|
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// @stuck: none — MATCH (97 ins, relocation-masked); $s0=&spr (call-crossing) + $s1=param_1 fell out naturally (no pins needed); frame 0x40 from svec(8)+spr(20)
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||||
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typedef struct { u16 a, b, c, d; } SV4U;
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||||
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||||
struct sprite8 {
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short f0; /* +0x00 */
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short f2; /* +0x02 */
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short f4; /* +0x04 */
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short f6; /* +0x06 */
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||||
short f8; /* +0x08 */
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short fa; /* +0x0a */
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||||
short fc; /* +0x0c */
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short fe; /* +0x0e */
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int f10; /* +0x10 (unwritten, reserved -> 20-byte struct => frame 0x40) */
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};
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extern s32 func_8012D5E4(s32 a0, s32 a1, s32 a2, s32 a3);
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||||
extern void func_8012F214(s32 a0, s32 a1, s32 a2);
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||||
extern s32 func_8012C51C(void *a0, s32 a1);
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extern s32 func_8012BEE8(s32 a0);
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extern void func_8012A828(s32 a0, void *a1);
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extern void func_8002D4C8(s32 a0, s32 a1);
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||||
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extern u8 D_8018AF78;
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extern u8 D_8018AF88;
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extern volatile unsigned short D_80126B96;
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extern void D_80196F3C;
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||||
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void func_8018470C(s32 param_1)
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{
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||||
SV4U svec; /* sp+0x10 */
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||||
struct sprite8 spr; /* sp+0x18 */
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||||
s32 base;
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||||
u16 uVar1;
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||||
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||||
if (*(int *)(param_1 + 0x1c) == 9) {
|
||||
base = (s32)&D_8018AF78;
|
||||
if (func_8012D5E4(param_1, base, base + 8, 9) != 0
|
||||
&& (*(unsigned short *)(param_1 + 0x70) & 1) != 0) {
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||||
D_80126B96 = D_80126B96 | 0x800;
|
||||
}
|
||||
if ((*(short *)(param_1 + 0x70) & 0x8000) != 0) {
|
||||
func_8012F214(param_1, (s32)&D_8018AF88, (s32)&svec);
|
||||
spr.f6 = 0xda;
|
||||
spr.fa = 0;
|
||||
spr.fc = 0x7fff;
|
||||
spr.f0 = svec.a;
|
||||
spr.f2 = svec.b;
|
||||
spr.f4 = svec.c;
|
||||
spr.fe = *(u16 *)(*(int *)(param_1 + 0x20) + 0x12);
|
||||
func_8012C51C(&spr, param_1);
|
||||
spr.fe = *(u16 *)(*(int *)(param_1 + 0x20) + 0x12) + 0x100;
|
||||
func_8012C51C(&spr, param_1);
|
||||
spr.fe = *(u16 *)(*(int *)(param_1 + 0x20) + 0x12) - 0x100;
|
||||
func_8012C51C(&spr, param_1);
|
||||
}
|
||||
func_8002D4C8(0x43e, 0);
|
||||
}
|
||||
if (func_8012BEE8(param_1) != 0) {
|
||||
*(int *)(param_1 + 0x1c) = 0x3c;
|
||||
*(short *)(param_1 + 2) = 3;
|
||||
func_8012A828(param_1, &D_80196F3C);
|
||||
uVar1 = *(u16 *)(*(int *)(param_1 + 0x78) + 2);
|
||||
*(short *)(param_1 + 0x5e) = 0;
|
||||
*(short *)(param_1 + 0xdc) = 0;
|
||||
*(int *)(param_1 + 0x1c) = 0x2d;
|
||||
*(short *)(param_1 + 0x5c) = uVar1;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
extern s32 (*D_8018AF90[])();
|
||||
|
||||
|
||||
Reference in New Issue
Block a user