mirror of
https://github.com/Druthulu/BFM-decomp
synced 2026-09-26 13:33:34 -04:00
phase-36: S105 s105_f5 — func_8018FB8C banked at 0 through the whole-object gate + propagated — f5 plain C (the set-once chain; the addu lever was a0v = 0)
This commit is contained in:
Drew T
+182
-182
@@ -1,7 +1,7 @@
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{
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"head": "04a26686e",
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"aliases": [
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@@ -21,207 +21,207 @@
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|
||||
},
|
||||
"ok": true,
|
||||
"seconds": 2.2
|
||||
"seconds": 2.3
|
||||
}
|
||||
|
||||
@@ -29604,3 +29604,4 @@
|
||||
{"ts": "2026-09-11 13:18:32", "label": "s105_f5", "rung": "E", "calib": {"head": "d49b4fc37", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC02_005/ov_SC02_005_jr_8018EA04.c", "fn": "func_8018F944", "addr": 2149120324, "aliases": null, "header": false, "includers": 0, "nhash_before": "d8333e50237534228a2fcdf5e4844f1b17416671", "nhash_after": "74ac69c4aa6b893bba101ac48f32a56f018b9938", "source": ".run/P36/agents/ov_SC02_005__func_8018F944/body.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.072, "objects": ["build/src/ov_SC02_005/ov_SC02_005_jr_8018EA04.o"], "before_text": "void func_8018F944(void *a0)\n{\n s32 v0;\n s32 eac;\n s32 *s0;\n register s32 a0v __asm__(\"$4\"); // !FAKE: pin $4 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n\n v0 = *(s32 *)((u8 *)a0 + 0x1C) - 1;\n *(s32 *)((u8 *)a0 + 0x1C) = v0;\n if (v0 != 0) {\n return;\n }\n\n *(s16 *)((u8 *)a0 + 0x2) = 4;\n __asm__(\"la %0, D_800A5E88\" : \"=r\"(s0)); // !FAKE: instruction la \u2014 NEEDED DIFFERS (P36 rung B tus9)\n s0[0] = 0;\n D_800A5E8C = -4;\n D_800A5E90 = -4;\n D_800A5E94 = 0xFF;\n D_800A5E95 = 0x4C;\n D_800A5E96 = 0;\n func_80028620(0, s0);\n\n D_800A5EA0 = -0xE;\n D_800A5EA5 = 0;\n func_80028620(1, &s0[4]);\n\n a0v = 2;\n eac = 0xA;\n s0[8] = 0;\n __asm__ __volatile__(\"\" ::: \"memory\"); // !FAKE: barrier memory \u2014 NEEDED DIFFERS (P36 rung B tus9)\n D_800A5EAC = eac;\n D_800A5EB0 = eac;\n D_800A5EB4 = 0xCC;\n D_800A5EB5 = 0x99;\n D_800A5EB6 = 0x99;\n func_80028620(a0v, &s0[8]);\n}\n", "after_text": "void func_8018F944(void *a0)\n{\n s32 v0;\n s32 *s0;\n s32 *p;\n\n v0 = *(s32 *)((u8 *)a0 + 0x1C) - 1;\n *(s32 *)((u8 *)a0 + 0x1C) = v0;\n if (v0 != 0) {\n return;\n }\n\n *(s16 *)((u8 *)a0 + 0x2) = 4;\n s0 = &D_800A5E88;\n s0[0] = 0;\n D_800A5E8C = -4;\n D_800A5E90 = -4;\n D_800A5E94 = 0xFF;\n D_800A5E95 = 0x4C;\n D_800A5E96 = 0;\n func_80028620(0, s0);\n\n D_800A5EA0 = -0xE;\n D_800A5EA5 = 0;\n func_80028620(1, &s0[4]);\n\n p = &s0[8];\n *p = 0;\n D_800A5EAC = 0xA;\n D_800A5EB0 = 0xA;\n D_800A5EB4 = 0xCC;\n D_800A5EB5 = 0x99;\n D_800A5EB6 = 0x99;\n func_80028620(2, p);\n}\n"}
|
||||
{"ts": "2026-09-11 13:18:49", "label": "s105_f5", "rung": "E", "calib": {"head": "855743df1", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC02_005/ov_SC02_005_jr_8018EA04.c", "fn": "func_801900B0", "addr": 2149122224, "aliases": null, "header": false, "includers": 0, "nhash_before": "d3895b0a7a94c21a46bd66eacb00356221d4fda9", "nhash_after": "a856234681a948aa126caf430bed58d3b9a7b6dd", "source": ".run/P36/agents/ov_SC02_005__func_801900B0/body.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.069, "objects": ["build/src/ov_SC02_005/ov_SC02_005_jr_8018EA04.o"], "before_text": "s32 func_801900B0(void) {\n register s32 r __asm__(\"$2\"); // !FAKE: pin $2 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n s32 v;\n\n v = ((s32 (*)(void))func_800CF854)();\n r = v ? 9 : 8;\n return r;\n}\n", "after_text": "s32 func_801900B0(void) {\n s32 v;\n\n v = ((s32 (*)(void))func_800CF854)();\n if (!v) {\n return 8;\n }\n return 9;\n}\n"}
|
||||
{"ts": "2026-09-11 13:19:07", "label": "s105_f5", "rung": "E", "calib": {"head": "04a26686e", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC02_005/ov_SC02_005_jr_8018EA04.c", "fn": "func_8018FA34", "addr": 2149120564, "aliases": null, "header": false, "includers": 0, "nhash_before": "f728c15a70ebe01f901e27eb020744295690e603", "nhash_after": "f71de903fa387590327c3f6ea39ebd7a6ebad57a", "source": ".run/P36/agents/ov_SC02_005__func_8018FA34/body.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.07, "objects": ["build/src/ov_SC02_005/ov_SC02_005_jr_8018EA04.o"], "before_text": "void func_8018FA34(s32 *a0)\n{\n s32 v0;\n s32 *s0;\n s32 *s1;\n /* Pin the 2nd func_80028620's first-arg (0) to its hard call reg so it\n * materializes as a real SET (survives cse/const-prop), and pair it with\n * the zero-byte scheduling barriers below. Without these, gcc-2.7.2's\n * sched1 sinks the independent addr-calc / const-0 arg-setup PAST the\n * rand()-result andi/addiu chain (S2-adjacent \"class3 tie\" residual,\n * cookbook \u00a725 / gcc-2.7.2-map/sched.md S1/S6); the target schedules\n * each independent op BEFORE the dependent chain that follows it. */\n register s32 a0v __asm__(\"$4\"); // !FAKE: pin $4 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n\n s1 = a0;\n v0 = rand();\n s0 = (s32 *)&D_800A5E88;\n __asm__ __volatile__(\"\" ::: \"memory\"); // !FAKE: barrier memory \u2014 NEEDED DIFFERS (P36 rung B tus9)\n v0 &= 0x1F;\n v0 -= 0x10;\n s0[0] = v0;\n\n v0 = rand();\n a0v = 0;\n __asm__ __volatile__(\"\" ::: \"memory\"); // !FAKE: barrier memory \u2014 NEEDED DIFFERS (P36 rung B tus9)\n v0 &= 0x1F;\n v0 -= 0x14;\n D_800A5E90 = v0;\n\n func_80028620(a0v, s0);\n\n if (D_801270C8 != 0xA) {\n return;\n }\n\n *(s16 *)((u8 *)s1 + 0x2) = 0x5;\n D_800A5EA0 = 0xE;\n func_80028620(1, &s0[4]);\n\n D_800A5EB0 = -0xA;\n func_80028620(2, &s0[8]);\n}\n", "after_text": "void func_8018FA34(s32 *a0)\n{\n s32 *s0;\n s32 *s1;\n s32 v0;\n\n s1 = a0;\n s0 = &D_800A5E88;\n\n v0 = rand();\n s0[0] = (v0 & 0x1F) - 0x10;\n\n v0 = rand();\n D_800A5E90 = (v0 & 0x1F) - 0x14;\n\n func_80028620(0, s0);\n\n if (D_801270C8 == 0xA) {\n *(s16 *)((u8 *)s1 + 2) = 5;\n D_800A5EA0 = 0xE;\n func_80028620(1, (void *)((u8 *)s0 + 0x10));\n D_800A5EB0 = -0xA;\n func_80028620(2, (void *)((u8 *)s0 + 0x20));\n }\n}\n"}
|
||||
{"ts": "2026-09-11 13:19:24", "label": "s105_f5", "rung": "E", "calib": {"head": "7f33a7510", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC02_005/ov_SC02_005_jr_8018EA04.c", "fn": "func_8018FB8C", "addr": 2149120908, "aliases": null, "header": false, "includers": 0, "nhash_before": "83c2c8274c551d5d0f4cbd91aeef7bef92f21d1f", "nhash_after": "0a2d40f027a03ba0fd4f9016d6d90efb6b3a1f1b", "source": ".run/P36/agents/ov_SC02_005__func_8018FB8C/body.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.069, "objects": ["build/src/ov_SC02_005/ov_SC02_005_jr_8018EA04.o"], "before_text": "void func_8018FB8C(void *a0) {\n s32 *s0;\n register s32 a0v __asm__(\"a0\"); // !FAKE: pin a0 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n s32 *s1 = (s32 *)a0;\n s32 tmp;\n\n tmp = rand();\n s0 = (s32 *)&D_800A5E88;\n tmp = (tmp & 0x1F) - 0x10;\n s0[0] = tmp;\n tmp = rand();\n __asm__(\"addu %0,$zero,$zero\" : \"=r\"(a0v)); // !FAKE: instruction addu \u2014 REFUSED instruction `addu` has no C spelling in the table (P36 rung B tus9)\n tmp = (tmp & 0x1F) - 0x14;\n D_800A5E90 = tmp;\n\n func_80028620(a0v, s0);\n\n if (D_801270C8 == 0xC) {\n *(s16 *)((s8 *)s1 + 2) = 0x7;\n D_800A5EA0 = 0xE;\n func_80028620(1, (void *)((s32)s0 + 0x10));\n __asm__(\"\" : \"=r\"(s0) : \"0\"(s0)); // !FAKE: launder \u2014 NEEDED DIFFERS (P36 rung B tus9)\n D_800A5EB0 = -0xA;\n func_80028620(2, (void *)((s32)s0 + 0x20));\n }\n}\n", "after_text": "void func_8018FB8C(void *a0) {\n s32 *s0;\n s32 *s1;\n s32 tmp;\n\n s1 = (s32 *)a0;\n s0 = &D_800A5E88;\n\n tmp = rand();\n s0[0] = (tmp & 0x1F) - 0x10;\n\n tmp = rand();\n D_800A5E90 = (tmp & 0x1F) - 0x14;\n\n func_80028620(0, s0);\n\n if (D_801270C8 == 0xC) {\n *(s16 *)((u8 *)s1 + 2) = 7;\n D_800A5EA0 = 0xE;\n func_80028620(1, (void *)((u8 *)s0 + 0x10));\n D_800A5EB0 = -0xA;\n func_80028620(2, (void *)((u8 *)s0 + 0x20));\n }\n}\n"}
|
||||
|
||||
@@ -4376,28 +4376,26 @@ extern s32 D_800A5EB0;
|
||||
|
||||
void func_8018FB8C(void *a0) {
|
||||
s32 *s0;
|
||||
register s32 a0v __asm__("a0"); // !FAKE: pin a0 — NEEDED DIFFERS (P36 rung B tus9)
|
||||
s32 *s1 = (s32 *)a0;
|
||||
s32 *s1;
|
||||
s32 tmp;
|
||||
|
||||
tmp = rand();
|
||||
s0 = (s32 *)&D_800A5E88;
|
||||
tmp = (tmp & 0x1F) - 0x10;
|
||||
s0[0] = tmp;
|
||||
tmp = rand();
|
||||
__asm__("addu %0,$zero,$zero" : "=r"(a0v)); // !FAKE: instruction addu — REFUSED instruction `addu` has no C spelling in the table (P36 rung B tus9)
|
||||
tmp = (tmp & 0x1F) - 0x14;
|
||||
D_800A5E90 = tmp;
|
||||
s1 = (s32 *)a0;
|
||||
s0 = &D_800A5E88;
|
||||
|
||||
func_80028620(a0v, s0);
|
||||
tmp = rand();
|
||||
s0[0] = (tmp & 0x1F) - 0x10;
|
||||
|
||||
tmp = rand();
|
||||
D_800A5E90 = (tmp & 0x1F) - 0x14;
|
||||
|
||||
func_80028620(0, s0);
|
||||
|
||||
if (D_801270C8 == 0xC) {
|
||||
*(s16 *)((s8 *)s1 + 2) = 0x7;
|
||||
*(s16 *)((u8 *)s1 + 2) = 7;
|
||||
D_800A5EA0 = 0xE;
|
||||
func_80028620(1, (void *)((s32)s0 + 0x10));
|
||||
__asm__("" : "=r"(s0) : "0"(s0)); // !FAKE: launder — NEEDED DIFFERS (P36 rung B tus9)
|
||||
func_80028620(1, (void *)((u8 *)s0 + 0x10));
|
||||
D_800A5EB0 = -0xA;
|
||||
func_80028620(2, (void *)((s32)s0 + 0x20));
|
||||
func_80028620(2, (void *)((u8 *)s0 + 0x20));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user