mirror of
https://github.com/Druthulu/BFM-decomp
synced 2026-09-26 13:33:34 -04:00
phase-36: S105 s105_f5 — func_8018F72C banked at 0 through the whole-object gate + propagated — f5 plain C (two derived pointers)
This commit is contained in:
Drew T
+175
-175
@@ -1,7 +1,7 @@
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{
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"head": "ac4460cb3",
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"head": "e399db17e",
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"stamp": "15956e4a96c4",
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"generated": "2026-09-11 13:19",
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"generated": "2026-09-11 13:20",
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"aliases": [
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"main",
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@@ -21,206 +21,206 @@
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|
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|
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|
||||
@@ -29607,3 +29607,4 @@
|
||||
{"ts": "2026-09-11 13:19:24", "label": "s105_f5", "rung": "E", "calib": {"head": "7f33a7510", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC02_005/ov_SC02_005_jr_8018EA04.c", "fn": "func_8018FB8C", "addr": 2149120908, "aliases": null, "header": false, "includers": 0, "nhash_before": "83c2c8274c551d5d0f4cbd91aeef7bef92f21d1f", "nhash_after": "0a2d40f027a03ba0fd4f9016d6d90efb6b3a1f1b", "source": ".run/P36/agents/ov_SC02_005__func_8018FB8C/body.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.069, "objects": ["build/src/ov_SC02_005/ov_SC02_005_jr_8018EA04.o"], "before_text": "void func_8018FB8C(void *a0) {\n s32 *s0;\n register s32 a0v __asm__(\"a0\"); // !FAKE: pin a0 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n s32 *s1 = (s32 *)a0;\n s32 tmp;\n\n tmp = rand();\n s0 = (s32 *)&D_800A5E88;\n tmp = (tmp & 0x1F) - 0x10;\n s0[0] = tmp;\n tmp = rand();\n __asm__(\"addu %0,$zero,$zero\" : \"=r\"(a0v)); // !FAKE: instruction addu \u2014 REFUSED instruction `addu` has no C spelling in the table (P36 rung B tus9)\n tmp = (tmp & 0x1F) - 0x14;\n D_800A5E90 = tmp;\n\n func_80028620(a0v, s0);\n\n if (D_801270C8 == 0xC) {\n *(s16 *)((s8 *)s1 + 2) = 0x7;\n D_800A5EA0 = 0xE;\n func_80028620(1, (void *)((s32)s0 + 0x10));\n __asm__(\"\" : \"=r\"(s0) : \"0\"(s0)); // !FAKE: launder \u2014 NEEDED DIFFERS (P36 rung B tus9)\n D_800A5EB0 = -0xA;\n func_80028620(2, (void *)((s32)s0 + 0x20));\n }\n}\n", "after_text": "void func_8018FB8C(void *a0) {\n s32 *s0;\n s32 *s1;\n s32 tmp;\n\n s1 = (s32 *)a0;\n s0 = &D_800A5E88;\n\n tmp = rand();\n s0[0] = (tmp & 0x1F) - 0x10;\n\n tmp = rand();\n D_800A5E90 = (tmp & 0x1F) - 0x14;\n\n func_80028620(0, s0);\n\n if (D_801270C8 == 0xC) {\n *(s16 *)((u8 *)s1 + 2) = 7;\n D_800A5EA0 = 0xE;\n func_80028620(1, (void *)((u8 *)s0 + 0x10));\n D_800A5EB0 = -0xA;\n func_80028620(2, (void *)((u8 *)s0 + 0x20));\n }\n}\n"}
|
||||
{"ts": "2026-09-11 13:19:41", "label": "s105_f5", "rung": "E", "calib": {"head": "ba665f30d", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC02_005/ov_SC02_005_jr_8018EA04.c", "fn": "func_8018FCE4", "addr": 2149121252, "aliases": null, "header": false, "includers": 0, "nhash_before": "5639a46d6bf09412ed8885fd42cdc52bcf33cbd6", "nhash_after": "c4c7f46c63af82c82ba070d1e3f9913de26efa28", "source": ".run/P36/agents/ov_SC02_005__func_8018FCE4/body.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.071, "objects": ["build/src/ov_SC02_005/ov_SC02_005_jr_8018EA04.o"], "before_text": "void func_8018FCE4(void *a0)\n{\n void *s1;\n s32 *s0;\n s32 v0;\n s32 eac;\n register s32 a0v __asm__(\"$4\"); // !FAKE: pin $4 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n\n s1 = a0;\n v0 = rand();\n s0 = (s32 *)&D_800A5E88;\n v0 = (v0 & 0x1F) - 0x10;\n s0[0] = v0;\n\n v0 = rand();\n a0v = 0;\n __asm__ __volatile__(\"\" ::: \"memory\"); // !FAKE: barrier memory \u2014 NEEDED DIFFERS (P36 rung B tus9)\n v0 = (v0 & 0x1F) - 0x14;\n D_800A5E90 = v0;\n\n func_80028620(a0v, s0);\n\n if (D_801270C8 == 0xD) {\n *(s16 *)((u8 *)s1 + 2) = 9;\n s0[0] = 0;\n D_800A5E8C = 0xA;\n D_800A5E90 = -0xA;\n D_800A5E94 = 0xCC;\n D_800A5E95 = 0x99;\n D_800A5E96 = 0x99;\n func_80028620(0, s0);\n\n D_800A5EA0 = -8;\n D_800A5EA5 = 0x19;\n func_80028620(1, &s0[4]);\n\n a0v = 2;\n eac = 0x14;\n __asm__(\"\" : \"=r\"(s0) : \"0\"(s0)); // !FAKE: launder \u2014 NEEDED DIFFERS (P36 rung B tus9)\n s0[8] = 0;\n __asm__ __volatile__(\"\" ::: \"memory\"); // !FAKE: barrier memory \u2014 NEEDED DIFFERS (P36 rung B tus9)\n D_800A5EAC = eac;\n D_800A5EB0 = 0xF;\n D_800A5EB4 = 0x4C;\n D_800A5EB5 = 0x33;\n D_800A5EB6 = 0x7F;\n func_80028620(a0v, &s0[8]);\n }\n}\n", "after_text": "void func_8018FCE4(void *a0)\n{\n void *s1;\n s32 *s0;\n s32 *p;\n s32 v0;\n\n s1 = a0;\n s0 = &D_800A5E88;\n\n v0 = rand();\n s0[0] = (v0 & 0x1F) - 0x10;\n\n v0 = rand();\n D_800A5E90 = (v0 & 0x1F) - 0x14;\n\n func_80028620(0, s0);\n\n if (D_801270C8 == 0xD) {\n *(s16 *)((u8 *)s1 + 2) = 9;\n s0[0] = 0;\n D_800A5E8C = 0xA;\n D_800A5E90 = -0xA;\n D_800A5E94 = 0xCC;\n D_800A5E95 = 0x99;\n D_800A5E96 = 0x99;\n func_80028620(0, s0);\n\n D_800A5EA0 = -8;\n D_800A5EA5 = 0x19;\n func_80028620(1, &s0[4]);\n\n p = &s0[8];\n *p = 0;\n D_800A5EAC = 0x14;\n D_800A5EB0 = 0xF;\n D_800A5EB4 = 0x4C;\n D_800A5EB5 = 0x33;\n D_800A5EB6 = 0x7F;\n func_80028620(2, p);\n }\n}\n"}
|
||||
{"ts": "2026-09-11 13:19:59", "label": "s105_f5", "rung": "E", "calib": {"head": "ac4460cb3", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC02_005/ov_SC02_005_jr_8018EA04.c", "fn": "func_8018FEA0", "addr": 2149121696, "aliases": null, "header": false, "includers": 0, "nhash_before": "2b6ec6640119eef3eed502daece45745e93dc838", "nhash_after": "7260145b6e8ce6c64915f4dc3e088aa7132a5c6c", "source": ".run/P36/agents/ov_SC02_005__func_8018FEA0/body.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.071, "objects": ["build/src/ov_SC02_005/ov_SC02_005_jr_8018EA04.o"], "before_text": "void func_8018FEA0(void *a0)\n{\n s32 *s0;\n s32 s1v;\n s32 s2v;\n s32 s3v;\n register s32 a0v __asm__(\"$4\"); // !FAKE: pin $4 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n s32 eb0;\n\n if (D_801270C8 >= 0x14) {\n a0v = 0;\n __asm__(\"la %0, D_800A5E88\" : \"=r\"(s0)); // !FAKE: instruction la \u2014 NEEDED DIFFERS (P36 rung B tus9)\n\n *(s16 *)((u8 *)a0 + 0x2) = 0xB;\n\n s3v = 0x16;\n s0[0] = 0;\n D_800A5E8C = s3v;\n D_800A5E90 = 0;\n D_800A5E94 = 0xB2;\n D_800A5E95 = 0x66;\n s1v = 0x33;\n D_800A5E96 = s1v;\n func_80028620(a0v, s0);\n\n a0v = 1;\n s0[4] = 0;\n D_800A5E9C = -0xE;\n D_800A5EA0 = -0xE;\n D_800A5EA4 = s1v;\n D_800A5EA5 = 0;\n s2v = 0x4C;\n D_800A5EA6 = s2v;\n func_80028620(a0v, &s0[4]);\n\n a0v = 2;\n eb0 = 0xF;\n s0[8] = 0;\n __asm__ __volatile__(\"\" ::: \"memory\"); // !FAKE: barrier memory \u2014 NEEDED DIFFERS (P36 rung B tus9)\n D_800A5EB0 = eb0;\n D_800A5EAC = s3v;\n D_800A5EB4 = s2v;\n D_800A5EB5 = s1v;\n D_800A5EB6 = 0x7F;\n func_80028620(a0v, &s0[8]);\n }\n}\n", "after_text": "void func_8018FEA0(void *a0)\n{\n s32 *s0;\n s32 *p1;\n s32 *p2;\n s32 s1v;\n s32 s2v;\n s32 s3v;\n\n if (D_801270C8 >= 0x14) {\n s0 = &D_800A5E88;\n\n *(s16 *)((u8 *)a0 + 0x2) = 0xB;\n\n s3v = 0x16;\n s0[0] = 0;\n D_800A5E8C = s3v;\n D_800A5E90 = 0;\n D_800A5E94 = 0xB2;\n D_800A5E95 = 0x66;\n s1v = 0x33;\n D_800A5E96 = s1v;\n func_80028620(0, s0);\n\n p1 = &s0[4];\n *p1 = 0;\n D_800A5E9C = -0xE;\n D_800A5EA0 = -0xE;\n D_800A5EA4 = s1v;\n D_800A5EA5 = 0;\n s2v = 0x4C;\n D_800A5EA6 = s2v;\n func_80028620(1, p1);\n\n p2 = &s0[8];\n *p2 = 0;\n D_800A5EB0 = 0xF;\n D_800A5EAC = s3v;\n D_800A5EB4 = s2v;\n D_800A5EB5 = s1v;\n D_800A5EB6 = 0x7F;\n func_80028620(2, p2);\n }\n}\n"}
|
||||
{"ts": "2026-09-11 13:20:16", "label": "s105_f5", "rung": "E", "calib": {"head": "e399db17e", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC02_005/ov_SC02_005_jr_8018EA04.c", "fn": "func_8018F72C", "addr": 2149119788, "aliases": null, "header": false, "includers": 0, "nhash_before": "5cdeb45de342575cd2b91b0b73d98f05e32b27d5", "nhash_after": "4023a387eb43665b4629ebaec71a32f042e629c4", "source": ".run/P36/agents/ov_SC02_005__func_8018F72C/body.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.07, "objects": ["build/src/ov_SC02_005/ov_SC02_005_jr_8018EA04.o"], "before_text": "void func_8018F72C(void *a0)\n{\n s32 v0;\n s32 *s0;\n s32 s1v;\n s32 s2v;\n register s32 a0v __asm__(\"$4\"); // !FAKE: pin $4 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n s32 e9c, eac;\n\n v0 = ((s32 (*)(void))func_8012C1B8)();\n *(s32 *)((u8 *)a0 + 0x20) = v0;\n\n if (v0 == 0) {\n func_8012CAE4(a0);\n return;\n }\n\n *(s16 *)((u8 *)a0 + 0x2) = 1;\n *(u32 *)(*(s32 *)((u8 *)a0 + 0x20) + 0x4) |= 0x80000000;\n\n __asm__(\"la %0, D_800A5E88\" : \"=r\"(s0)); // !FAKE: instruction la \u2014 NEEDED DIFFERS (P36 rung B tus9)\n s0[0] = 0;\n D_800A5E8C = 0xA;\n D_800A5E90 = -0xA;\n D_800A5E94 = 0xCC;\n D_800A5E95 = 0x99;\n D_800A5E96 = 0x99;\n func_80028620(0, s0);\n\n a0v = 1;\n e9c = -0xE;\n s0[4] = 0;\n __asm__ __volatile__(\"\" ::: \"memory\"); // !FAKE: barrier memory \u2014 NEEDED DIFFERS (P36 rung B tus9)\n D_800A5E9C = e9c;\n D_800A5EA0 = -0x8;\n s2v = 0x33;\n D_800A5EA4 = s2v;\n D_800A5EA5 = 0x19;\n s1v = 0x4C;\n D_800A5EA6 = s1v;\n func_80028620(a0v, &s0[4]);\n\n a0v = 2;\n eac = 0x14;\n s0[8] = 0;\n __asm__ __volatile__(\"\" ::: \"memory\"); // !FAKE: barrier memory \u2014 NEEDED DIFFERS (P36 rung B tus9)\n D_800A5EAC = eac;\n D_800A5EB0 = 0xF;\n D_800A5EB4 = s1v;\n D_800A5EB5 = s2v;\n D_800A5EB6 = 0x7F;\n func_80028620(a0v, &s0[8]);\n\n if (func_800CF854()) {\n *(s16 *)((u8 *)a0 + 0x2) = 0xA;\n }\n}\n", "after_text": "void func_8018F72C(void *a0)\n{\n s32 v0;\n s32 *s0;\n s32 *p1;\n s32 *p2;\n s32 s1v;\n s32 s2v;\n\n v0 = ((s32 (*)(void))func_8012C1B8)();\n *(s32 *)((u8 *)a0 + 0x20) = v0;\n\n if (v0 == 0) {\n func_8012CAE4(a0);\n return;\n }\n\n *(s16 *)((u8 *)a0 + 0x2) = 1;\n *(u32 *)(*(s32 *)((u8 *)a0 + 0x20) + 0x4) |= 0x80000000;\n\n s0 = &D_800A5E88;\n s0[0] = 0;\n D_800A5E8C = 0xA;\n D_800A5E90 = -0xA;\n D_800A5E94 = 0xCC;\n D_800A5E95 = 0x99;\n D_800A5E96 = 0x99;\n func_80028620(0, s0);\n\n p1 = &s0[4];\n *p1 = 0;\n D_800A5E9C = -0xE;\n D_800A5EA0 = -0x8;\n s2v = 0x33;\n D_800A5EA4 = s2v;\n D_800A5EA5 = 0x19;\n s1v = 0x4C;\n D_800A5EA6 = s1v;\n func_80028620(1, p1);\n\n p2 = &s0[8];\n *p2 = 0;\n D_800A5EAC = 0x14;\n D_800A5EB0 = 0xF;\n D_800A5EB4 = s1v;\n D_800A5EB5 = s2v;\n D_800A5EB6 = 0x7F;\n func_80028620(2, p2);\n\n if (func_800CF854()) {\n *(s16 *)((u8 *)a0 + 0x2) = 0xA;\n }\n}\n"}
|
||||
|
||||
@@ -4144,10 +4144,10 @@ void func_8018F72C(void *a0)
|
||||
{
|
||||
s32 v0;
|
||||
s32 *s0;
|
||||
s32 *p1;
|
||||
s32 *p2;
|
||||
s32 s1v;
|
||||
s32 s2v;
|
||||
register s32 a0v __asm__("$4"); // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus9)
|
||||
s32 e9c, eac;
|
||||
|
||||
v0 = ((s32 (*)(void))func_8012C1B8)();
|
||||
*(s32 *)((u8 *)a0 + 0x20) = v0;
|
||||
@@ -4160,7 +4160,7 @@ void func_8018F72C(void *a0)
|
||||
*(s16 *)((u8 *)a0 + 0x2) = 1;
|
||||
*(u32 *)(*(s32 *)((u8 *)a0 + 0x20) + 0x4) |= 0x80000000;
|
||||
|
||||
__asm__("la %0, D_800A5E88" : "=r"(s0)); // !FAKE: instruction la — NEEDED DIFFERS (P36 rung B tus9)
|
||||
s0 = &D_800A5E88;
|
||||
s0[0] = 0;
|
||||
D_800A5E8C = 0xA;
|
||||
D_800A5E90 = -0xA;
|
||||
@@ -4169,29 +4169,25 @@ void func_8018F72C(void *a0)
|
||||
D_800A5E96 = 0x99;
|
||||
func_80028620(0, s0);
|
||||
|
||||
a0v = 1;
|
||||
e9c = -0xE;
|
||||
s0[4] = 0;
|
||||
__asm__ __volatile__("" ::: "memory"); // !FAKE: barrier memory — NEEDED DIFFERS (P36 rung B tus9)
|
||||
D_800A5E9C = e9c;
|
||||
p1 = &s0[4];
|
||||
*p1 = 0;
|
||||
D_800A5E9C = -0xE;
|
||||
D_800A5EA0 = -0x8;
|
||||
s2v = 0x33;
|
||||
D_800A5EA4 = s2v;
|
||||
D_800A5EA5 = 0x19;
|
||||
s1v = 0x4C;
|
||||
D_800A5EA6 = s1v;
|
||||
func_80028620(a0v, &s0[4]);
|
||||
func_80028620(1, p1);
|
||||
|
||||
a0v = 2;
|
||||
eac = 0x14;
|
||||
s0[8] = 0;
|
||||
__asm__ __volatile__("" ::: "memory"); // !FAKE: barrier memory — NEEDED DIFFERS (P36 rung B tus9)
|
||||
D_800A5EAC = eac;
|
||||
p2 = &s0[8];
|
||||
*p2 = 0;
|
||||
D_800A5EAC = 0x14;
|
||||
D_800A5EB0 = 0xF;
|
||||
D_800A5EB4 = s1v;
|
||||
D_800A5EB5 = s2v;
|
||||
D_800A5EB6 = 0x7F;
|
||||
func_80028620(a0v, &s0[8]);
|
||||
func_80028620(2, p2);
|
||||
|
||||
if (func_800CF854()) {
|
||||
*(s16 *)((u8 *)a0 + 0x2) = 0xA;
|
||||
|
||||
Reference in New Issue
Block a user