phase-36: S104 s104_e17 — func_8018CC24 banked at 0 through the whole-object gate + propagated — $2 pin → 0: every multi-death temp split at once (local-alloc.c:472; find_reg global.c:945-990)

2026-09-26 21:36:06 -04:00 · 2026-09-11 02:36:01 -06:00
parent 99355f6723
commit c51e7d1711
11 changed files with 558 additions and 214 deletions
@@ -0,0 +1,55 @@
+void func_8017E558(void *arg0) {
+    extern u8 D_801EEDC8[];
+    s32 cnt2;
+    s32 i;
+    s32 j;
+    s32 base;
+    s32 p;
+    s32 vel;
+    s32 pos;
+    u16 life;
+    s32 f18;
+
+    cnt2 = 0;
+    for (i = 0; i < 8; i++) {
+        base = (s32)&D_801EEDC8[i * 0x1D0];
+        if (*(s16 *)(base) == 0) {
+            *(s32 *)(base + 0xC) = *(s32 *)(base + 0xC) + 0x10000;
+        }
+        for (j = 0; j < 16; j++) {
+            p = base + 0x10 + j * 0x1C;
+            switch (*(s16 *)(p)) {
+            case 0:
+                vel = *(s32 *)(p + 0xC) + *(s32 *)(p + 0x10);
+                pos = *(s32 *)(p + 0x14);
+                life = *(u16 *)(p + 2) - 1;
+                pos = pos + vel;
+                *(s32 *)(p + 0x14) = pos;
+                *(s32 *)(p + 0xC) = vel;
+                *(u16 *)(p + 2) = life;
+                if ((s16)life == -1) {
+                    *(u16 *)(p) = *(u16 *)(p) + 1;
+                }
+                *(u16 *)(p + 4) = *(u16 *)(p + 4) + *(u16 *)(p + 6);
+                *(u16 *)(p + 0xA) = *(u16 *)(p + 0xA) + 0x10;
+                break;
+            case 1:
+                *(u16 *)(p + 4) = *(u16 *)(p + 4) + 0x80;
+                f18 = *(s32 *)(p + 0x18) - 8;
+                *(s32 *)(p + 0x18) = f18;
+                if (f18 < 0) {
+                    *(s32 *)(p + 0x18) = 0;
+                    *(u16 *)(p) = *(u16 *)(p) + 1;
+                }
+                break;
+            case 2:
+                cnt2 = cnt2 + 1;
+                break;
+            }
+        }
+        func_8017E6EC(arg0, base);
+    }
+    if (cnt2 == 0x80) {
+        ((void (*)(u8 *))func_80146C3C)(arg0);
+    }
+}
@@ -0,0 +1,83 @@
+# func_8017E558 (ov_SC04_011_jr_8017D494.c): mechanism (P36 T7 S104, agent e17)
+
+**Result: score 0 in plain C.** No pin, no asm, no added volatile. Levers go from 2 to 0 (the `$5` pin on `base` and the
+`$2` pin on `sym`). Signature unchanged. **The same two moves close five copies in other TUs (10 more levers), all at 0**:
+`scratch/copies/LIST.txt` lists them with their files (`func_8017D994` ov_SC03_105, `func_8017F278` ov_SC03_028,
+`func_8017E1D4` ov_SC05_010, `func_8017E7E8` ov_SC07_002, `func_8017DDE0` ov_SC06_029).
+
+## (a) The residual in one sentence
+Two defects stacked. First a COUNT one (99 vs 101): mine hoists `&D_801EEDC8` out of the outer loop and walks the group
+pointer (`lui/addiu s0` before the loop, `addiu s0,s0,464`), where the target walks an OFFSET (`s1 += 464`) and rebuilds
+the address every iteration (`lui v0; addiu v0; addu a1,s1,v0`). Under it, a REGISTER permutation of the four
+caller-saved loop values: target base→`a1`, p→`a2`, the inner offset→`a3`, j→`t0`; mine gives p `a1` and base `t0`.
+
+## (b) The passes and the decisions (proven on the `-dL`/`.greg` dumps and bytes)
+1. **loop.c keeps the symbol load in the loop only when its pseudo lives ONE insn.** `move_movables` hoists an invariant
+   only if `threshold * savings * lifetime >= insn_count` (`loop.c:1631`, threshold from `loop.c:532`). In the free body
+   the block-local `s32 sym = …;` is set, then the five-insn `i * 0x1D0` expansion runs, then the add: life 6, and the
+   `.loop` dump says `Insn 28: regno 83 (life 6), move-insn savings 1  moved to 296`. Once hoisted, `sym` is invariant and
+   `base = sym + i*464` is a giv (`Insn 40: giv … mult 464 add (reg/v:SI 83)`), reduced to a walked pointer (mine).
+   Written as ONE expression, `&D_801EEDC8[i * 0x1D0]`, the address is forced into a register right at the add: life 1,
+   `Insn 35: regno 89 (life 1), move-insn savings 1 not desirable`. It stays in the loop, is not invariant
+   (`n_times_set == 1`), so `simplify_giv_expr`'s REG case fails and `base` is NOT a giv. Only `i*464` is reduced
+   (`giv at 33 reduced to (reg:SI 135)` = `s1`). That is the target's count and shape (`scratch/v_a.c`, `v_c.c`: 101/101).
+2. **The call takes `base` as its second argument.** `func_8017E6EC` is defined later in the TU as `(s32 a0, s32 a1)` and
+   its first act is `move s7,a1` (it reads `14(a1)`, `2(a1)`: the group record). The body called it with one argument
+   (the TU's no-prototype `extern void func_8017E6EC();` let it). Passing `base` adds the copy `(set (reg:SI 5) base)`
+   before the call. jump2 deletes it as a no-op once `base` sits in `a1`. global.c records the preference: the `.greg`
+   of `scratch/dumps_v_c2/` shows `r76 … prefers a1`. `find_reg`'s first pass skips registers that a conflicting allocno
+   prefers (`regs_someone_prefers`, built from the LATER conflicting allocnos' preferences at `global.c:864-880`,
+   applied at `global.c:945-953`), so `p` (r77, priority 98571, allocated first) passes over `a1` and
+   takes `a2`. The inner offset giv (r131) takes `a3`, `j` (r75) `t0`, and `base` gets its preferred `a1`. Dispositions:
+   `75 in 8  76 in 5  77 in 6  131 in 7`, exactly the target.
+
+## (c) The moves that closed it (joint; each alone scores worse)
+```c
+        base = (s32)&D_801EEDC8[i * 0x1D0];     /* was: { s32 sym = (s32)D_801EEDC8; base = sym + i * 0x1D0; } */
+        ...
+        func_8017E6EC(arg0, base);               /* was: func_8017E6EC(arg0); the callee is (s32, s32) */
+```
+- Move 1 alone (`scratch/v_a.c`, `v_b.c`, `v_c.c`: the three one-expression spellings): 34, count right, registers wrong.
+- Move 2 alone (`scratch/v_free2.c`): 56, worse than the start (53).
+- Both: `v_a2.c` (`(s32)D_801EEDC8 + i * 0x1D0`), `v_b2.c` (`i * 0x1D0 + (s32)D_801EEDC8`), `v_c2.c` = `body.c`, and
+  `v_f2.c` (`(s32)((u8 *)D_801EEDC8 + i * 0x1D0)`): all 0.
+- The offset split into its own statement (`base = i * 0x1D0; base += (s32)D_801EEDC8;`, `v_d2.c`/`v_e2.c`): 8, 102 ins.
+  A self-updating `base` is two sets, so it is no longer the single-expression shape.
+
+## (d) Generator proposals
+- (count) When the target rebuilds a `lui/addiu` of a symbol INSIDE a loop and adds a walked offset (`addu rB,sOff,v0`)
+  but mine hoists the symbol and walks a pointer: fold every `T sym = &SYM; … x = sym + i*K;` into the one expression
+  `x = (s32)&SYM[i*K]` (and delete the temp). The symbol pseudo's lifetime must be 1 insn for `loop.c:1631` to refuse the
+  hoist.
+- (register) When a call's callee is defined in the same TU with MORE parameters than the call passes (`extern void f();`
+  with no prototype, the definition `f(s32, s32)`), and the target has a loop-carried value sitting in the next argument
+  register at the call: pass that value as the missing argument. This is METHOD step 3's first bullet ("a dropped call
+  argument") with a way to find it: compare the callee's DEFINITION arity with the call.
+
+## (e) What did NOT work
+The sweep's best was 27 (R6 inline sym + R7 do-while); R6 inline sym alone reached 34, the same as my move 1. No generator
+adds a call argument whose value is not already the next argument register's source. That is why move 2 was never
+reached.
+
+## (f) Where the method fell short
+- The tree's own header (`src/…_jr_8017D494.c:3153-3155`) says "the no-prototype forward decl is required so the
+  1-argument call site here does not become a 2-argument call". That is an old lever's reasoning, written as a law, and
+  it is wrong: the 2-argument call IS the original. The header is now stale (pins and the 1-arg claim), and so are the
+  matching comments in the five twins (e.g. ov_SC06_029's "is called here with one argument").
+- What found move 2 was the `.greg` table: base had priority 5322 against p's 98571, so no order move could put it
+  first. The only other way for `a1` to go to the lower allocno is a hard-register preference, and a preference for `a1`
+  is a call's second argument. The callee's objdump (`move s7,a1` as its first act) confirmed it.
+- Count first (METHOD step 2) worked. The count gap was a loop.c hoist, not a missing insn of mine, and the `-dL` dump's
+  "moved to" / "not desirable" lines named it in one compile.
+
+## (g) Structs question
+Partly. The TU already has the struct (`GroupRec_801EB5C8_8017E3B0`, 0x1D0 bytes, 16 `SubRec` of 0x1C at +0x10,
+block-scope in `func_8017E3B0`), and two twins declare their symbol with it. With the struct array, `base = (s32)&D[i];`
+closes too (proven on ov_SC03_028 and ov_SC06_029, `scratch/copies/`). So a struct gives the natural single-expression
+spelling for move 1 for free. It does not give move 2: the call argument is an allocation preference, not a memory-order
+channel. The inner loop's `p = base + 0x10 + j*0x1C` would be `&grp->subs[j]` in the structs phase. Not tested here, and
+it could change the inner loop's giv shape (today `16 + 28j` is the reduced giv and `base +` it is not, because
+`simplify_giv_expr` cannot add a REG invariant to a constant, `loop.c` PLUS/USE case). Test it on bytes before assuming.
+
+Files: `body.c` (score 0), `scratch/v_*.c` (the variants above with their scores), `scratch/dumps_{free,v_a,v_c2}/`,
+`scratch/copies/` (the five twins' ported bodies, their tree text, `LIST.txt`, `port.py`), `scratch/try.sh`.
@@ -0,0 +1,23 @@
+s32 func_80188A30(s32 a0) {
+    extern u16 D_80194814;
+    extern u16 D_80194816;
+    extern u16 D_801F161E;
+    extern s16 D_80126B98;
+    s16 in[3];
+    s16 out[3];
+
+    in[1] = 0;
+    in[0] = 0;
+    out[1] = 0;
+    out[0] = 0;
+    in[2] = D_80194814;
+    out[2] = D_80194816;
+    if (func_8012DEB8((s32)a0, (s32)in, (s32)out) != 0) {
+        D_80126B98 = 0x18;
+        if (*(s16 *)((s32)a0 + 0x106) == 0) {
+            u16 cnt = D_801F161E;
+            *(s16 *)((s32)a0 + 0x106) = 1;
+            D_801F161E = cnt + 1;
+        }
+    }
+}
@@ -0,0 +1,54 @@
+# func_80188A30 (ov_SC04_011_jr_8017D494.c): mechanism (P36 T7 S104, agent e17)
+
+**Result: score 0 in plain C with a SIGNATURE change — PARKED.** The return type is `s32` instead of `void`, the body is the
+lever-free `body_free.c` unchanged, and the function falls off the end (no `return` statement, like a K&R implicit-int
+function). No pin, no asm, no added volatile. Levers go from 1 to 0 (the `"memory"` barrier at tree line 11065).
+It needs the TU's later prototype changed too: line 13461 `extern void func_80188A30(s32 a0);` becomes
+`extern s32 func_80188A30(s32 a0);`. The whole-TU candidate is `scratch/tu_ret.c` (scored WITHOUT `--body`: 0). Its only
+caller, `func_8018C260` (line 13485, ignores the result), is also byte-identical under the new prototype (0).
+`body.c` alone does NOT compile with `--body` (the unchanged `extern void` conflicts); score it with the whole TU.
+
+## (a) The residual in one sentence
+One instruction missing (36 vs 37). The target leaves the delay slot of `beqz v0,<epilogue>` (the call-result test)
+EMPTY (`nop`). Mine fills it with `li v0,24`, the first insn of the fall-through arm (`D_80126B98 = 0x18`).
+
+## (b) The pass and the decision (source read; proven on bytes)
+reorg, `fill_eager_delay_slots` → `fill_slots_from_thread` (`reorg.c:3270-3380`). For a conditional branch it steals from
+the fall-through thread only an insn that does not set anything live on the OPPOSITE thread (`reorg.c:3375`,
+`! insn_sets_resource_p (trial, &opposite_needed, 1)`). The opposite thread is the jump target, the function end, so
+`opposite_needed` comes from `mark_target_live_regs` (`:3293`), which returns `end_of_function_needs` there (`:2458`).
+`init_resource_info` seeds that set with the return-value register when `current_function_return_rtx` is a REG
+(`reorg.c:4274-4277`). In a `void` function it is not, `$v0` is dead at the epilogue, and `li v0,24` is stolen. In an
+`s32` function `$v0` is live at the epilogue, `li v0,24` sets it, the steal is refused, and the slot stays `nop`.
+This is cookbook §162f1 ("a non-void return type is observable in delay slots") exactly: `li v1,1` in the second
+epilogue-bound `bnez` slot is still filled in both, because it does not set `$v0`.
+
+## (c) The move that closed it
+`void func_80188A30(s32 a0)` → `s32 func_80188A30(s32 a0)` (and the extern at 13461). Nothing else. The function emits no
+extra instruction: no path gains a `move v0,…`.
+
+## (d) Generator proposal
+When the only residual is an EMPTY delay slot (`nop`) on a branch to the epilogue where mine fills it with an insn that
+sets `$v0`, flip the function's return type from `void` to `s32` (and its prototypes in the TU); if a caller uses no result
+the callers' bytes do not change (§162f1). This is a signature change, so the generator should emit it as a parked
+candidate with the prototype edits listed.
+
+## (e) What did NOT work
+- The sweep (R7 blocks, R9 swaps, R10 param copy, R18 bystanders): 2 on every move; no generator touches the return type.
+- I know of no plain-C `void` spelling that reaches this (reasoned, not enumerated): in a void function `$v0` is not live at the end
+  (`current_function_return_rtx == 0`), and the fall-through's first insn is the constant load in every order the target
+  allows (the target's order is `li v0,24; lui at; sh`, the same as mine). The fallback, if the signature change is refused,
+  is the tree's body (1 marked barrier lever, the minimum).
+
+## (f) Where the method fell short
+Nothing blocked. Reading the whole objdump (METHOD step 1) showed the missing insn is a `nop` in a slot mine fills with a
+`$v0` write before an epilogue branch. That shape is already in the cookbook (§162f1, found by grepping
+`end_of_function_needs`), but neither PROMPT nor METHOD lists "empty slot before the epilogue → return type". Add it to
+METHOD step 3's list of what emits a missing instruction.
+
+## (g) Structs question
+No. The decision is reorg's liveness at the function end, set by the return type. No memory access is involved. (`a0` is an
+actor; `+0x106` is an s16 "already triggered" flag, and a struct would not change this.)
+
+Files: `body.c` (the `s32` definition), `scratch/tu_ret.c` (whole TU with the prototype changed: 0 for `func_80188A30` and
+for its caller `func_8018C260`), `scratch/free.o` (the free body's object, 36 ins).
@@ -0,0 +1,24 @@
+void func_8018CC24(s32 arg0) {
+    s32 a0;
+    s32 a1;
+    u16 val;
+
+    func_8012AD80(arg0);
+
+    a0 = *(s32 *)(arg0 + 0x20);
+    *(u16 *)(a0 + 0x10) = *(u16 *)(a0 + 0x10) + (*(u16 *)(arg0 + 0x106));
+
+    a1 = *(s32 *)(arg0 + 0x20);
+    val = *(u16 *)(arg0 + 0x108);
+    *(u16 *)(a1 + 0x14) = *(u16 *)(a1 + 0x14) + val;
+
+    if ((*(s32 *)(arg0 + 0x1C) & 0x3) == 0) {
+        func_8018A7E8(arg0);
+    }
+
+    *(s32 *)(arg0 + 0x1C) = *(s32 *)(arg0 + 0x1C) + 1;
+
+    if (*(s16 *)(arg0 + 0xA) >= -0x3FF) {
+        func_8012C218((void *)arg0);
+    }
+}
@@ -0,0 +1,56 @@
+# func_8018CC24 (ov_SC04_011_jr_8017D494.c): mechanism (P36 T7 S104, agent e17)
+
+**Result: score 0 in plain C, on the first `--try`.** No pin, no asm, no added volatile. Levers go from 1 to 0 (the `$2`
+pin on `v0`). Signature unchanged. The same edit closes `func_8018CCB8` (the next function, same shape plus a `Blk8`
+stack copy and a different callee); no copy of the class exists in another TU (grep of
+`v1_sign = *(s16 *)(s0 + 0xA);` finds only these two).
+
+## (a) The residual in one sentence
+Same count (37/37). A pure v0/v1 permutation: the decompiler variable `v0` (the field sums and the `+0x1C` counter) is in
+`v1` in mine and in `v0` in the target, and `v1`/`v1_sign` take the other register.
+
+## (b) The pass and the decision (read on the `.lreg`/`.greg` dumps; proven on bytes)
+- The free body REUSES `v0` for four values (two field sums, the `& 3` test's load, the counter) and `v1` for two. In the
+  `.lreg` of `scratch/dumps_free/`, `r75` (`v0`) "dies in 4 places" and `r74`/`r76` die in 2. local-alloc refuses a
+  pseudo that dies more than once (`local-alloc.c:472`), so all three become GLOBAL allocnos (`.greg` order `75 72 76 74`).
+- global.c then takes them in priority order (`allocno_compare`, `global.c:594-610`). `r75` is first (35000) but it
+  CONFLICTS with hard `v0`: the local compare temps (`r82`, `r85`, `r77`, allocated to `v0` by local-alloc before global
+  runs) are live while `r75` is live, e.g. the `slti` of the final test is born before the counter's `sw`. `find_reg`
+  (`global.c:945-990`) therefore skips `v0` and gives `r75` `v1`; the later allocnos take `v0`. The pin forced `r75` into
+  `v0`. (`scratch/dumps_free/`, `tools/alloc_table.py free func_8018CC24 scratch`.)
+- With one name per value every temp is born and dies in one block, local-alloc allocates it (`qty_compare`), and each
+  sum lands in `v0` next to the `v1` addend, exactly as the target and the lever-free sibling `func_8018CA04` have it.
+
+## (c) The move that closed it
+One variable per value (S103 c1/c8, generator R23), applied to BOTH `v0` and `v1` at once. The delivered `body.c` is the
+text of the lever-free same-TU sibling `func_8018CA04` (first entry of `related.txt`) with the `func_8012AD80` call moved
+first (that is the only structural difference in the bytes): the sums written in place,
+`*(u16 *)(a0 + 0x10) = *(u16 *)(a0 + 0x10) + *(u16 *)(arg0 + 0x106);`, the counter as
+`*(s32 *)(arg0 + 0x1C) = *(s32 *)(arg0 + 0x1C) + 1;`, the test on `*(s16 *)(arg0 + 0xA)` directly. Also proven:
+- `scratch/vA_split.c` (the free body with `x1,y1,x2,y2,c1,c2` as separate names, `s0 = a0` kept): 0.
+- `scratch/vE_sharedptr.c` (the same with ONE pointer local reused for both `+0x20` loads): 0 — the pointer's reuse is
+  harmless, only the value temps matter.
+
+## (d) Generator proposal
+When a register residual is a pure pair permutation and the `.lreg` shows two or more named temps that "die in N>1
+places", split EVERY such temp into one name per value in a single candidate (R23 splits one variable at a time and each
+single split scores worse here: 10 and 19).
+
+## (e) What did NOT work (byte evidence)
+- Splitting only `v0` (`scratch/vC_splitv0only.c`): 10 (a `v1`/`a0` swap remains).
+- Splitting only `v1` (`scratch/vD_splitv1only.c`): 19.
+- The sweep (R12 widths, R6/R8/R9/R10/R18, R4, R7): best 2, all COUNT-class. No generator produces the joint split.
+
+## (f) Where the method fell short
+Nothing blocked. `related.txt`'s first entry (`func_8018CA04`, 3 shared callees) is the same function with the call in a
+different place; reading it and matching the call position closed it on the first `--try`. The sweep should try
+"port the top related.txt body" before any generator.
+
+## (g) Structs question
+No. The lever was a local-alloc/global-alloc decision about register temps reused across statement groups; no memory
+access order is involved. `arg0` is clearly an actor struct (`+0x0A` s16 y?, `+0x1C` frame counter, `+0x20` child
+pointer with u16 fields at `+0x10`/`+0x14`, `+0x106`/`+0x108` u16 deltas), and a struct would make the text readable,
+but it would not change this allocation.
+
+Files: `body.c` (score 0), `scratch/vA_split.c`, `scratch/vE_sharedptr.c` (0), `scratch/vC_splitv0only.c` (10),
+`scratch/vD_splitv1only.c` (19), `scratch/dumps_free/`.
@@ -0,0 +1,27 @@
+void func_8018CCB8(s32 arg0) {
+    s32 a0;
+    s32 a1;
+    u16 val;
+    Blk8 sp10;
+
+    sp10 = D_801ED9AC[0];
+
+    func_8012AD80(arg0);
+
+    a0 = *(s32 *)(arg0 + 0x20);
+    *(u16 *)(a0 + 0x10) = *(u16 *)(a0 + 0x10) + (*(u16 *)(arg0 + 0x106));
+
+    a1 = *(s32 *)(arg0 + 0x20);
+    val = *(u16 *)(arg0 + 0x108);
+    *(u16 *)(a1 + 0x14) = *(u16 *)(a1 + 0x14) + val;
+
+    if ((*(s32 *)(arg0 + 0x1C) & 0x3) == 0) {
+        func_8018B0B0((void *)arg0, &sp10, (void *)0, 8);
+    }
+
+    *(s32 *)(arg0 + 0x1C) = *(s32 *)(arg0 + 0x1C) + 1;
+
+    if (*(s16 *)(arg0 + 0xA) >= -0x77F) {
+        func_8012C218((void *)arg0);
+    }
+}
@@ -0,0 +1,35 @@
+# func_8018CCB8 (ov_SC04_011_jr_8017D494.c): mechanism (P36 T7 S104, agent e17)
+
+**Result: score 0 in plain C, on the first `--try`.** No pin, no asm, no added volatile. Levers go from 1 to 0 (the `$2`
+pin on `v0`). Signature unchanged.
+
+This is the same class as `func_8018CC24` (the function just before it): identical body plus a `Blk8 sp10 = D_801ED9AC[0];`
+stack copy, `func_8018B0B0(arg0, &sp10, 0, 8)` in place of `func_8018A7E8`, and `-0x77F` in the last test. The full reading
+is in `../ov_SC04_011__func_8018CC24/mechanism.md`; in short:
+
+## (a) The residual
+Same count (53/53), a pure v0/v1 permutation (`v1->v0 x14, v0->v1 x8`).
+
+## (b) The pass
+The free body reuses `v0` for four values and `v1` for two; each dies in several places, so local-alloc refuses them
+(`local-alloc.c:472`) and they go global. The counter/sum pseudo conflicts with hard `v0` (the local compare temps sit in
+`v0` while it is live), so `find_reg` (`global.c:945-990`) gives it `v1`.
+
+## (c) The move
+One name per value, both variables at once. Delivered as the lever-free sibling text (`func_8018CA04`'s spelling, the call
+first, the sums and the counter written in place). `scratch/vA_split.c` (free body, `x1,y1,x2,y2,c1,c2` split, `s0`/`ptr`
+kept): 0 too.
+
+## (d) Generator proposal
+Split every multi-death temp named in `.lreg` in ONE candidate (R23 splits one at a time).
+
+## (e) What did not work
+The sweep: best 2 (R12 width `v0` s32->s16). Single splits were measured on the twin (10 and 19).
+
+## (f) Method
+`related.txt`'s top entry gave the text.
+
+## (g) Structs question
+No; a register-allocation decision about reused temps. `sp10` is an 8-byte struct copy (`Blk8`), already typed.
+
+Files: `body.c` (score 0), `scratch/vA_split.c` (0).
@@ -1,7 +1,7 @@
 {
- "head": "23f7c80df",
+ "head": "99355f672",
 "stamp": "15956e4a96c4",
- "generated": "2026-09-11 02:34",
+ "generated": "2026-09-11 02:35",
 "aliases": [
  "main",
  "ov_SC03_014",
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+   "seconds": 5.25,
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+   "seconds": 4.578000000000001,
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+  "build/src/ov_SC04_011/ov_SC04_011_o0c.o": 0.067
 },
 "ok": true,
- "seconds": 2.2
+ "seconds": 2.6
 }
@@ -13948,42 +13948,28 @@ extern void func_8012AD80(s32 a0);
 extern void func_8012C218(void *a0);
 extern void func_8018A7E8(s32);

-void func_8018CC24(s32 a0) {
-    s32 s0;
-    s32 a0_ptr;
-    register s32 v0 __asm__("$2");  // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B t3_tus1)
-    s32 v1;
-    s32 v1_sign;
+void func_8018CC24(s32 arg0) {
+    s32 a0;
+    s32 a1;
+    u16 val;

-    s0 = a0;
+    func_8012AD80(arg0);

-    func_8012AD80(a0);
+    a0 = *(s32 *)(arg0 + 0x20);
+    *(u16 *)(a0 + 0x10) = *(u16 *)(a0 + 0x10) + (*(u16 *)(arg0 + 0x106));

-    a0_ptr = *(s32 *)(s0 + 0x20);
-    v1 = *(u16 *)(s0 + 0x106);
-    v0 = *(u16 *)(a0_ptr + 0x10);
-    v0 = v0 + v1;
-    *(u16 *)(a0_ptr + 0x10) = (u16)v0;
+    a1 = *(s32 *)(arg0 + 0x20);
+    val = *(u16 *)(arg0 + 0x108);
+    *(u16 *)(a1 + 0x14) = *(u16 *)(a1 + 0x14) + val;

-    a0_ptr = *(s32 *)(s0 + 0x20);
-    v1 = *(u16 *)(s0 + 0x108);
-    v0 = *(u16 *)(a0_ptr + 0x14);
-    v0 = v0 + v1;
-    *(u16 *)(a0_ptr + 0x14) = (u16)v0;
-
-    v0 = *(s32 *)(s0 + 0x1C);
-    if ((v0 & 0x3) == 0) {
-        func_8018A7E8(a0);
+    if ((*(s32 *)(arg0 + 0x1C) & 0x3) == 0) {
+        func_8018A7E8(arg0);
    }

-    v0 = *(s32 *)(s0 + 0x1C);
-    v1_sign = *(s16 *)(s0 + 0xA);
-    v0++;
+    *(s32 *)(arg0 + 0x1C) = *(s32 *)(arg0 + 0x1C) + 1;

-    *(s32 *)(s0 + 0x1C) = v0;
-
-    if (v1_sign >= -0x3FF) {
-        func_8012C218((void *)a0);
+    if (*(s16 *)(arg0 + 0xA) >= -0x3FF) {
+        func_8012C218((void *)arg0);
    }
 }