mirror/BFM-decomp
1
0
Fork 0
mirror of https://github.com/Druthulu/BFM-decomp synced 2026-09-26 21:36:06 -04:00
Code Issues Packages Projects Releases Wiki Activity

phase-36: T7 burst — 503 more bodies banked, and the per-file scratch-object collision fixed at its cause

Browse Source 
The scorer named its scratch object after the FILE (compile_obj tag="score"), so the nine burst agents sharing one
translation unit wrote and read one object. Two reported it independently without seeing the code: spurious
COMPILE-ERRORs naming an unrelated header, and one agent scoring four candidates against another agent's function. The
tag is now per function. Every landed body was re-verified after the fix and all still score 0; the banks were never at
risk, the agents' intermediate readings were.

- banked: func_801627E8 (132), func_8017A3D8 (118), func_80141874 (119 of 125), func_801345F8 (134). 28,887 -> 27,984.
  lever_census --check: 27,984 pin/asm sites, 27,984 marked !FAKE, 0 UNMARKED — OK
- THE FINDING: the biggest lever class in this phase is a WRONG DECLARATION, not codegen. Four agents independently
  reached score 0 by restoring a call's real arity, each in a different spelling — a function-pointer cast, a widened
  block-scope prototype, a call given its argument, and a definition given its two parameters. The mechanisms differ
  (combine.c:1458's added_sets_2 gate; set_preference global.c:1589 ahead of first-fit at :1001-1015, the argument copy
  becoming a self-move deleted at toplev.c:3142 so it costs zero instructions; assign_parms' parameter home copies) but
  the class is one: a truncated (void) declaration removes an instruction the pin was then hired to fake. No generator
  can reach it — every generator rewrites statements that exist, and this changes a call's arity.
- func_80157D20 does not bank body-only (gcc rejects a block-scope redeclaration), so its Path A joins func_80136824 and
  func_80168828 as the third measured case for the types phase.
- two more new classes, byte-proven: a store sinking past a load because true_dependence's exception (sched.c:837-839)
  discards the edge, fixed by declaring the global an array and storing through [0] to set MEM_IN_STRUCT_P; and a
  post-decrement queued by expand_increment until the next sequence point, fixed by splitting the statement plus a u16
  destination cse refuses to join (cse.c:1017-1019).
- correction to record: an uninitialised register __asm__("$0") is an opaque operand, not a constant holder — R16 must
  refuse it.
- snapshot row 20.
This commit is contained in:
Drew T
2026-09-10 10:38:24 -06:00
parent fb6c857f7c
commit c6b380fcd0
511 changed files with 3932 additions and 3470 deletions
Download Patch File Download Diff File Expand all files Collapse all files
.run/P36/census/lever_census.json
+42 -42
View File
@@ -64,7 +64,7 @@
"instruction/direct": 1558,
"instruction/via-macro": 22,
"keepalive/direct": 1443,
"launder/direct": 4008,
"launder/direct": 3876,
"launder/via-macro": 444,
"verbatim-body/direct": 2682
}
@@ -72,23 +72,23 @@
"binaries": 218,
"classes": {
"A": {
"bodies": 7078,
"distinct_bodies": 969,
"bodies": 6575,
"distinct_bodies": 966,
"file_scope": 0,
"in_bodies": 16736,
"in_bodies": 15965,
"kinds": {
"pin": 16736
"pin": 15965
},
"marked": 16736,
"sites": 16736,
"tus": 2486,
"marked": 15965,
"sites": 15965,
"tus": 2363,
"unmarked": 0
},
"B": {
"bodies": 8757,
"distinct_bodies": 915,
"bodies": 8625,
"distinct_bodies": 914,
"file_scope": 13,
"in_bodies": 21681,
"in_bodies": 21549,
"kinds": {
"asm-body": 13,
"barrier": 4201,
@@ -97,12 +97,12 @@
"gte-unsigned": 3,
"instruction": 1580,
"keepalive": 1443,
"launder": 4452,
"launder": 4320,
"verbatim-body": 2682
},
"marked": 12417,
"sites": 21694,
"tus": 2128,
"marked": 12285,
"sites": 21562,
"tus": 2126,
"unmarked": 9277
},
"C": {
@@ -207,9 +207,9 @@
"coverage": {
"asm": {
"comment_dead": 6792,
"live": 38794,
"live": 37891,
"macro_block": 194,
"raw": 45780
"raw": 44877
},
"attribute": {
"comment_dead": 0,
@@ -225,9 +225,9 @@
},
"register": {
"comment_dead": 8587,
"live": 16786,
"live": 16015,
"macro_block": 18,
"raw": 25391
"raw": 24620
},
"volatile": {
"comment_dead": 2480,
@@ -237,7 +237,7 @@
}
},
"coverage_ok": true,
"elapsed_s": 24.6,
"elapsed_s": 26.6,
"generated": "2026-09-10",
"gte_levers": {
"direct": 362,
@@ -248,15 +248,15 @@
"via_macro": 100,
"what": "GTE ops whose clobbers exceed the canonical macro's (a scheduling steer): class-B levers INSIDE the headline number since T5 (2026-09-09), marked, 0 at the close"
},
"head": "9f5b22176",
"head": "fb6c857f7",
"headers": 3181,
"levers_AB": {
"asm": 12151,
"bodies": 8752,
"distinct_bodies": 1278,
"marked": 28887,
"pins": 16736,
"sites": 28887,
"asm": 12019,
"bodies": 8249,
"distinct_bodies": 1275,
"marked": 27984,
"pins": 15965,
"sites": 27984,
"unmarked": 0,
"what": "register pins + asm statements excluding GTE ops: the classes the phase drives to 0"
},
@@ -390,9 +390,9 @@
},
"pins": {
"bare_name": 15,
"init": 2157,
"init": 1757,
"registers": {
"$0": 773,
"$0": 639,
"$10": 144,
"$11": 5,
"$12": 406,
@@ -403,7 +403,7 @@
"$17": 497,
"$18": 311,
"$19": 572,
"$2": 3248,
"$2": 3129,
"$20": 284,
"$21": 407,
"$22": 7,
@@ -411,8 +411,8 @@
"$25": 1,
"$29": 13,
"$3": 1919,
"$4": 2556,
"$5": 2312,
"$4": 2172,
"$5": 2178,
"$6": 470,
"$7": 704,
"$8": 429,
@@ -423,30 +423,30 @@
"v0": 2,
"v1": 3
},
"sites": 16736,
"sites": 15965,
"sp": 13,
"spelling": {
"__asm__": 16658,
"__asm__": 15887,
"asm": 78
},
"volatile_qualified": 7,
"zero": 773
"zero": 639
},
"src_stamp": "5896e20c18fe8254",
"src_stamp": "6c5ac5576d493a26",
"tus": 4121,
"unclassified": 0,
"union_AD": {
"bodies": 12015,
"bodies": 11512,
"by_kind": {
"main": 165,
"md": 135,
"ov": 11458,
"ov": 10961,
"resident": 10,
"shared": 247
"shared": 241
},
"copies_in_multi": 10749,
"distinct_bodies": 1563,
"multi_copy_classes": 297
"copies_in_multi": 10246,
"distinct_bodies": 1560,
"multi_copy_classes": 294
},
"verbatim_excluded": {
"functions": 13,
.run/P36/census/lever_census.txt
+12 -12
View File
@@ -1,31 +1,31 @@
lever_census: 218 binaries · 4,121 TUs + 3,181 headers · coverage OK · unclassified 0 · verbatim excluded 13 fn / 14 sites (manifest 13)
coverage asm raw 45780 = live 38794 + macro-block 194 + comment/dead 6792
coverage register raw 25391 = live 16786 + macro-block 18 + comment/dead 8587
coverage asm raw 44877 = live 37891 + macro-block 194 + comment/dead 6792
coverage register raw 24620 = live 16015 + macro-block 18 + comment/dead 8587
coverage volatile raw 4456 = live 1894 + macro-block 82 + comment/dead 2480
coverage builtin raw 599 = live 445 + macro-block 0 + comment/dead 154
coverage attribute raw 76 = live 76 + macro-block 0 + comment/dead 0
class sites in-bodies file-scope bodies distinct TUs marked unmarked kinds
A pins 16736 16736 0 7078 969 2486 16736 0 {'pin': 16736}
B asm 21694 21681 13 8757 915 2128 12417 9277 {'gte': 6858, 'barrier': 4201, 'gte-lever': 462, 'gte-unsigned': 3, 'launder': 4452, 'instruction': 1580, 'asm-body': 13, 'keepalive': 1443, 'verbatim-body': 2682}
C volatile 1590 1438 152 496 96 610 14 1576 {'decl-body': 58, 'decl-file': 152, 'cast': 1378, 'param': 2}
A pins 15965 15965 0 6575 966 2363 15965 0 {'pin': 15965}
B asm 21562 21549 13 8625 914 2126 12285 9277 {'instruction': 1580, 'keepalive': 1443, 'gte': 6858, 'barrier': 4201, 'launder': 4320, 'gte-lever': 462, 'gte-unsigned': 3, 'asm-body': 13, 'verbatim-body': 2682}
C volatile 1590 1438 152 496 96 610 14 1576 {'cast': 1378, 'decl-file': 152, 'decl-body': 58, 'param': 2}
D register 50 50 0 47 47 6 0 50 {'register': 50}
E asm-label 7428 1005 6423 737 117 2080 0 7428 {'asm-label': 7428}
F builtin 445 445 0 428 27 302 0 445 {'builtin': 445}
G attribute 76 1 75 1 1 40 0 76 {'attribute': 76}
UNION A–D: 12,015 bodies · 1,563 distinct (addresses normalized) · 297 multi-copy classes holding 10,749 bodies · by kind {'ov': 11458, 'md': 135, 'shared': 247, 'main': 165, 'resident': 10}
THE PHASE'S NUMBER (pins + asm statements, GTE excluded): 28,887 sites in 8,752 bodies (1,278 distinct) · marked !FAKE 28,887 · UNMARKED 0
UNION A–D: 11,512 bodies · 1,560 distinct (addresses normalized) · 294 multi-copy classes holding 10,246 bodies · by kind {'ov': 10961, 'shared': 241, 'md': 135, 'main': 165, 'resident': 10}
THE PHASE'S NUMBER (pins + asm statements, GTE excluded): 27,984 sites in 8,249 bodies (1,275 distinct) · marked !FAKE 27,984 · UNMARKED 0
orphan !FAKE markers (no pin/asm site on the line nor below): 0
GTE levers (clobbers beyond the canonical macro's): 462 sites (100 via a variant macro, 362 direct) · marked 462 · UNMARKED 0 · unsigned GTE statements 3
per-TU asm macro definitions outside the GTE header: 314 {'gte': 150, 'launder': 154, 'instruction': 9, 'barrier': 1} (GTE variants 64)
pins: 16,736 · $0 773 · $sp 13 · with initializer 2,157 · volatile-qualified 7 · bare-name 15 · spellings {'__asm__': 16658, 'asm': 78}
per-TU asm macro definitions outside the GTE header: 314 {'launder': 154, 'gte': 150, 'instruction': 9, 'barrier': 1} (GTE variants 64)
pins: 15,965 · $0 639 · $sp 13 · with initializer 1,757 · volatile-qualified 7 · bare-name 15 · spellings {'__asm__': 15887, 'asm': 78}
whole-body asm routines in C shells, manifest PERMANENT (hand asm, NOT levers): 22 routines · 2,682 sites (2,660 private copies + 22 shared headers); asm-bodies NOT permanent (levers): 13 site(s) ['func_8001E378:DECOMPILE-NOW', 'func_80020F34:DECOMPILE-NOW', 'func_800249F0:DECOMPILE-NOW', 'func_80025CBC:DECOMPILE-NOW', 'func_80026514:UNCERTAIN', 'func_800268D0:UNCERTAIN', 'func_80027058:DECOMPILE-NOW', 'func_80027200:DECOMPILE-NOW', 'func_800CBA44:DECOMPILE-NOW', 'func_8017D810:DECOMPILE-NOW', 'func_8017E26C:UNCERTAIN', 'func_80184440:DECOMPILE-NOW', 'func_801A3BCC:DECOMPILE-NOW']
asm kinds: {'asm-body/direct': 13, 'barrier/direct': 4199, 'barrier/via-macro': 2, 'gte/direct': 200, 'gte/via-macro': 6658, 'gte-lever/direct': 362, 'gte-lever/via-macro': 100, 'gte-unsigned/direct': 3, 'instruction/direct': 1558, 'instruction/via-macro': 22, 'keepalive/direct': 1443, 'launder/direct': 4008, 'launder/via-macro': 444, 'verbatim-body/direct': 2682}
asm kinds: {'asm-body/direct': 13, 'barrier/direct': 4199, 'barrier/via-macro': 2, 'gte/direct': 200, 'gte/via-macro': 6658, 'gte-lever/direct': 362, 'gte-lever/via-macro': 100, 'gte-unsigned/direct': 3, 'instruction/direct': 1558, 'instruction/via-macro': 22, 'keepalive/direct': 1443, 'launder/direct': 3876, 'launder/via-macro': 444, 'verbatim-body/direct': 2682}
instruction mnemonics: {'addu': 834, 'move': 406, 'la': 142, 'lh': 134, 'addiu': 22, 'RTP_SND': 22, '.section': 7, 'lui': 4, 'and': 2, 'mult': 1, 'mfhi': 1, 'sll': 1, 'li': 1, 'lw': 1, 'nop': 1, 'srl': 1}
gte mnemonics: {'gte_ldv0': 757, 'gte_stlvnl': 593, 'gte_stsxy': 447, 'gte_rtps': 437, 'gte_stflg': 415, 'gte_rtpt': 352, 'gte_SetRotMatrix': 246, 'gte_stsxy3': 236, 'gte_rtv0tr': 228, 'gte_SetTransMatrix': 226, 'gte_ldv3c': 184, 'gte_ldv3': 177, 'gte_ldrgb': 164, 'gte_stsv': 161, 'lwc2': 159, 'gte_stsz4': 149, 'gte_stsz3': 147, 'gte_stszotz': 134, 'gte_ldIR0z': 134, 'gte_ldIRGB': 134, 'gte_dpcl': 134, 'gte_stORGB': 134, 'gte_stsxy3_f3': 111, 'gte_stclmv': 108, 'gte_nclip': 108, 'gte_stopz': 108, 'gte_stsxy3c': 108, 'gte_stsxy3_ft3': 79, 'gte_rtir': 75, 'gte_ldclmv': 72}
asm-bearing macro definitions: 314 (20 names, 3 with >1 text) kinds {'gte': 150, 'launder': 154, 'instruction': 9, 'barrier': 1}
asm-bearing macro definitions: 314 (20 names, 3 with >1 text) kinds {'launder': 154, 'gte': 150, 'instruction': 9, 'barrier': 1}
controls (R39):
src/800.c func_800226C0 pins got 14 expected 45 N-A
src/shared/ov/func_80178004.h pins got 8 expected 26 N-A
ov_SC03_006 func_80184034 bare-name pins got 0 expected 3 N-A
engine_prelude.h asm sites (a macro definition only) got 0 expected 0 OK
elapsed 24.6 s
elapsed 26.6 s
.run/P36/delever/calibration.json
+180 -180
View File
@@ -1,7 +1,7 @@
{
"head": "9f5b22176",
"head": "fb6c857f7",
"stamp": "b44c5a8a3423",
"generated": "2026-09-10 10:27",
"generated": "2026-09-10 10:35",
"aliases": [
"main",
"ov_SC03_014",
@@ -21,207 +21,207 @@
"main": {
"objects": 85,
"identical": 85,
"seconds": 7.466000000000002,
"mean_s": 0.088
"seconds": 7.376999999999999,
"mean_s": 0.087
},
"ov_SC03_014": {
"objects": 32,
"identical": 32,
"seconds": 4.936999999999999,
"mean_s": 0.154
"seconds": 4.6209999999999996,
"mean_s": 0.144
},
"ov_SC03_015": {
"objects": 32,
"identical": 32,
"seconds": 4.856000000000001,
"mean_s": 0.152
"seconds": 4.533,
"mean_s": 0.142
},
"ov_SC04_011": {
"objects": 28,
"identical": 28,
"seconds": 4.155,
"mean_s": 0.148
"seconds": 3.927,
"mean_s": 0.14
}
},
"per_object_seconds": {
"build/src/800.o": 0.774,
"build/src/800_b.o": 0.081,
"build/src/800.o": 0.793,
"build/src/800_b.o": 0.093,
"build/src/800_b_2.o": 0.328,
"build/src/800_b_o0a.o": 0.105,
"build/src/800_c.o": 0.2,
"build/src/800b2.o": 0.077,
"build/src/apicard1.o": 0.073,
"build/src/800_b_o0a.o": 0.078,
"build/src/800_c.o": 0.213,
"build/src/800b2.o": 0.086,
"build/src/apicard1.o": 0.087,
"build/src/apicard2.o": 0.087,
"build/src/apicard3.o": 0.069,
"build/src/apicard4.o": 0.091,
"build/src/apicard5.o": 0.077,
"build/src/apicard6.o": 0.071,
"build/src/apicard7.o": 0.073,
"build/src/boot.o": 0.099,
"build/src/gap.o": 0.145,
"build/src/libapi1.o": 0.088,
"build/src/libapi2.o": 0.059,
"build/src/libc2_1.o": 0.068,
"build/src/libc2_2.o": 0.066,
"build/src/libcd1.o": 0.087,
"build/src/libcd2.o": 0.065,
"build/src/libetc.o": 0.071,
"build/src/libgpu.o": 0.092,
"build/src/libgpu2.o": 0.086,
"build/src/libgs1.o": 0.096,
"build/src/libgs2.o": 0.073,
"build/src/libgs3.o": 0.067,
"build/src/libgs4.o": 0.076,
"build/src/libgs5.o": 0.068,
"build/src/libgs6.o": 0.087,
"build/src/libgs7.o": 0.07,
"build/src/libgs8.o": 0.068,
"build/src/apicard3.o": 0.075,
"build/src/apicard4.o": 0.069,
"build/src/apicard5.o": 0.088,
"build/src/apicard6.o": 0.099,
"build/src/apicard7.o": 0.082,
"build/src/boot.o": 0.1,
"build/src/gap.o": 0.098,
"build/src/libapi1.o": 0.087,
"build/src/libapi2.o": 0.07,
"build/src/libc2_1.o": 0.074,
"build/src/libc2_2.o": 0.067,
"build/src/libcd1.o": 0.082,
"build/src/libcd2.o": 0.073,
"build/src/libetc.o": 0.075,
"build/src/libgpu.o": 0.076,
"build/src/libgpu2.o": 0.081,
"build/src/libgs1.o": 0.078,
"build/src/libgs2.o": 0.071,
"build/src/libgs3.o": 0.073,
"build/src/libgs4.o": 0.073,
"build/src/libgs5.o": 0.069,
"build/src/libgs6.o": 0.081,
"build/src/libgs7.o": 0.067,
"build/src/libgs8.o": 0.069,
"build/src/libgte1.o": 0.067,
"build/src/libgte10.o": 0.062,
"build/src/libgte11.o": 0.063,
"build/src/libgte12.o": 0.066,
"build/src/libgte10.o": 0.064,
"build/src/libgte11.o": 0.07,
"build/src/libgte12.o": 0.071,
"build/src/libgte13.o": 0.072,
"build/src/libgte14.o": 0.069,
"build/src/libgte15.o": 0.066,
"build/src/libgte16.o": 0.074,
"build/src/libgte17.o": 0.073,
"build/src/libgte18.o": 0.065,
"build/src/libgte19.o": 0.076,
"build/src/libgte2.o": 0.072,
"build/src/libgte20.o": 0.074,
"build/src/libgte21.o": 0.069,
"build/src/libgte22.o": 0.074,
"build/src/libgte23.o": 0.069,
"build/src/libgte24.o": 0.069,
"build/src/libgte25.o": 0.072,
"build/src/libgte26.o": 0.068,
"build/src/libgte27.o": 0.074,
"build/src/libgte28.o": 0.082,
"build/src/libgte29.o": 0.072,
"build/src/libgte3.o": 0.07,
"build/src/libgte30.o": 0.067,
"build/src/libgte4.o": 0.07,
"build/src/libgte5.o": 0.073,
"build/src/libgte6.o": 0.07,
"build/src/libgte7.o": 0.068,
"build/src/libgte8.o": 0.078,
"build/src/libgte9.o": 0.068,
"build/src/libmcrd1.o": 0.079,
"build/src/libmcrd2.o": 0.079,
"build/src/libpad1.o": 0.074,
"build/src/libpad2.o": 0.077,
"build/src/sgap.o": 0.078,
"build/src/sgap_2.o": 0.071,
"build/src/libgte14.o": 0.081,
"build/src/libgte15.o": 0.076,
"build/src/libgte16.o": 0.072,
"build/src/libgte17.o": 0.074,
"build/src/libgte18.o": 0.076,
"build/src/libgte19.o": 0.065,
"build/src/libgte2.o": 0.064,
"build/src/libgte20.o": 0.071,
"build/src/libgte21.o": 0.072,
"build/src/libgte22.o": 0.077,
"build/src/libgte23.o": 0.071,
"build/src/libgte24.o": 0.065,
"build/src/libgte25.o": 0.067,
"build/src/libgte26.o": 0.069,
"build/src/libgte27.o": 0.069,
"build/src/libgte28.o": 0.068,
"build/src/libgte29.o": 0.06,
"build/src/libgte3.o": 0.068,
"build/src/libgte30.o": 0.069,
"build/src/libgte4.o": 0.064,
"build/src/libgte5.o": 0.068,
"build/src/libgte6.o": 0.067,
"build/src/libgte7.o": 0.07,
"build/src/libgte8.o": 0.069,
"build/src/libgte9.o": 0.071,
"build/src/libmcrd1.o": 0.076,
"build/src/libmcrd2.o": 0.067,
"build/src/libpad1.o": 0.078,
"build/src/libpad2.o": 0.07,
"build/src/sgap.o": 0.071,
"build/src/sgap_2.o": 0.067,
"build/src/sgap_3.o": 0.069,
"build/src/sgap_4.o": 0.085,
"build/src/sgap_5.o": 0.076,
"build/src/sgap_6.o": 0.072,
"build/src/sgap_8.o": 0.077,
"build/src/snd1.o": 0.078,
"build/src/snd10.o": 0.07,
"build/src/snd11.o": 0.072,
"build/src/snd12.o": 0.069,
"build/src/sgap_4.o": 0.065,
"build/src/sgap_5.o": 0.065,
"build/src/sgap_6.o": 0.068,
"build/src/sgap_8.o": 0.072,
"build/src/snd1.o": 0.071,
"build/src/snd10.o": 0.064,
"build/src/snd11.o": 0.06,
"build/src/snd12.o": 0.066,
"build/src/snd2.o": 0.075,
"build/src/snd3.o": 0.07,
"build/src/snd4.o": 0.072,
"build/src/snd5.o": 0.081,
"build/src/snd6.o": 0.077,
"build/src/snd7.o": 0.07,
"build/src/snd8.o": 0.075,
"build/src/snd9.o": 0.071,
"build/src/ov_SC03_014/ov_SC03_014.o": 0.134,
"build/src/ov_SC03_014/ov_SC03_014_after.o": 0.541,
"build/src/ov_SC03_014/ov_SC03_014_jr_8012ACE0.o": 0.416,
"build/src/ov_SC03_014/ov_SC03_014_jr_80135888.o": 0.067,
"build/src/ov_SC03_014/ov_SC03_014_jr_80135A4C.o": 0.06,
"build/src/ov_SC03_014/ov_SC03_014_jr_80135D20.o": 0.143,
"build/src/ov_SC03_014/ov_SC03_014_jr_801380E0.o": 0.163,
"build/src/ov_SC03_014/ov_SC03_014_jr_8013C98C.o": 0.115,
"build/src/ov_SC03_014/ov_SC03_014_jr_8013F350.o": 0.084,
"build/src/ov_SC03_014/ov_SC03_014_jr_8013FFD8.o": 0.071,
"build/src/ov_SC03_014/ov_SC03_014_jr_80140608.o": 0.19,
"build/src/snd3.o": 0.08,
"build/src/snd4.o": 0.071,
"build/src/snd5.o": 0.068,
"build/src/snd6.o": 0.121,
"build/src/snd7.o": 0.067,
"build/src/snd8.o": 0.067,
"build/src/snd9.o": 0.07,
"build/src/ov_SC03_014/ov_SC03_014.o": 0.131,
"build/src/ov_SC03_014/ov_SC03_014_after.o": 0.513,
"build/src/ov_SC03_014/ov_SC03_014_jr_8012ACE0.o": 0.378,
"build/src/ov_SC03_014/ov_SC03_014_jr_80135888.o": 0.059,
"build/src/ov_SC03_014/ov_SC03_014_jr_80135A4C.o": 0.065,
"build/src/ov_SC03_014/ov_SC03_014_jr_80135D20.o": 0.126,
"build/src/ov_SC03_014/ov_SC03_014_jr_801380E0.o": 0.158,
"build/src/ov_SC03_014/ov_SC03_014_jr_8013C98C.o": 0.11,
"build/src/ov_SC03_014/ov_SC03_014_jr_8013F350.o": 0.081,
"build/src/ov_SC03_014/ov_SC03_014_jr_8013FFD8.o": 0.065,
"build/src/ov_SC03_014/ov_SC03_014_jr_80140608.o": 0.174,
"build/src/ov_SC03_014/ov_SC03_014_jr_8015444C.o": 0.074,
"build/src/ov_SC03_014/ov_SC03_014_jr_80154C24.o": 0.18,
"build/src/ov_SC03_014/ov_SC03_014_jr_801588CC.o": 0.105,
"build/src/ov_SC03_014/ov_SC03_014_jr_80159C84.o": 0.081,
"build/src/ov_SC03_014/ov_SC03_014_jr_8015A3C8.o": 0.071,
"build/src/ov_SC03_014/ov_SC03_014_jr_8015AE2C.o": 0.093,
"build/src/ov_SC03_014/ov_SC03_014_jr_8015C32C.o": 0.511,
"build/src/ov_SC03_014/ov_SC03_014_jr_8016AB6C.o": 0.278,
"build/src/ov_SC03_014/ov_SC03_014_jr_80171B4C.o": 0.101,
"build/src/ov_SC03_014/ov_SC03_014_jr_801734BC.o": 0.214,
"build/src/ov_SC03_014/ov_SC03_014_jr_801789AC.o": 0.065,
"build/src/ov_SC03_014/ov_SC03_014_jr_80178D40.o": 0.108,
"build/src/ov_SC03_014/ov_SC03_014_jr_8017A4AC.o": 0.074,
"build/src/ov_SC03_014/ov_SC03_014_jr_8017AE2C.o": 0.178,
"build/src/ov_SC03_014/ov_SC03_014_jr_8017EB7C.o": 0.22,
"build/src/ov_SC03_014/ov_SC03_014_jr_80184440.o": 0.055,
"build/src/ov_SC03_014/ov_SC03_014_jr_801848E4.o": 0.292,
"build/src/ov_SC03_014/ov_SC03_014_o0b.o": 0.064,
"build/src/ov_SC03_014/ov_SC03_014_o0c.o": 0.061,
"build/src/ov_SC03_014/ov_SC03_014_o0d.o": 0.057,
"build/src/ov_SC03_014/ov_SC03_014_o0e.o": 0.071,
"build/src/ov_SC03_015/ov_SC03_015.o": 0.129,
"build/src/ov_SC03_015/ov_SC03_015_after.o": 0.522,
"build/src/ov_SC03_015/ov_SC03_015_jr_8012ACE0.o": 0.407,
"build/src/ov_SC03_015/ov_SC03_015_jr_80135888.o": 0.056,
"build/src/ov_SC03_015/ov_SC03_015_jr_80135A4C.o": 0.049,
"build/src/ov_SC03_015/ov_SC03_015_jr_80135D20.o": 0.12,
"build/src/ov_SC03_015/ov_SC03_015_jr_801380E0.o": 0.165,
"build/src/ov_SC03_015/ov_SC03_015_jr_8013C98C.o": 0.125,
"build/src/ov_SC03_014/ov_SC03_014_jr_80154C24.o": 0.171,
"build/src/ov_SC03_014/ov_SC03_014_jr_801588CC.o": 0.087,
"build/src/ov_SC03_014/ov_SC03_014_jr_80159C84.o": 0.07,
"build/src/ov_SC03_014/ov_SC03_014_jr_8015A3C8.o": 0.073,
"build/src/ov_SC03_014/ov_SC03_014_jr_8015AE2C.o": 0.09,
"build/src/ov_SC03_014/ov_SC03_014_jr_8015C32C.o": 0.495,
"build/src/ov_SC03_014/ov_SC03_014_jr_8016AB6C.o": 0.246,
"build/src/ov_SC03_014/ov_SC03_014_jr_80171B4C.o": 0.086,
"build/src/ov_SC03_014/ov_SC03_014_jr_801734BC.o": 0.2,
"build/src/ov_SC03_014/ov_SC03_014_jr_801789AC.o": 0.062,
"build/src/ov_SC03_014/ov_SC03_014_jr_80178D40.o": 0.101,
"build/src/ov_SC03_014/ov_SC03_014_jr_8017A4AC.o": 0.069,
"build/src/ov_SC03_014/ov_SC03_014_jr_8017AE2C.o": 0.175,
"build/src/ov_SC03_014/ov_SC03_014_jr_8017EB7C.o": 0.192,
"build/src/ov_SC03_014/ov_SC03_014_jr_80184440.o": 0.053,
"build/src/ov_SC03_014/ov_SC03_014_jr_801848E4.o": 0.272,
"build/src/ov_SC03_014/ov_SC03_014_o0b.o": 0.061,
"build/src/ov_SC03_014/ov_SC03_014_o0c.o": 0.054,
"build/src/ov_SC03_014/ov_SC03_014_o0d.o": 0.061,
"build/src/ov_SC03_014/ov_SC03_014_o0e.o": 0.069,
"build/src/ov_SC03_015/ov_SC03_015.o": 0.105,
"build/src/ov_SC03_015/ov_SC03_015_after.o": 0.505,
"build/src/ov_SC03_015/ov_SC03_015_jr_8012ACE0.o": 0.382,
"build/src/ov_SC03_015/ov_SC03_015_jr_80135888.o": 0.047,
"build/src/ov_SC03_015/ov_SC03_015_jr_80135A4C.o": 0.057,
"build/src/ov_SC03_015/ov_SC03_015_jr_80135D20.o": 0.117,
"build/src/ov_SC03_015/ov_SC03_015_jr_801380E0.o": 0.156,
"build/src/ov_SC03_015/ov_SC03_015_jr_8013C98C.o": 0.114,
"build/src/ov_SC03_015/ov_SC03_015_jr_8013F350.o": 0.081,
"build/src/ov_SC03_015/ov_SC03_015_jr_8013FFD8.o": 0.068,
"build/src/ov_SC03_015/ov_SC03_015_jr_80140608.o": 0.188,
"build/src/ov_SC03_015/ov_SC03_015_jr_8015444C.o": 0.076,
"build/src/ov_SC03_015/ov_SC03_015_jr_80154C24.o": 0.184,
"build/src/ov_SC03_015/ov_SC03_015_jr_801588CC.o": 0.1,
"build/src/ov_SC03_015/ov_SC03_015_jr_80159C84.o": 0.071,
"build/src/ov_SC03_015/ov_SC03_015_jr_8015A3C8.o": 0.071,
"build/src/ov_SC03_015/ov_SC03_015_jr_8015AE2C.o": 0.105,
"build/src/ov_SC03_015/ov_SC03_015_jr_8015C32C.o": 0.488,
"build/src/ov_SC03_015/ov_SC03_015_jr_8016AB6C.o": 0.288,
"build/src/ov_SC03_015/ov_SC03_015_jr_80171B4C.o": 0.101,
"build/src/ov_SC03_015/ov_SC03_015_jr_801734BC.o": 0.216,
"build/src/ov_SC03_015/ov_SC03_015_jr_801789AC.o": 0.068,
"build/src/ov_SC03_015/ov_SC03_015_jr_80178D40.o": 0.107,
"build/src/ov_SC03_015/ov_SC03_015_jr_8017A4AC.o": 0.069,
"build/src/ov_SC03_015/ov_SC03_015_jr_8017AE2C.o": 0.186,
"build/src/ov_SC03_015/ov_SC03_015_jr_8017EB7C.o": 0.204,
"build/src/ov_SC03_015/ov_SC03_015_jr_80184440.o": 0.055,
"build/src/ov_SC03_015/ov_SC03_015_jr_801848E4.o": 0.288,
"build/src/ov_SC03_015/ov_SC03_015_o0b.o": 0.066,
"build/src/ov_SC03_015/ov_SC03_015_o0c.o": 0.063,
"build/src/ov_SC03_015/ov_SC03_015_o0d.o": 0.062,
"build/src/ov_SC03_015/ov_SC03_015_o0e.o": 0.078,
"build/src/ov_SC04_011/ov_SC04_011.o": 0.135,
"build/src/ov_SC04_011/ov_SC04_011_after.o": 0.448,
"build/src/ov_SC04_011/ov_SC04_011_jr_8012ACE0.o": 0.359,
"build/src/ov_SC04_011/ov_SC04_011_jr_80135888.o": 0.057,
"build/src/ov_SC04_011/ov_SC04_011_jr_80135A4C.o": 0.056,
"build/src/ov_SC04_011/ov_SC04_011_jr_80135D20.o": 0.13,
"build/src/ov_SC04_011/ov_SC04_011_jr_801380E0.o": 0.156,
"build/src/ov_SC04_011/ov_SC04_011_jr_8013C98C.o": 0.117,
"build/src/ov_SC04_011/ov_SC04_011_jr_8013F350.o": 0.084,
"build/src/ov_SC04_011/ov_SC04_011_jr_8013FFD8.o": 0.069,
"build/src/ov_SC04_011/ov_SC04_011_jr_80140608.o": 0.181,
"build/src/ov_SC04_011/ov_SC04_011_jr_8015444C.o": 0.077,
"build/src/ov_SC04_011/ov_SC04_011_jr_80154C24.o": 0.175,
"build/src/ov_SC04_011/ov_SC04_011_jr_801588CC.o": 0.104,
"build/src/ov_SC04_011/ov_SC04_011_jr_80159C84.o": 0.078,
"build/src/ov_SC04_011/ov_SC04_011_jr_8015A3C8.o": 0.073,
"build/src/ov_SC04_011/ov_SC04_011_jr_8015AE2C.o": 0.098,
"build/src/ov_SC04_011/ov_SC04_011_jr_8015C32C.o": 0.364,
"build/src/ov_SC04_011/ov_SC04_011_jr_8016AB6C.o": 0.218,
"build/src/ov_SC04_011/ov_SC04_011_jr_80171B4C.o": 0.111,
"build/src/ov_SC04_011/ov_SC04_011_jr_801734BC.o": 0.179,
"build/src/ov_SC04_011/ov_SC04_011_jr_801789AC.o": 0.057,
"build/src/ov_SC04_011/ov_SC04_011_jr_80178D40.o": 0.1,
"build/src/ov_SC04_011/ov_SC04_011_jr_8017A4AC.o": 0.072,
"build/src/ov_SC04_011/ov_SC04_011_jr_8017AE2C.o": 0.101,
"build/src/ov_SC04_011/ov_SC04_011_jr_8017D494.o": 0.445,
"build/src/ov_SC04_011/ov_SC04_011_o0b.o": 0.054,
"build/src/ov_SC04_011/ov_SC04_011_o0c.o": 0.057
"build/src/ov_SC03_015/ov_SC03_015_jr_8013FFD8.o": 0.063,
"build/src/ov_SC03_015/ov_SC03_015_jr_80140608.o": 0.175,
"build/src/ov_SC03_015/ov_SC03_015_jr_8015444C.o": 0.075,
"build/src/ov_SC03_015/ov_SC03_015_jr_80154C24.o": 0.159,
"build/src/ov_SC03_015/ov_SC03_015_jr_801588CC.o": 0.093,
"build/src/ov_SC03_015/ov_SC03_015_jr_80159C84.o": 0.063,
"build/src/ov_SC03_015/ov_SC03_015_jr_8015A3C8.o": 0.07,
"build/src/ov_SC03_015/ov_SC03_015_jr_8015AE2C.o": 0.091,
"build/src/ov_SC03_015/ov_SC03_015_jr_8015C32C.o": 0.451,
"build/src/ov_SC03_015/ov_SC03_015_jr_8016AB6C.o": 0.278,
"build/src/ov_SC03_015/ov_SC03_015_jr_80171B4C.o": 0.098,
"build/src/ov_SC03_015/ov_SC03_015_jr_801734BC.o": 0.204,
"build/src/ov_SC03_015/ov_SC03_015_jr_801789AC.o": 0.062,
"build/src/ov_SC03_015/ov_SC03_015_jr_80178D40.o": 0.099,
"build/src/ov_SC03_015/ov_SC03_015_jr_8017A4AC.o": 0.067,
"build/src/ov_SC03_015/ov_SC03_015_jr_8017AE2C.o": 0.161,
"build/src/ov_SC03_015/ov_SC03_015_jr_8017EB7C.o": 0.189,
"build/src/ov_SC03_015/ov_SC03_015_jr_80184440.o": 0.058,
"build/src/ov_SC03_015/ov_SC03_015_jr_801848E4.o": 0.268,
"build/src/ov_SC03_015/ov_SC03_015_o0b.o": 0.062,
"build/src/ov_SC03_015/ov_SC03_015_o0c.o": 0.058,
"build/src/ov_SC03_015/ov_SC03_015_o0d.o": 0.053,
"build/src/ov_SC03_015/ov_SC03_015_o0e.o": 0.072,
"build/src/ov_SC04_011/ov_SC04_011.o": 0.126,
"build/src/ov_SC04_011/ov_SC04_011_after.o": 0.421,
"build/src/ov_SC04_011/ov_SC04_011_jr_8012ACE0.o": 0.339,
"build/src/ov_SC04_011/ov_SC04_011_jr_80135888.o": 0.056,
"build/src/ov_SC04_011/ov_SC04_011_jr_80135A4C.o": 0.052,
"build/src/ov_SC04_011/ov_SC04_011_jr_80135D20.o": 0.124,
"build/src/ov_SC04_011/ov_SC04_011_jr_801380E0.o": 0.15,
"build/src/ov_SC04_011/ov_SC04_011_jr_8013C98C.o": 0.114,
"build/src/ov_SC04_011/ov_SC04_011_jr_8013F350.o": 0.073,
"build/src/ov_SC04_011/ov_SC04_011_jr_8013FFD8.o": 0.066,
"build/src/ov_SC04_011/ov_SC04_011_jr_80140608.o": 0.169,
"build/src/ov_SC04_011/ov_SC04_011_jr_8015444C.o": 0.067,
"build/src/ov_SC04_011/ov_SC04_011_jr_80154C24.o": 0.169,
"build/src/ov_SC04_011/ov_SC04_011_jr_801588CC.o": 0.087,
"build/src/ov_SC04_011/ov_SC04_011_jr_80159C84.o": 0.062,
"build/src/ov_SC04_011/ov_SC04_011_jr_8015A3C8.o": 0.067,
"build/src/ov_SC04_011/ov_SC04_011_jr_8015AE2C.o": 0.096,
"build/src/ov_SC04_011/ov_SC04_011_jr_8015C32C.o": 0.348,
"build/src/ov_SC04_011/ov_SC04_011_jr_8016AB6C.o": 0.21,
"build/src/ov_SC04_011/ov_SC04_011_jr_80171B4C.o": 0.1,
"build/src/ov_SC04_011/ov_SC04_011_jr_801734BC.o": 0.173,
"build/src/ov_SC04_011/ov_SC04_011_jr_801789AC.o": 0.061,
"build/src/ov_SC04_011/ov_SC04_011_jr_80178D40.o": 0.094,
"build/src/ov_SC04_011/ov_SC04_011_jr_8017A4AC.o": 0.064,
"build/src/ov_SC04_011/ov_SC04_011_jr_8017AE2C.o": 0.095,
"build/src/ov_SC04_011/ov_SC04_011_jr_8017D494.o": 0.437,
"build/src/ov_SC04_011/ov_SC04_011_o0b.o": 0.052,
"build/src/ov_SC04_011/ov_SC04_011_o0c.o": 0.055
},
"ok": true,
"seconds": 2.4
"seconds": 2.3
}
.run/P36/delever/ledger.jsonl
+509
View File
File diff suppressed because one or more lines are too long
docs/lever-progress.tsv
+1
View File
@@ -18,3 +18,4 @@ date milestone head sites_AB pins asm bodies_AB distinct_AB marked unmarked gte_
2026-09-10 S102 T7 s7 (stopped early to restore agent cadence) — 5 of 207 judged at the wider width 724c68859 29140 16989 12151 9005 1280 29140 0 462 314 1590 50 7428 445 76
2026-09-10 S102 T7 a7 — func_801287B8: a truncated local extern was faking a pin; the missing call argument restored through a function-pointer cast (127 bodies) bb0e95c7c 29013 16862 12151 8878 1279 29013 0 462 314 1590 50 7428 445 76
2026-09-10 S102 T7 a4 — func_8016C49C: one do-while on the function's LAST statement doubles a loop-note reference weight and flips allocno_compare (126 bodies) 9f5b22176 28887 16736 12151 8752 1278 28887 0 462 314 1590 50 7428 445 76
2026-09-10 S102 T7 burst — a8/a12/a18/a19 banked (132+118+119+134 bodies): the call-arity class twice, a MEM_IN_STRUCT_P alias flip, and a sequence-point split fb6c857f7 27984 15965 12019 8249 1275 27984 0 462 314 1590 50 7428 445 76
1 date milestone head sites_AB pins asm bodies_AB distinct_AB marked unmarked gte_levers per_tu_asm_macros class_C class_D class_E class_F class_G
18 2026-09-10 S102 T7 s7 (stopped early to restore agent cadence) — 5 of 207 judged at the wider width 724c68859 29140 16989 12151 9005 1280 29140 0 462 314 1590 50 7428 445 76
19 2026-09-10 S102 T7 a7 — func_801287B8: a truncated local extern was faking a pin; the missing call argument restored through a function-pointer cast (127 bodies) bb0e95c7c 29013 16862 12151 8878 1279 29013 0 462 314 1590 50 7428 445 76
20 2026-09-10 S102 T7 a4 — func_8016C49C: one do-while on the function's LAST statement doubles a loop-note reference weight and flips allocno_compare (126 bodies) 9f5b22176 28887 16736 12151 8752 1278 28887 0 462 314 1590 50 7428 445 76
21 2026-09-10 S102 T7 burst — a8/a12/a18/a19 banked (132+118+119+134 bodies): the call-arity class twice, a MEM_IN_STRUCT_P alias flip, and a sequence-point split fb6c857f7 27984 15965 12019 8249 1275 27984 0 462 314 1590 50 7428 445 76
docs/levers.md
+10 -1
View File
@@ -64,6 +64,7 @@ counted, not marked). E, F and G belong to the canonical type layer and are the
| 2026-09-10 | S102 T7 s7 (stopped early to restore agent cadence) — 5 of 207 judged at the wider width | 16989 | 12151 | **29140** | 9005 | 1280 | 462 | 314 | 1590 | 50 | 7428 | 445 | 76 | `724c68859` |
| 2026-09-10 | S102 T7 a7 — func_801287B8: a truncated local extern was faking a pin; the missing call argument restored through a function-pointer cast (127 bodies) | 16862 | 12151 | **29013** | 8878 | 1279 | 462 | 314 | 1590 | 50 | 7428 | 445 | 76 | `bb0e95c7c` |
| 2026-09-10 | S102 T7 a4 — func_8016C49C: one do-while on the function's LAST statement doubles a loop-note reference weight and flips allocno_compare (126 bodies) | 16736 | 12151 | **28887** | 8752 | 1278 | 462 | 314 | 1590 | 50 | 7428 | 445 | 76 | `9f5b22176` |
| 2026-09-10 | S102 T7 burst — a8/a12/a18/a19 banked (132+118+119+134 bodies): the call-arity class twice, a MEM_IN_STRUCT_P alias flip, and a sequence-point split | 15965 | 12019 | **27984** | 8249 | 1275 | 462 | 314 | 1590 | 50 | 7428 | 445 | 76 | `fb6c857f7` |
### The campaign — every batch, from the ledger (derived on every render)
@@ -123,7 +124,15 @@ counted, not marked). E, F and G belong to the canonical type layer and are the
| `a7p` | 2026-09-10 | E | 0 | 0 | 0 | 126 | 126 |
| `a4` | 2026-09-10 | E | 0 | 0 | 0 | 1 | 1 |
| `a4p` | 2026-09-10 | E | 0 | 0 | 0 | 125 | 125 |
| **total** | | | **17,119** | **20,778** | **283** | **5,360** | **3,963** |
| `a8` | 2026-09-10 | E | 0 | 0 | 0 | 2 | 1 |
| `a8p` | 2026-09-10 | E | 0 | 0 | 0 | 262 | 131 |
| `a12` | 2026-09-10 | E | 0 | 0 | 0 | 1 | 1 |
| `a19` | 2026-09-10 | E | 0 | 0 | 0 | 3 | 1 |
| `a18` | 2026-09-10 | E | 0 | 0 | 0 | 1 | 1 |
| `a12p` | 2026-09-10 | E | 0 | 0 | 0 | 117 | 117 |
| `a19p` | 2026-09-10 | E | 0 | 0 | 0 | 399 | 133 |
| `a18p` | 2026-09-10 | E | 0 | 0 | 0 | 124 | 124 |
| **total** | | | **17,119** | **20,778** | **283** | **6,269** | **4,472** |
*Generated by `tools/lever_progress.py --render` from `.run/P36/census/lever_census.json` and `.run/P36/delever/ledger.jsonl`; the series lives in `docs/lever-progress.tsv` (R75: published numbers are generated, never typed).*
phase-ends/CURRENT_PHASE.md
+41 -1
View File
@@ -1116,7 +1116,47 @@ accumulate here as the phase produces them.**
line — the most informative line in a `.greg` dump — and its `Register N in M.` regex missed 7 of the 8 allocnos.
`lever_census --check: 28,887 pin/asm sites, 28,887 marked !FAKE, 0 UNMARKED — OK` (29,013 → 28,887); snapshot row 19.
## 🛑 SESSION CHECKPOINT — S101 (2026-09-09) / LIVE, refreshed S102 (2026-09-10): T0–T6 ☑, **T7 RUNNING — agent a1 BANKED + HARVESTED: `func_80156044` (130 bodies) and its move toolified as generator **R15, the sink**, which then closed 6 more exemplars (267 bodies) in 4 compiles each with no tokens; agent a2 banked 125 more; 30,358 → 29,572 sites, R22 218/218**; **lane B DELIVERED + 4 claims verified on bytes; lane A = rung G, `tools/delever_search.py`, BUILT, CONTROLLED, MEASURED over six runs (g1–g6b: 33,427 → 30,358 sites, 12,048 → 9,747 bodies, every bank R22 218/218, no drafting tokens); the head is where the number is (57 classes ≥100 copies = 7,318 of 9,796 residue bodies) and the wide search is spent on it; T7 APPROVED by Drew as ONE AGENT AT A TIME — the packs, the brief and the agent's scorer are built; NEXT = §2: start the serial agent loop IN THIS FRESH SESSION** | the number at this commit: **28,887 sites** in 8,752 bodies · marked 28,887 · UNMARKED 0 · orphans 0 — `lever_census --check` OK · `lever_progress --check` OK (19 milestones). **S102's loop state: the burst of 20 agents is in flight; a4 and a7 landed and banked (126 + 127 bodies); the build/ coupling is FIXED (a baseline snapshot the R22 gate cannot wipe), so the fleet gate and the agents are now independent.**
- **S102 — THE BURST OF 20 (Drew, 2026-09-10: "maintain your concurrency of 4 if you think that is best. but lets do a
burst. burst 20 agents now"). The first landings, and a CROSS-AGENT DEFECT they found for us.**
**The defect (fixed at its cause):** `score_file` called `compile_obj(..., tag="score")` with a CONSTANT tag, and
`compile_obj` names its scratch object `<obj>.<tag>.o` — keyed by the FILE. Nine of the burst's agents shared one
translation unit, so they wrote and read ONE object. Two reported it independently without either seeing the code: one
saw spurious `COMPILE-ERROR`s naming an unrelated header that re-ran clean, the other **scored four candidates against
another agent's function** before `--try`'s echo of the TU and function name gave it away. The tag is now per FUNCTION
(`score_<alias>_<fn>`). **Every landed body was re-verified after the fix and all still score 0** — the banks were
never at risk (the coordinator verifies serially and `apply_body_core` judges on the real recipes), but the agents'
own intermediate readings were.
**Banked from the burst so far — 503 bodies:** `func_801627E8` (a8, 132), `func_8017A3D8` (a12, 118),
`func_80141874` (a18, 119 of 125, 6 refused), `func_801345F8` (a19, 134). 28,887 → **27,984 sites**;
`lever_census --check: 27,984 pin/asm sites, 27,984 marked !FAKE, 0 UNMARKED — OK`; snapshot row 20.
**THE FINDING OF THE BURST — the biggest lever class in the phase is a WRONG DECLARATION, not codegen.** Four agents
independently reached score 0 by restoring a call's real arity, each in a different spelling:
*a7* `extern void func_8013BC7C(void);` against a shared body taking `void *` → a function-pointer cast at the call;
*a8* `extern void (*D_80192FD0[])(void);` → widen the block-scope prototype to `(u8 *)` and pass the pointer, which
removed BOTH its levers; *a12* `extern int func_8001AAA0(void);` against `void func_8001AAA0(s32)` at `src/800.c:7846`
— and another TU already declares it correctly and calls it with an argument; *a13* `func_80157D20` itself declared
`(void)` in 131 of its 138 defining sites while the target's prologue copies two parameter registers. The mechanisms
differ (combine's `added_sets_2` gate at `combine.c:1458`; `set_preference` `global.c:1589` applied ahead of first-fit
at `:1001-1015`, the argument copy becoming a self-move deleted by `jump_optimize` at `toplev.c:3142` so it costs ZERO
instructions; `assign_parms`' parameter home copies), but the class is one: **a truncated `(void)` declaration removes
an instruction the pin was then hired to fake.** No mechanical generator can reach it — every generator rewrites
statements that exist, and this changes a call's ARITY — which is why these bodies sat at 3 through thousands of
compiles across seven runs.
**a13 is the one that does NOT bank body-only:** `func_80157D20` reaches 0 only by widening its own `extern` line, and
gcc 2.7.2 rejects a block-scope redeclaration (`conflicting types`), so the body-only ceiling is 4. Its Path A (widen the
declaration in the 131 + 5 defining sites, worth 2 pins × 132 copies) is recorded for the types phase together with
`func_80136824` and a2's `func_80168828` — **three measured cases now, all the same shape.**
**Two more new classes, each byte-proven:** *a18* `func_80141874` — a plain scalar global's STORE sank past an array
load because `true_dependence`'s exception clause (`sched.c:837-839`) discards the edge when the load is in-struct and
varying and the store is neither, even though `memrefs_conflict_p` returns 1; declaring the global `extern u16 X[];` and
storing through `X[0]` sets `MEM_IN_STRUCT_P` on the store, the exception fails and the order is restored — and the
delevered body is SHORTER than the levered one. *a19* `func_801345F8` — a post-decrement inside a `while` condition is
QUEUED by `expand_increment` and flushed only at the next sequence point, so splitting it into its own statement (or a
comma operator) plus a `u16` destination that `insert_regs` (`cse.c:1017-1019`) refuses to join keeps the copy alive.
Its answer to the `$0` question is a correction worth keeping: `zr` is `register int __asm__("$0")` with NO initializer,
an opaque operand and NOT R16's constant holder — **R16 must refuse an uninitialised `register … __asm__` declaration.**
## 🛑 SESSION CHECKPOINT — S101 (2026-09-09) / LIVE, refreshed S102 (2026-09-10): T0–T6 ☑, **T7 RUNNING — agent a1 BANKED + HARVESTED: `func_80156044` (130 bodies) and its move toolified as generator **R15, the sink**, which then closed 6 more exemplars (267 bodies) in 4 compiles each with no tokens; agent a2 banked 125 more; 30,358 → 29,572 sites, R22 218/218**; **lane B DELIVERED + 4 claims verified on bytes; lane A = rung G, `tools/delever_search.py`, BUILT, CONTROLLED, MEASURED over six runs (g1–g6b: 33,427 → 30,358 sites, 12,048 → 9,747 bodies, every bank R22 218/218, no drafting tokens); the head is where the number is (57 classes ≥100 copies = 7,318 of 9,796 residue bodies) and the wide search is spent on it; T7 APPROVED by Drew as ONE AGENT AT A TIME — the packs, the brief and the agent's scorer are built; NEXT = §2: start the serial agent loop IN THIS FRESH SESSION** | the number at this commit: **27,984 sites** in 8,249 bodies · marked 27,984 · UNMARKED 0 · orphans 0 — `lever_census --check` OK · `lever_progress --check` OK (20 milestones). **S102's loop state: the burst of 20 is landing; a4/a7/a8/a12/a18/a19 banked (756 bodies); the per-file scratch-object collision is FIXED (per-function tag); the biggest class found is a truncated `(void)` DECLARATION, three cases of which need the types phase.**
### 0. How to use this block
A fresh session reads CLAUDE.md's load order, replays this block verbatim, confirms the effort (**Drew: `/effort xhigh`, Fable 5.1**
src/ov_MAIN_012/ov_MAIN_012_jr_80131340.c
+15 -13
View File
@@ -1883,19 +1883,18 @@ s32 func_801345F8(s32 arg)
extern u16 * D_8017E910;
extern u16 D_80184130;
register u16 *param_1 __asm__("$5") = ((u16 *)arg); // !FAKE: pin $5 — NEEDED DIFFERS (P36 rung B tus2)
register u16 *cc __asm__("$4") = D_8017E910; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
int c8000 = 0x8000;
register int zr __asm__("$0"); // !FAKE: pin $0 — NEEDED DIFFERS (P36 rung B tus2)
u32 c1, c2, uVar6, uVar2, cnt, v14;
u16 *ptmp, *puVar4, *puVar7, uVar1;
int hi, harg, iVar9, iVar8, uVar3, uVar10, tbl;
u16 *cc = D_8017E910;
u16 *param_1 = ((u16 *)arg);
u32 c1, c2, cnt, v14;
u16 uVar6, uVar2, rem;
u16 *ptmp, *puVar4, *puVar7, uVar1, harg;
int hi, iVar9, iVar8, uVar3, uVar10, tbl;
c1 = ((int)(cc[0] + c8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1 + zr;
c1 = ((int)(cc[0] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1;
if ((c1 & 0xffff) < (u32)param_1[2]) {
c2 = ((int)(cc[2] + c8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2 + zr;
c2 = ((int)(cc[2] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2;
if ((c2 & 0xffff) < (u32)param_1[3])
goto do_mult;
return 0;
@@ -1912,10 +1911,13 @@ s32 func_801345F8(s32 arg)
cnt = (u32)ptmp[1];
v14 = *(int *)(param_1 + 10);
puVar4 = (u16 *)(v14 + (u32)*ptmp + cnt * 2) - 1;
while (((cnt-- + zr) & 0xffff) != 0) {
for (;;) {
rem = cnt--;
if (rem == 0)
break;
uVar1 = *puVar4;
hi = uVar1 & 0x8000;
harg = hi + zr;
harg = hi;
if (hi == 0)
puVar7 = (u16 *)(iVar9 + (u32)uVar1 * 0x12);
else
src/ov_MAIN_012/ov_MAIN_012_jr_8015A3C8.c
+4 -5
View File
@@ -6133,16 +6133,15 @@ extern void func_801627C0(void);
void func_801627E8(void)
{
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_80180F24[])(void); /* word-stride table of dispatch fn pointers */
register u8 *p __asm__("$4") = (u8 *)&D_8011F750; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_80180F24[])(u8 *); /* word-stride table of dispatch fn pointers; each takes the ctl block */
u8 *p = (u8 *)&D_8011F750;
s32 idx;
__asm__ __volatile__("" : "=r"(p) : "0"(p)); /* materialize &D_8011F750 into $a0 (defeat %lo-fold of the lbu) */ // !FAKE: launder — NEEDED DIFFERS (P36 rung B tus2)
idx = *p;
if (idx != 0) {
idx = idx - 1;
D_80180F24[idx]();
D_80180F24[idx](p);
}
}
src/ov_SC01_000/ov_SC01_000_jr_8012ACE0.c
+15 -13
View File
@@ -2657,19 +2657,18 @@ s32 func_801345F8(s32 arg)
extern u16 * D_8017F198;
extern u16 D_801A4458;
register u16 *param_1 __asm__("$5") = ((u16 *)arg); // !FAKE: pin $5 — NEEDED DIFFERS (P36 rung B tus2)
register u16 *cc __asm__("$4") = D_8017F198; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
int c8000 = 0x8000;
register int zr __asm__("$0"); // !FAKE: pin $0 — NEEDED DIFFERS (P36 rung B tus2)
u32 c1, c2, uVar6, uVar2, cnt, v14;
u16 *ptmp, *puVar4, *puVar7, uVar1;
int hi, harg, iVar9, iVar8, uVar3, uVar10, tbl;
u16 *cc = D_8017F198;
u16 *param_1 = ((u16 *)arg);
u32 c1, c2, cnt, v14;
u16 uVar6, uVar2, rem;
u16 *ptmp, *puVar4, *puVar7, uVar1, harg;
int hi, iVar9, iVar8, uVar3, uVar10, tbl;
c1 = ((int)(cc[0] + c8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1 + zr;
c1 = ((int)(cc[0] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1;
if ((c1 & 0xffff) < (u32)param_1[2]) {
c2 = ((int)(cc[2] + c8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2 + zr;
c2 = ((int)(cc[2] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2;
if ((c2 & 0xffff) < (u32)param_1[3])
goto do_mult;
return 0;
@@ -2686,10 +2685,13 @@ s32 func_801345F8(s32 arg)
cnt = (u32)ptmp[1];
v14 = *(int *)(param_1 + 10);
puVar4 = (u16 *)(v14 + (u32)*ptmp + cnt * 2) - 1;
while (((cnt-- + zr) & 0xffff) != 0) {
for (;;) {
rem = cnt--;
if (rem == 0)
break;
uVar1 = *puVar4;
hi = uVar1 & 0x8000;
harg = hi + zr;
harg = hi;
if (hi == 0)
puVar7 = (u16 *)(iVar9 + (u32)uVar1 * 0x12);
else
src/ov_SC01_000/ov_SC01_000_jr_80140608.c
+3 -5
View File
@@ -1349,15 +1349,13 @@ extern unsigned short D_80115112;
void func_80141874(void) {
extern u16 D_8011511C;
extern u16 D_8011511C[];
extern u16 D_80115116;
extern void (*D_80180008[])(void);
register void (*fp)(void) __asm__("$2"); /* pin fn-ptr to $v0 → store retires early */ // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B tus2)
func_801754A8();
D_8011511E = func_80014ED4(0);
D_8011511C = func_80015018(0);
fp = D_80180008[D_80115112];
fp();
D_8011511C[0] = func_80015018(0);
D_80180008[D_80115112]();
func_80141C04();
D_80115116 += 1;
}
src/ov_SC01_000/ov_SC01_000_jr_8015C32C.c
+4 -5
View File
@@ -3934,16 +3934,15 @@ void func_80162760(void)
void func_801627E8(void)
{
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_801817AC[])(void); /* word-stride table of dispatch fn pointers */
register u8 *p __asm__("$4") = (u8 *)&D_8011F750; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_801817AC[])(u8 *); /* word-stride table of dispatch fn pointers; each takes the ctl block */
u8 *p = (u8 *)&D_8011F750;
s32 idx;
__asm__ __volatile__("" : "=r"(p) : "0"(p)); /* materialize &D_8011F750 into $a0 (defeat %lo-fold of the lbu) */ // !FAKE: launder — NEEDED DIFFERS (P36 rung B tus2)
idx = *p;
if (idx != 0) {
idx = idx - 1;
D_801817AC[idx]();
D_801817AC[idx](p);
}
}
src/ov_SC01_000/ov_SC01_000_jr_80178D40.c
+2 -2
View File
@@ -3507,10 +3507,10 @@ int func_8017A3D8(void)
return 0;
case 100:
{
register int a __asm__("$4"); // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus8)
int a;
a = D_801A56A8;
if (a != -1) {
return func_8001AAA0() != 0;
return ((int (*)(int))func_8001AAA0)(a) != 0;
}
return func_800D0CE0() == 1;
}
src/ov_SC01_001/ov_SC01_001_jr_8012ACE0.c
+15 -13
View File
@@ -2657,19 +2657,18 @@ s32 func_801345F8(s32 arg)
extern u16 * D_80183DE8;
extern u16 D_801EC6E8;
register u16 *param_1 __asm__("$5") = ((u16 *)arg); // !FAKE: pin $5 — NEEDED DIFFERS (P36 rung B tus2)
register u16 *cc __asm__("$4") = D_80183DE8; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
int c8000 = 0x8000;
register int zr __asm__("$0"); // !FAKE: pin $0 — NEEDED DIFFERS (P36 rung B tus2)
u32 c1, c2, uVar6, uVar2, cnt, v14;
u16 *ptmp, *puVar4, *puVar7, uVar1;
int hi, harg, iVar9, iVar8, uVar3, uVar10, tbl;
u16 *cc = D_80183DE8;
u16 *param_1 = ((u16 *)arg);
u32 c1, c2, cnt, v14;
u16 uVar6, uVar2, rem;
u16 *ptmp, *puVar4, *puVar7, uVar1, harg;
int hi, iVar9, iVar8, uVar3, uVar10, tbl;
c1 = ((int)(cc[0] + c8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1 + zr;
c1 = ((int)(cc[0] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1;
if ((c1 & 0xffff) < (u32)param_1[2]) {
c2 = ((int)(cc[2] + c8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2 + zr;
c2 = ((int)(cc[2] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2;
if ((c2 & 0xffff) < (u32)param_1[3])
goto do_mult;
return 0;
@@ -2686,10 +2685,13 @@ s32 func_801345F8(s32 arg)
cnt = (u32)ptmp[1];
v14 = *(int *)(param_1 + 10);
puVar4 = (u16 *)(v14 + (u32)*ptmp + cnt * 2) - 1;
while (((cnt-- + zr) & 0xffff) != 0) {
for (;;) {
rem = cnt--;
if (rem == 0)
break;
uVar1 = *puVar4;
hi = uVar1 & 0x8000;
harg = hi + zr;
harg = hi;
if (hi == 0)
puVar7 = (u16 *)(iVar9 + (u32)uVar1 * 0x12);
else
src/ov_SC01_001/ov_SC01_001_jr_80140608.c
+3 -5
View File
@@ -1349,15 +1349,13 @@ extern unsigned short D_80115112;
void func_80141874(void) {
extern u16 D_8011511C;
extern u16 D_8011511C[];
extern u16 D_80115116;
extern void (*D_80184C58[])(void);
register void (*fp)(void) __asm__("$2"); /* pin fn-ptr to $v0 → store retires early */ // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B tus2)
func_801754A8();
D_8011511E = func_80014ED4(0);
D_8011511C = func_80015018(0);
fp = D_80184C58[D_80115112];
fp();
D_8011511C[0] = func_80015018(0);
D_80184C58[D_80115112]();
func_80141C04();
D_80115116 += 1;
}
src/ov_SC01_001/ov_SC01_001_jr_8015C32C.c
+4 -5
View File
@@ -3931,16 +3931,15 @@ void func_80162760(void)
void func_801627E8(void)
{
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_801863FC[])(void); /* word-stride table of dispatch fn pointers */
register u8 *p __asm__("$4") = (u8 *)&D_8011F750; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_801863FC[])(u8 *); /* word-stride table of dispatch fn pointers; each takes the ctl block */
u8 *p = (u8 *)&D_8011F750;
s32 idx;
__asm__ __volatile__("" : "=r"(p) : "0"(p)); /* materialize &D_8011F750 into $a0 (defeat %lo-fold of the lbu) */ // !FAKE: launder — NEEDED DIFFERS (P36 rung B tus2)
idx = *p;
if (idx != 0) {
idx = idx - 1;
D_801863FC[idx]();
D_801863FC[idx](p);
}
}
src/ov_SC01_001/ov_SC01_001_jr_80178D40.c
+2 -2
View File
@@ -3505,10 +3505,10 @@ int func_8017A3D8(void)
return 0;
case 100:
{
register int a __asm__("$4"); // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus8)
int a;
a = D_801ED938;
if (a != -1) {
return func_8001AAA0() != 0;
return ((int (*)(int))func_8001AAA0)(a) != 0;
}
return func_800D0CE0() == 1;
}
src/ov_SC01_004/ov_SC01_004_jr_8012ACE0.c
+15 -13
View File
@@ -2658,19 +2658,18 @@ s32 func_801345F8(s32 arg)
extern u16 * D_8017F7AC;
extern u16 D_8018EE50;
register u16 *param_1 __asm__("$5") = ((u16 *)arg); // !FAKE: pin $5 — NEEDED DIFFERS (P36 rung B tus2)
register u16 *cc __asm__("$4") = D_8017F7AC; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
int c8000 = 0x8000;
register int zr __asm__("$0"); // !FAKE: pin $0 — NEEDED DIFFERS (P36 rung B tus2)
u32 c1, c2, uVar6, uVar2, cnt, v14;
u16 *ptmp, *puVar4, *puVar7, uVar1;
int hi, harg, iVar9, iVar8, uVar3, uVar10, tbl;
u16 *cc = D_8017F7AC;
u16 *param_1 = ((u16 *)arg);
u32 c1, c2, cnt, v14;
u16 uVar6, uVar2, rem;
u16 *ptmp, *puVar4, *puVar7, uVar1, harg;
int hi, iVar9, iVar8, uVar3, uVar10, tbl;
c1 = ((int)(cc[0] + c8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1 + zr;
c1 = ((int)(cc[0] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1;
if ((c1 & 0xffff) < (u32)param_1[2]) {
c2 = ((int)(cc[2] + c8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2 + zr;
c2 = ((int)(cc[2] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2;
if ((c2 & 0xffff) < (u32)param_1[3])
goto do_mult;
return 0;
@@ -2687,10 +2686,13 @@ s32 func_801345F8(s32 arg)
cnt = (u32)ptmp[1];
v14 = *(int *)(param_1 + 10);
puVar4 = (u16 *)(v14 + (u32)*ptmp + cnt * 2) - 1;
while (((cnt-- + zr) & 0xffff) != 0) {
for (;;) {
rem = cnt--;
if (rem == 0)
break;
uVar1 = *puVar4;
hi = uVar1 & 0x8000;
harg = hi + zr;
harg = hi;
if (hi == 0)
puVar7 = (u16 *)(iVar9 + (u32)uVar1 * 0x12);
else
src/ov_SC01_004/ov_SC01_004_jr_80140608.c
+3 -5
View File
@@ -1349,15 +1349,13 @@ extern unsigned short D_80115112;
void func_80141874(void) {
extern u16 D_8011511C;
extern u16 D_8011511C[];
extern u16 D_80115116;
extern void (*D_8018061C[])(void);
register void (*fp)(void) __asm__("$2"); /* pin fn-ptr to $v0 → store retires early */ // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B tus2)
func_801754A8();
D_8011511E = func_80014ED4(0);
D_8011511C = func_80015018(0);
fp = D_8018061C[D_80115112];
fp();
D_8011511C[0] = func_80015018(0);
D_8018061C[D_80115112]();
func_80141C04();
D_80115116 += 1;
}
src/ov_SC01_004/ov_SC01_004_jr_8015C32C.c
+4 -5
View File
@@ -3933,16 +3933,15 @@ void func_80162760(void)
void func_801627E8(void)
{
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_80181DC0[])(void); /* word-stride table of dispatch fn pointers */
register u8 *p __asm__("$4") = (u8 *)&D_8011F750; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_80181DC0[])(u8 *); /* word-stride table of dispatch fn pointers; each takes the ctl block */
u8 *p = (u8 *)&D_8011F750;
s32 idx;
__asm__ __volatile__("" : "=r"(p) : "0"(p)); /* materialize &D_8011F750 into $a0 (defeat %lo-fold of the lbu) */ // !FAKE: launder — NEEDED DIFFERS (P36 rung B tus2)
idx = *p;
if (idx != 0) {
idx = idx - 1;
D_80181DC0[idx]();
D_80181DC0[idx](p);
}
}
src/ov_SC01_004/ov_SC01_004_jr_80178D40.c
+2 -2
View File
@@ -3505,10 +3505,10 @@ int func_8017A3D8(void)
return 0;
case 100:
{
register int a __asm__("$4"); // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus8)
int a;
a = D_801900A0;
if (a != -1) {
return func_8001AAA0() != 0;
return ((int (*)(int))func_8001AAA0)(a) != 0;
}
return func_800D0CE0() == 1;
}
src/ov_SC01_005/ov_SC01_005_jr_8012ACE0.c
+15 -13
View File
@@ -2650,19 +2650,18 @@ s32 func_801345F8(s32 arg)
extern u16 * D_80182940;
extern u16 D_801CC5B0;
register u16 *param_1 __asm__("$5") = ((u16 *)arg); // !FAKE: pin $5 — NEEDED DIFFERS (P36 rung B tus2)
register u16 *cc __asm__("$4") = D_80182940; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
int c8000 = 0x8000;
register int zr __asm__("$0"); // !FAKE: pin $0 — NEEDED DIFFERS (P36 rung B tus2)
u32 c1, c2, uVar6, uVar2, cnt, v14;
u16 *ptmp, *puVar4, *puVar7, uVar1;
int hi, harg, iVar9, iVar8, uVar3, uVar10, tbl;
u16 *cc = D_80182940;
u16 *param_1 = ((u16 *)arg);
u32 c1, c2, cnt, v14;
u16 uVar6, uVar2, rem;
u16 *ptmp, *puVar4, *puVar7, uVar1, harg;
int hi, iVar9, iVar8, uVar3, uVar10, tbl;
c1 = ((int)(cc[0] + c8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1 + zr;
c1 = ((int)(cc[0] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1;
if ((c1 & 0xffff) < (u32)param_1[2]) {
c2 = ((int)(cc[2] + c8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2 + zr;
c2 = ((int)(cc[2] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2;
if ((c2 & 0xffff) < (u32)param_1[3])
goto do_mult;
return 0;
@@ -2679,10 +2678,13 @@ s32 func_801345F8(s32 arg)
cnt = (u32)ptmp[1];
v14 = *(int *)(param_1 + 10);
puVar4 = (u16 *)(v14 + (u32)*ptmp + cnt * 2) - 1;
while (((cnt-- + zr) & 0xffff) != 0) {
for (;;) {
rem = cnt--;
if (rem == 0)
break;
uVar1 = *puVar4;
hi = uVar1 & 0x8000;
harg = hi + zr;
harg = hi;
if (hi == 0)
puVar7 = (u16 *)(iVar9 + (u32)uVar1 * 0x12);
else
src/ov_SC01_005/ov_SC01_005_jr_80140608.c
+3 -5
View File
@@ -1349,15 +1349,13 @@ extern unsigned short D_80115112;
void func_80141874(void) {
extern u16 D_8011511C;
extern u16 D_8011511C[];
extern u16 D_80115116;
extern void (*D_801837B0[])(void);
register void (*fp)(void) __asm__("$2"); /* pin fn-ptr to $v0 → store retires early */ // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B tus2)
func_801754A8();
D_8011511E = func_80014ED4(0);
D_8011511C = func_80015018(0);
fp = D_801837B0[D_80115112];
fp();
D_8011511C[0] = func_80015018(0);
D_801837B0[D_80115112]();
func_80141C04();
D_80115116 += 1;
}
src/ov_SC01_005/ov_SC01_005_jr_8015C32C.c
+4 -5
View File
@@ -3933,16 +3933,15 @@ void func_80162760(void)
void func_801627E8(void)
{
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_80184F54[])(void); /* word-stride table of dispatch fn pointers */
register u8 *p __asm__("$4") = (u8 *)&D_8011F750; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_80184F54[])(u8 *); /* word-stride table of dispatch fn pointers; each takes the ctl block */
u8 *p = (u8 *)&D_8011F750;
s32 idx;
__asm__ __volatile__("" : "=r"(p) : "0"(p)); /* materialize &D_8011F750 into $a0 (defeat %lo-fold of the lbu) */ // !FAKE: launder — NEEDED DIFFERS (P36 rung B tus2)
idx = *p;
if (idx != 0) {
idx = idx - 1;
D_80184F54[idx]();
D_80184F54[idx](p);
}
}
src/ov_SC01_005/ov_SC01_005_jr_80178D40.c
+2 -2
View File
@@ -3505,10 +3505,10 @@ int func_8017A3D8(void)
return 0;
case 100:
{
register int a __asm__("$4"); // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus8)
int a;
a = D_801CD800;
if (a != -1) {
return func_8001AAA0() != 0;
return ((int (*)(int))func_8001AAA0)(a) != 0;
}
return func_800D0CE0() == 1;
}
src/ov_SC01_008/ov_SC01_008_jr_8012ACE0.c
+15 -13
View File
@@ -2658,19 +2658,18 @@ s32 func_801345F8(s32 arg)
extern u16 * D_8017FD20;
extern u16 D_801A2060;
register u16 *param_1 __asm__("$5") = ((u16 *)arg); // !FAKE: pin $5 — NEEDED DIFFERS (P36 rung B tus2)
register u16 *cc __asm__("$4") = D_8017FD20; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
int c8000 = 0x8000;
register int zr __asm__("$0"); // !FAKE: pin $0 — NEEDED DIFFERS (P36 rung B tus2)
u32 c1, c2, uVar6, uVar2, cnt, v14;
u16 *ptmp, *puVar4, *puVar7, uVar1;
int hi, harg, iVar9, iVar8, uVar3, uVar10, tbl;
u16 *cc = D_8017FD20;
u16 *param_1 = ((u16 *)arg);
u32 c1, c2, cnt, v14;
u16 uVar6, uVar2, rem;
u16 *ptmp, *puVar4, *puVar7, uVar1, harg;
int hi, iVar9, iVar8, uVar3, uVar10, tbl;
c1 = ((int)(cc[0] + c8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1 + zr;
c1 = ((int)(cc[0] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1;
if ((c1 & 0xffff) < (u32)param_1[2]) {
c2 = ((int)(cc[2] + c8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2 + zr;
c2 = ((int)(cc[2] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2;
if ((c2 & 0xffff) < (u32)param_1[3])
goto do_mult;
return 0;
@@ -2687,10 +2686,13 @@ s32 func_801345F8(s32 arg)
cnt = (u32)ptmp[1];
v14 = *(int *)(param_1 + 10);
puVar4 = (u16 *)(v14 + (u32)*ptmp + cnt * 2) - 1;
while (((cnt-- + zr) & 0xffff) != 0) {
for (;;) {
rem = cnt--;
if (rem == 0)
break;
uVar1 = *puVar4;
hi = uVar1 & 0x8000;
harg = hi + zr;
harg = hi;
if (hi == 0)
puVar7 = (u16 *)(iVar9 + (u32)uVar1 * 0x12);
else
src/ov_SC01_008/ov_SC01_008_jr_80140608.c
+3 -5
View File
@@ -1349,15 +1349,13 @@ extern unsigned short D_80115112;
void func_80141874(void) {
extern u16 D_8011511C;
extern u16 D_8011511C[];
extern u16 D_80115116;
extern void (*D_80180B90[])(void);
register void (*fp)(void) __asm__("$2"); /* pin fn-ptr to $v0 → store retires early */ // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B tus2)
func_801754A8();
D_8011511E = func_80014ED4(0);
D_8011511C = func_80015018(0);
fp = D_80180B90[D_80115112];
fp();
D_8011511C[0] = func_80015018(0);
D_80180B90[D_80115112]();
func_80141C04();
D_80115116 += 1;
}
src/ov_SC01_008/ov_SC01_008_jr_8015C32C.c
+4 -5
View File
@@ -3933,16 +3933,15 @@ void func_80162760(void)
void func_801627E8(void)
{
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_80182334[])(void); /* word-stride table of dispatch fn pointers */
register u8 *p __asm__("$4") = (u8 *)&D_8011F750; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_80182334[])(u8 *); /* word-stride table of dispatch fn pointers; each takes the ctl block */
u8 *p = (u8 *)&D_8011F750;
s32 idx;
__asm__ __volatile__("" : "=r"(p) : "0"(p)); /* materialize &D_8011F750 into $a0 (defeat %lo-fold of the lbu) */ // !FAKE: launder — NEEDED DIFFERS (P36 rung B tus2)
idx = *p;
if (idx != 0) {
idx = idx - 1;
D_80182334[idx]();
D_80182334[idx](p);
}
}
src/ov_SC01_008/ov_SC01_008_jr_80178D40.c
+2 -2
View File
@@ -3505,10 +3505,10 @@ int func_8017A3D8(void)
return 0;
case 100:
{
register int a __asm__("$4"); // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus8)
int a;
a = D_801A32B0;
if (a != -1) {
return func_8001AAA0() != 0;
return ((int (*)(int))func_8001AAA0)(a) != 0;
}
return func_800D0CE0() == 1;
}
src/ov_SC01_009/ov_SC01_009_jr_8012ACE0.c
+15 -13
View File
@@ -2658,19 +2658,18 @@ s32 func_801345F8(s32 arg)
extern u16 * D_80182F08;
extern u16 D_801F1EC0;
register u16 *param_1 __asm__("$5") = ((u16 *)arg); // !FAKE: pin $5 — NEEDED DIFFERS (P36 rung B tus2)
register u16 *cc __asm__("$4") = D_80182F08; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
int c8000 = 0x8000;
register int zr __asm__("$0"); // !FAKE: pin $0 — NEEDED DIFFERS (P36 rung B tus2)
u32 c1, c2, uVar6, uVar2, cnt, v14;
u16 *ptmp, *puVar4, *puVar7, uVar1;
int hi, harg, iVar9, iVar8, uVar3, uVar10, tbl;
u16 *cc = D_80182F08;
u16 *param_1 = ((u16 *)arg);
u32 c1, c2, cnt, v14;
u16 uVar6, uVar2, rem;
u16 *ptmp, *puVar4, *puVar7, uVar1, harg;
int hi, iVar9, iVar8, uVar3, uVar10, tbl;
c1 = ((int)(cc[0] + c8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1 + zr;
c1 = ((int)(cc[0] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1;
if ((c1 & 0xffff) < (u32)param_1[2]) {
c2 = ((int)(cc[2] + c8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2 + zr;
c2 = ((int)(cc[2] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2;
if ((c2 & 0xffff) < (u32)param_1[3])
goto do_mult;
return 0;
@@ -2687,10 +2686,13 @@ s32 func_801345F8(s32 arg)
cnt = (u32)ptmp[1];
v14 = *(int *)(param_1 + 10);
puVar4 = (u16 *)(v14 + (u32)*ptmp + cnt * 2) - 1;
while (((cnt-- + zr) & 0xffff) != 0) {
for (;;) {
rem = cnt--;
if (rem == 0)
break;
uVar1 = *puVar4;
hi = uVar1 & 0x8000;
harg = hi + zr;
harg = hi;
if (hi == 0)
puVar7 = (u16 *)(iVar9 + (u32)uVar1 * 0x12);
else
src/ov_SC01_009/ov_SC01_009_jr_80140608.c
+3 -5
View File
@@ -1349,15 +1349,13 @@ extern unsigned short D_80115112;
void func_80141874(void) {
extern u16 D_8011511C;
extern u16 D_8011511C[];
extern u16 D_80115116;
extern void (*D_80183D78[])(void);
register void (*fp)(void) __asm__("$2"); /* pin fn-ptr to $v0 → store retires early */ // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B tus2)
func_801754A8();
D_8011511E = func_80014ED4(0);
D_8011511C = func_80015018(0);
fp = D_80183D78[D_80115112];
fp();
D_8011511C[0] = func_80015018(0);
D_80183D78[D_80115112]();
func_80141C04();
D_80115116 += 1;
}
src/ov_SC01_009/ov_SC01_009_jr_8015C32C.c
+4 -5
View File
@@ -3933,16 +3933,15 @@ void func_80162760(void)
void func_801627E8(void)
{
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_8018551C[])(void); /* word-stride table of dispatch fn pointers */
register u8 *p __asm__("$4") = (u8 *)&D_8011F750; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_8018551C[])(u8 *); /* word-stride table of dispatch fn pointers; each takes the ctl block */
u8 *p = (u8 *)&D_8011F750;
s32 idx;
__asm__ __volatile__("" : "=r"(p) : "0"(p)); /* materialize &D_8011F750 into $a0 (defeat %lo-fold of the lbu) */ // !FAKE: launder — NEEDED DIFFERS (P36 rung B tus2)
idx = *p;
if (idx != 0) {
idx = idx - 1;
D_8018551C[idx]();
D_8018551C[idx](p);
}
}
src/ov_SC01_074/ov_SC01_074_jr_8012ACE0.c
+15 -13
View File
@@ -2658,19 +2658,18 @@ s32 func_801345F8(s32 arg)
extern u16 * D_8017EB88;
extern u16 D_8019A940;
register u16 *param_1 __asm__("$5") = ((u16 *)arg); // !FAKE: pin $5 — NEEDED DIFFERS (P36 rung B tus2)
register u16 *cc __asm__("$4") = D_8017EB88; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
int c8000 = 0x8000;
register int zr __asm__("$0"); // !FAKE: pin $0 — NEEDED DIFFERS (P36 rung B tus2)
u32 c1, c2, uVar6, uVar2, cnt, v14;
u16 *ptmp, *puVar4, *puVar7, uVar1;
int hi, harg, iVar9, iVar8, uVar3, uVar10, tbl;
u16 *cc = D_8017EB88;
u16 *param_1 = ((u16 *)arg);
u32 c1, c2, cnt, v14;
u16 uVar6, uVar2, rem;
u16 *ptmp, *puVar4, *puVar7, uVar1, harg;
int hi, iVar9, iVar8, uVar3, uVar10, tbl;
c1 = ((int)(cc[0] + c8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1 + zr;
c1 = ((int)(cc[0] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1;
if ((c1 & 0xffff) < (u32)param_1[2]) {
c2 = ((int)(cc[2] + c8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2 + zr;
c2 = ((int)(cc[2] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2;
if ((c2 & 0xffff) < (u32)param_1[3])
goto do_mult;
return 0;
@@ -2687,10 +2686,13 @@ s32 func_801345F8(s32 arg)
cnt = (u32)ptmp[1];
v14 = *(int *)(param_1 + 10);
puVar4 = (u16 *)(v14 + (u32)*ptmp + cnt * 2) - 1;
while (((cnt-- + zr) & 0xffff) != 0) {
for (;;) {
rem = cnt--;
if (rem == 0)
break;
uVar1 = *puVar4;
hi = uVar1 & 0x8000;
harg = hi + zr;
harg = hi;
if (hi == 0)
puVar7 = (u16 *)(iVar9 + (u32)uVar1 * 0x12);
else
src/ov_SC01_074/ov_SC01_074_jr_80140608.c
+3 -5
View File
@@ -1350,15 +1350,13 @@ extern unsigned short D_80115112;
void func_80141874(void) {
extern u16 D_8011511C;
extern u16 D_8011511C[];
extern u16 D_80115116;
extern void (*D_8017F9F8[])(void);
register void (*fp)(void) __asm__("$2"); /* pin fn-ptr to $v0 → store retires early */ // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B tus2)
func_801754A8();
D_8011511E = func_80014ED4(0);
D_8011511C = func_80015018(0);
fp = D_8017F9F8[D_80115112];
fp();
D_8011511C[0] = func_80015018(0);
D_8017F9F8[D_80115112]();
func_80141C04();
D_80115116 += 1;
}
src/ov_SC01_074/ov_SC01_074_jr_8015C32C.c
+4 -5
View File
@@ -3933,16 +3933,15 @@ void func_80162760(void)
void func_801627E8(void)
{
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_8018119C[])(void); /* word-stride table of dispatch fn pointers */
register u8 *p __asm__("$4") = (u8 *)&D_8011F750; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_8018119C[])(u8 *); /* word-stride table of dispatch fn pointers; each takes the ctl block */
u8 *p = (u8 *)&D_8011F750;
s32 idx;
__asm__ __volatile__("" : "=r"(p) : "0"(p)); /* materialize &D_8011F750 into $a0 (defeat %lo-fold of the lbu) */ // !FAKE: launder — NEEDED DIFFERS (P36 rung B tus2)
idx = *p;
if (idx != 0) {
idx = idx - 1;
D_8018119C[idx]();
D_8018119C[idx](p);
}
}
src/ov_SC01_074/ov_SC01_074_jr_80178D40.c
+2 -2
View File
@@ -3505,10 +3505,10 @@ int func_8017A3D8(void)
return 0;
case 100:
{
register int a __asm__("$4"); // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus8)
int a;
a = D_8019BB90;
if (a != -1) {
return func_8001AAA0() != 0;
return ((int (*)(int))func_8001AAA0)(a) != 0;
}
return func_800D0CE0() == 1;
}
src/ov_SC01_077/ov_SC01_077_jr_8012ACE0.c
+15 -13
View File
@@ -3044,19 +3044,18 @@ s32 func_801345F8(s32 arg)
extern u16 * D_801870AC;
extern u16 D_801D9500;
register u16 *param_1 __asm__("$5") = ((u16 *)arg); // !FAKE: pin $5 — NEEDED DIFFERS (P36 rung B tus2)
register u16 *cc __asm__("$4") = D_801870AC; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
int c8000 = 0x8000;
register int zr __asm__("$0"); // !FAKE: pin $0 — NEEDED DIFFERS (P36 rung B tus2)
u32 c1, c2, uVar6, uVar2, cnt, v14;
u16 *ptmp, *puVar4, *puVar7, uVar1;
int hi, harg, iVar9, iVar8, uVar3, uVar10, tbl;
u16 *cc = D_801870AC;
u16 *param_1 = ((u16 *)arg);
u32 c1, c2, cnt, v14;
u16 uVar6, uVar2, rem;
u16 *ptmp, *puVar4, *puVar7, uVar1, harg;
int hi, iVar9, iVar8, uVar3, uVar10, tbl;
c1 = ((int)(cc[0] + c8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1 + zr;
c1 = ((int)(cc[0] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1;
if ((c1 & 0xffff) < (u32)param_1[2]) {
c2 = ((int)(cc[2] + c8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2 + zr;
c2 = ((int)(cc[2] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2;
if ((c2 & 0xffff) < (u32)param_1[3])
goto do_mult;
return 0;
@@ -3073,10 +3072,13 @@ s32 func_801345F8(s32 arg)
cnt = (u32)ptmp[1];
v14 = *(int *)(param_1 + 10);
puVar4 = (u16 *)(v14 + (u32)*ptmp + cnt * 2) - 1;
while (((cnt-- + zr) & 0xffff) != 0) {
for (;;) {
rem = cnt--;
if (rem == 0)
break;
uVar1 = *puVar4;
hi = uVar1 & 0x8000;
harg = hi + zr;
harg = hi;
if (hi == 0)
puVar7 = (u16 *)(iVar9 + (u32)uVar1 * 0x12);
else
src/ov_SC01_077/ov_SC01_077_jr_80178D40.c
+2 -2
View File
@@ -3644,10 +3644,10 @@ int func_8017A3D8(void)
return 0;
case 100:
{
register int a __asm__("$4"); // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus8)
int a;
a = D_801DA750;
if (a != -1) {
return func_8001AAA0() != 0;
return ((int (*)(int))func_8001AAA0)(a) != 0;
}
return func_800D0CE0() == 1;
}
src/ov_SC01_080/ov_SC01_080_jr_8012ACE0.c
+15 -13
View File
@@ -2658,19 +2658,18 @@ s32 func_801345F8(s32 arg)
extern u16 * D_80183AE8;
extern u16 D_801C4770;
register u16 *param_1 __asm__("$5") = ((u16 *)arg); // !FAKE: pin $5 — NEEDED DIFFERS (P36 rung B tus2)
register u16 *cc __asm__("$4") = D_80183AE8; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
int c8000 = 0x8000;
register int zr __asm__("$0"); // !FAKE: pin $0 — NEEDED DIFFERS (P36 rung B tus2)
u32 c1, c2, uVar6, uVar2, cnt, v14;
u16 *ptmp, *puVar4, *puVar7, uVar1;
int hi, harg, iVar9, iVar8, uVar3, uVar10, tbl;
u16 *cc = D_80183AE8;
u16 *param_1 = ((u16 *)arg);
u32 c1, c2, cnt, v14;
u16 uVar6, uVar2, rem;
u16 *ptmp, *puVar4, *puVar7, uVar1, harg;
int hi, iVar9, iVar8, uVar3, uVar10, tbl;
c1 = ((int)(cc[0] + c8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1 + zr;
c1 = ((int)(cc[0] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1;
if ((c1 & 0xffff) < (u32)param_1[2]) {
c2 = ((int)(cc[2] + c8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2 + zr;
c2 = ((int)(cc[2] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2;
if ((c2 & 0xffff) < (u32)param_1[3])
goto do_mult;
return 0;
@@ -2687,10 +2686,13 @@ s32 func_801345F8(s32 arg)
cnt = (u32)ptmp[1];
v14 = *(int *)(param_1 + 10);
puVar4 = (u16 *)(v14 + (u32)*ptmp + cnt * 2) - 1;
while (((cnt-- + zr) & 0xffff) != 0) {
for (;;) {
rem = cnt--;
if (rem == 0)
break;
uVar1 = *puVar4;
hi = uVar1 & 0x8000;
harg = hi + zr;
harg = hi;
if (hi == 0)
puVar7 = (u16 *)(iVar9 + (u32)uVar1 * 0x12);
else
src/ov_SC01_080/ov_SC01_080_jr_80140608.c
+3 -5
View File
@@ -1350,15 +1350,13 @@ extern unsigned short D_80115112;
void func_80141874(void) {
extern u16 D_8011511C;
extern u16 D_8011511C[];
extern u16 D_80115116;
extern void (*D_80184958[])(void);
register void (*fp)(void) __asm__("$2"); /* pin fn-ptr to $v0 → store retires early */ // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B tus2)
func_801754A8();
D_8011511E = func_80014ED4(0);
D_8011511C = func_80015018(0);
fp = D_80184958[D_80115112];
fp();
D_8011511C[0] = func_80015018(0);
D_80184958[D_80115112]();
func_80141C04();
D_80115116 += 1;
}
src/ov_SC01_080/ov_SC01_080_jr_8015C32C.c
+4 -5
View File
@@ -3933,16 +3933,15 @@ void func_80162760(void)
void func_801627E8(void)
{
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_801860FC[])(void); /* word-stride table of dispatch fn pointers */
register u8 *p __asm__("$4") = (u8 *)&D_8011F750; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_801860FC[])(u8 *); /* word-stride table of dispatch fn pointers; each takes the ctl block */
u8 *p = (u8 *)&D_8011F750;
s32 idx;
__asm__ __volatile__("" : "=r"(p) : "0"(p)); /* materialize &D_8011F750 into $a0 (defeat %lo-fold of the lbu) */ // !FAKE: launder — NEEDED DIFFERS (P36 rung B tus2)
idx = *p;
if (idx != 0) {
idx = idx - 1;
D_801860FC[idx]();
D_801860FC[idx](p);
}
}
src/ov_SC01_080/ov_SC01_080_jr_80178D40.c
+2 -2
View File
@@ -3505,10 +3505,10 @@ int func_8017A3D8(void)
return 0;
case 100:
{
register int a __asm__("$4"); // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus8)
int a;
a = D_801C59C0;
if (a != -1) {
return func_8001AAA0() != 0;
return ((int (*)(int))func_8001AAA0)(a) != 0;
}
return func_800D0CE0() == 1;
}
src/ov_SC01_084/ov_SC01_084_jr_8012ACE0.c
+15 -13
View File
@@ -2658,19 +2658,18 @@ s32 func_801345F8(s32 arg)
extern u16 * D_80186DDC;
extern u16 D_801C6218;
register u16 *param_1 __asm__("$5") = ((u16 *)arg); // !FAKE: pin $5 — NEEDED DIFFERS (P36 rung B tus2)
register u16 *cc __asm__("$4") = D_80186DDC; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
int c8000 = 0x8000;
register int zr __asm__("$0"); // !FAKE: pin $0 — NEEDED DIFFERS (P36 rung B tus2)
u32 c1, c2, uVar6, uVar2, cnt, v14;
u16 *ptmp, *puVar4, *puVar7, uVar1;
int hi, harg, iVar9, iVar8, uVar3, uVar10, tbl;
u16 *cc = D_80186DDC;
u16 *param_1 = ((u16 *)arg);
u32 c1, c2, cnt, v14;
u16 uVar6, uVar2, rem;
u16 *ptmp, *puVar4, *puVar7, uVar1, harg;
int hi, iVar9, iVar8, uVar3, uVar10, tbl;
c1 = ((int)(cc[0] + c8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1 + zr;
c1 = ((int)(cc[0] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1;
if ((c1 & 0xffff) < (u32)param_1[2]) {
c2 = ((int)(cc[2] + c8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2 + zr;
c2 = ((int)(cc[2] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2;
if ((c2 & 0xffff) < (u32)param_1[3])
goto do_mult;
return 0;
@@ -2687,10 +2686,13 @@ s32 func_801345F8(s32 arg)
cnt = (u32)ptmp[1];
v14 = *(int *)(param_1 + 10);
puVar4 = (u16 *)(v14 + (u32)*ptmp + cnt * 2) - 1;
while (((cnt-- + zr) & 0xffff) != 0) {
for (;;) {
rem = cnt--;
if (rem == 0)
break;
uVar1 = *puVar4;
hi = uVar1 & 0x8000;
harg = hi + zr;
harg = hi;
if (hi == 0)
puVar7 = (u16 *)(iVar9 + (u32)uVar1 * 0x12);
else
src/ov_SC01_084/ov_SC01_084_jr_80140608.c
+3 -5
View File
@@ -1350,15 +1350,13 @@ extern unsigned short D_80115112;
void func_80141874(void) {
extern u16 D_8011511C;
extern u16 D_8011511C[];
extern u16 D_80115116;
extern void (*D_80187C4C[])(void);
register void (*fp)(void) __asm__("$2"); /* pin fn-ptr to $v0 → store retires early */ // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B tus2)
func_801754A8();
D_8011511E = func_80014ED4(0);
D_8011511C = func_80015018(0);
fp = D_80187C4C[D_80115112];
fp();
D_8011511C[0] = func_80015018(0);
D_80187C4C[D_80115112]();
func_80141C04();
D_80115116 += 1;
}
src/ov_SC01_084/ov_SC01_084_jr_8015C32C.c
+4 -5
View File
@@ -3932,16 +3932,15 @@ void func_80162760(void)
void func_801627E8(void)
{
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_801893F0[])(void); /* word-stride table of dispatch fn pointers */
register u8 *p __asm__("$4") = (u8 *)&D_8011F750; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_801893F0[])(u8 *); /* word-stride table of dispatch fn pointers; each takes the ctl block */
u8 *p = (u8 *)&D_8011F750;
s32 idx;
__asm__ __volatile__("" : "=r"(p) : "0"(p)); /* materialize &D_8011F750 into $a0 (defeat %lo-fold of the lbu) */ // !FAKE: launder — NEEDED DIFFERS (P36 rung B tus2)
idx = *p;
if (idx != 0) {
idx = idx - 1;
D_801893F0[idx]();
D_801893F0[idx](p);
}
}
src/ov_SC01_084/ov_SC01_084_jr_80178D40.c
+2 -2
View File
@@ -3506,10 +3506,10 @@ int func_8017A3D8(void)
return 0;
case 100:
{
register int a __asm__("$4"); // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus8)
int a;
a = D_801C7468;
if (a != -1) {
return func_8001AAA0() != 0;
return ((int (*)(int))func_8001AAA0)(a) != 0;
}
return func_800D0CE0() == 1;
}
src/ov_SC02_000/ov_SC02_000_jr_8012ACE0.c
+15 -13
View File
@@ -2655,19 +2655,18 @@ s32 func_801345F8(s32 arg)
extern u16 * D_8018B18C;
extern u16 D_801E6D48;
register u16 *param_1 __asm__("$5") = ((u16 *)arg); // !FAKE: pin $5 — NEEDED DIFFERS (P36 rung B tus2)
register u16 *cc __asm__("$4") = D_8018B18C; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
int c8000 = 0x8000;
register int zr __asm__("$0"); // !FAKE: pin $0 — NEEDED DIFFERS (P36 rung B tus2)
u32 c1, c2, uVar6, uVar2, cnt, v14;
u16 *ptmp, *puVar4, *puVar7, uVar1;
int hi, harg, iVar9, iVar8, uVar3, uVar10, tbl;
u16 *cc = D_8018B18C;
u16 *param_1 = ((u16 *)arg);
u32 c1, c2, cnt, v14;
u16 uVar6, uVar2, rem;
u16 *ptmp, *puVar4, *puVar7, uVar1, harg;
int hi, iVar9, iVar8, uVar3, uVar10, tbl;
c1 = ((int)(cc[0] + c8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1 + zr;
c1 = ((int)(cc[0] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1;
if ((c1 & 0xffff) < (u32)param_1[2]) {
c2 = ((int)(cc[2] + c8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2 + zr;
c2 = ((int)(cc[2] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2;
if ((c2 & 0xffff) < (u32)param_1[3])
goto do_mult;
return 0;
@@ -2684,10 +2683,13 @@ s32 func_801345F8(s32 arg)
cnt = (u32)ptmp[1];
v14 = *(int *)(param_1 + 10);
puVar4 = (u16 *)(v14 + (u32)*ptmp + cnt * 2) - 1;
while (((cnt-- + zr) & 0xffff) != 0) {
for (;;) {
rem = cnt--;
if (rem == 0)
break;
uVar1 = *puVar4;
hi = uVar1 & 0x8000;
harg = hi + zr;
harg = hi;
if (hi == 0)
puVar7 = (u16 *)(iVar9 + (u32)uVar1 * 0x12);
else
src/ov_SC02_000/ov_SC02_000_jr_80140608.c
+3 -5
View File
@@ -1349,15 +1349,13 @@ extern unsigned short D_80115112;
void func_80141874(void) {
extern u16 D_8011511C;
extern u16 D_8011511C[];
extern u16 D_80115116;
extern void (*D_8018BFFC[])(void);
register void (*fp)(void) __asm__("$2"); /* pin fn-ptr to $v0 → store retires early */ // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B tus2)
func_801754A8();
D_8011511E = func_80014ED4(0);
D_8011511C = func_80015018(0);
fp = D_8018BFFC[D_80115112];
fp();
D_8011511C[0] = func_80015018(0);
D_8018BFFC[D_80115112]();
func_80141C04();
D_80115116 += 1;
}
src/ov_SC02_000/ov_SC02_000_jr_8015C32C.c
+4 -5
View File
@@ -3931,16 +3931,15 @@ void func_80162760(void)
void func_801627E8(void)
{
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_8018D7A0[])(void); /* word-stride table of dispatch fn pointers */
register u8 *p __asm__("$4") = (u8 *)&D_8011F750; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_8018D7A0[])(u8 *); /* word-stride table of dispatch fn pointers; each takes the ctl block */
u8 *p = (u8 *)&D_8011F750;
s32 idx;
__asm__ __volatile__("" : "=r"(p) : "0"(p)); /* materialize &D_8011F750 into $a0 (defeat %lo-fold of the lbu) */ // !FAKE: launder — NEEDED DIFFERS (P36 rung B tus2)
idx = *p;
if (idx != 0) {
idx = idx - 1;
D_8018D7A0[idx]();
D_8018D7A0[idx](p);
}
}
src/ov_SC02_000/ov_SC02_000_jr_80178D40.c
+2 -2
View File
@@ -3503,10 +3503,10 @@ int func_8017A3D8(void)
return 0;
case 100:
{
register int a __asm__("$4"); // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus8)
int a;
a = D_801E7F98;
if (a != -1) {
return func_8001AAA0() != 0;
return ((int (*)(int))func_8001AAA0)(a) != 0;
}
return func_800D0CE0() == 1;
}
src/ov_SC02_004/ov_SC02_004_jr_8012ACE0.c
+15 -13
View File
@@ -2658,19 +2658,18 @@ s32 func_801345F8(s32 arg)
extern u16 * D_8017E26C;
extern u16 D_80194F98;
register u16 *param_1 __asm__("$5") = ((u16 *)arg); // !FAKE: pin $5 — NEEDED DIFFERS (P36 rung B tus2)
register u16 *cc __asm__("$4") = D_8017E26C; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
int c8000 = 0x8000;
register int zr __asm__("$0"); // !FAKE: pin $0 — NEEDED DIFFERS (P36 rung B tus2)
u32 c1, c2, uVar6, uVar2, cnt, v14;
u16 *ptmp, *puVar4, *puVar7, uVar1;
int hi, harg, iVar9, iVar8, uVar3, uVar10, tbl;
u16 *cc = D_8017E26C;
u16 *param_1 = ((u16 *)arg);
u32 c1, c2, cnt, v14;
u16 uVar6, uVar2, rem;
u16 *ptmp, *puVar4, *puVar7, uVar1, harg;
int hi, iVar9, iVar8, uVar3, uVar10, tbl;
c1 = ((int)(cc[0] + c8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1 + zr;
c1 = ((int)(cc[0] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1;
if ((c1 & 0xffff) < (u32)param_1[2]) {
c2 = ((int)(cc[2] + c8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2 + zr;
c2 = ((int)(cc[2] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2;
if ((c2 & 0xffff) < (u32)param_1[3])
goto do_mult;
return 0;
@@ -2687,10 +2686,13 @@ s32 func_801345F8(s32 arg)
cnt = (u32)ptmp[1];
v14 = *(int *)(param_1 + 10);
puVar4 = (u16 *)(v14 + (u32)*ptmp + cnt * 2) - 1;
while (((cnt-- + zr) & 0xffff) != 0) {
for (;;) {
rem = cnt--;
if (rem == 0)
break;
uVar1 = *puVar4;
hi = uVar1 & 0x8000;
harg = hi + zr;
harg = hi;
if (hi == 0)
puVar7 = (u16 *)(iVar9 + (u32)uVar1 * 0x12);
else
src/ov_SC02_004/ov_SC02_004_jr_80140608.c
+3 -5
View File
@@ -1350,15 +1350,13 @@ extern unsigned short D_80115112;
void func_80141874(void) {
extern u16 D_8011511C;
extern u16 D_8011511C[];
extern u16 D_80115116;
extern void (*D_8017F0DC[])(void);
register void (*fp)(void) __asm__("$2"); /* pin fn-ptr to $v0 → store retires early */ // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B tus2)
func_801754A8();
D_8011511E = func_80014ED4(0);
D_8011511C = func_80015018(0);
fp = D_8017F0DC[D_80115112];
fp();
D_8011511C[0] = func_80015018(0);
D_8017F0DC[D_80115112]();
func_80141C04();
D_80115116 += 1;
}
src/ov_SC02_004/ov_SC02_004_jr_8015C32C.c
+4 -5
View File
@@ -3933,16 +3933,15 @@ void func_80162760(void)
void func_801627E8(void)
{
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_80180880[])(void); /* word-stride table of dispatch fn pointers */
register u8 *p __asm__("$4") = (u8 *)&D_8011F750; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_80180880[])(u8 *); /* word-stride table of dispatch fn pointers; each takes the ctl block */
u8 *p = (u8 *)&D_8011F750;
s32 idx;
__asm__ __volatile__("" : "=r"(p) : "0"(p)); /* materialize &D_8011F750 into $a0 (defeat %lo-fold of the lbu) */ // !FAKE: launder — NEEDED DIFFERS (P36 rung B tus2)
idx = *p;
if (idx != 0) {
idx = idx - 1;
D_80180880[idx]();
D_80180880[idx](p);
}
}
src/ov_SC02_004/ov_SC02_004_jr_80178D40.c
+2 -2
View File
@@ -3505,10 +3505,10 @@ int func_8017A3D8(void)
return 0;
case 100:
{
register int a __asm__("$4"); // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus8)
int a;
a = D_801961E8;
if (a != -1) {
return func_8001AAA0() != 0;
return ((int (*)(int))func_8001AAA0)(a) != 0;
}
return func_800D0CE0() == 1;
}
src/ov_SC02_005/ov_SC02_005_jr_8012ACE0.c
+15 -13
View File
@@ -2658,19 +2658,18 @@ s32 func_801345F8(s32 arg)
extern u16 * D_80190E70;
extern u16 D_801E3010;
register u16 *param_1 __asm__("$5") = ((u16 *)arg); // !FAKE: pin $5 — NEEDED DIFFERS (P36 rung B tus2)
register u16 *cc __asm__("$4") = D_80190E70; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
int c8000 = 0x8000;
register int zr __asm__("$0"); // !FAKE: pin $0 — NEEDED DIFFERS (P36 rung B tus2)
u32 c1, c2, uVar6, uVar2, cnt, v14;
u16 *ptmp, *puVar4, *puVar7, uVar1;
int hi, harg, iVar9, iVar8, uVar3, uVar10, tbl;
u16 *cc = D_80190E70;
u16 *param_1 = ((u16 *)arg);
u32 c1, c2, cnt, v14;
u16 uVar6, uVar2, rem;
u16 *ptmp, *puVar4, *puVar7, uVar1, harg;
int hi, iVar9, iVar8, uVar3, uVar10, tbl;
c1 = ((int)(cc[0] + c8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1 + zr;
c1 = ((int)(cc[0] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1;
if ((c1 & 0xffff) < (u32)param_1[2]) {
c2 = ((int)(cc[2] + c8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2 + zr;
c2 = ((int)(cc[2] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2;
if ((c2 & 0xffff) < (u32)param_1[3])
goto do_mult;
return 0;
@@ -2687,10 +2686,13 @@ s32 func_801345F8(s32 arg)
cnt = (u32)ptmp[1];
v14 = *(int *)(param_1 + 10);
puVar4 = (u16 *)(v14 + (u32)*ptmp + cnt * 2) - 1;
while (((cnt-- + zr) & 0xffff) != 0) {
for (;;) {
rem = cnt--;
if (rem == 0)
break;
uVar1 = *puVar4;
hi = uVar1 & 0x8000;
harg = hi + zr;
harg = hi;
if (hi == 0)
puVar7 = (u16 *)(iVar9 + (u32)uVar1 * 0x12);
else
src/ov_SC02_005/ov_SC02_005_jr_80140608.c
+3 -5
View File
@@ -1350,15 +1350,13 @@ extern unsigned short D_80115112;
void func_80141874(void) {
extern u16 D_8011511C;
extern u16 D_8011511C[];
extern u16 D_80115116;
extern void (*D_80191CE0[])(void);
register void (*fp)(void) __asm__("$2"); /* pin fn-ptr to $v0 → store retires early */ // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B tus2)
func_801754A8();
D_8011511E = func_80014ED4(0);
D_8011511C = func_80015018(0);
fp = D_80191CE0[D_80115112];
fp();
D_8011511C[0] = func_80015018(0);
D_80191CE0[D_80115112]();
func_80141C04();
D_80115116 += 1;
}
src/ov_SC02_005/ov_SC02_005_jr_8015C32C.c
+4 -5
View File
@@ -3931,16 +3931,15 @@ void func_80162760(void)
void func_801627E8(void)
{
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_80193484[])(void); /* word-stride table of dispatch fn pointers */
register u8 *p __asm__("$4") = (u8 *)&D_8011F750; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_80193484[])(u8 *); /* word-stride table of dispatch fn pointers; each takes the ctl block */
u8 *p = (u8 *)&D_8011F750;
s32 idx;
__asm__ __volatile__("" : "=r"(p) : "0"(p)); /* materialize &D_8011F750 into $a0 (defeat %lo-fold of the lbu) */ // !FAKE: launder — NEEDED DIFFERS (P36 rung B tus2)
idx = *p;
if (idx != 0) {
idx = idx - 1;
D_80193484[idx]();
D_80193484[idx](p);
}
}
src/ov_SC02_005/ov_SC02_005_jr_80178D40.c
+2 -2
View File
@@ -3507,10 +3507,10 @@ int func_8017A3D8(void)
return 0;
case 100:
{
register int a __asm__("$4"); // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus8)
int a;
a = D_801E4260;
if (a != -1) {
return func_8001AAA0() != 0;
return ((int (*)(int))func_8001AAA0)(a) != 0;
}
return func_800D0CE0() == 1;
}
src/ov_SC02_011/ov_SC02_011_jr_8012ACE0.c
+15 -13
View File
@@ -2658,19 +2658,18 @@ s32 func_801345F8(s32 arg)
extern u16 * D_801912C0;
extern u16 D_801E9EF0;
register u16 *param_1 __asm__("$5") = ((u16 *)arg); // !FAKE: pin $5 — NEEDED DIFFERS (P36 rung B tus2)
register u16 *cc __asm__("$4") = D_801912C0; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
int c8000 = 0x8000;
register int zr __asm__("$0"); // !FAKE: pin $0 — NEEDED DIFFERS (P36 rung B tus2)
u32 c1, c2, uVar6, uVar2, cnt, v14;
u16 *ptmp, *puVar4, *puVar7, uVar1;
int hi, harg, iVar9, iVar8, uVar3, uVar10, tbl;
u16 *cc = D_801912C0;
u16 *param_1 = ((u16 *)arg);
u32 c1, c2, cnt, v14;
u16 uVar6, uVar2, rem;
u16 *ptmp, *puVar4, *puVar7, uVar1, harg;
int hi, iVar9, iVar8, uVar3, uVar10, tbl;
c1 = ((int)(cc[0] + c8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1 + zr;
c1 = ((int)(cc[0] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1;
if ((c1 & 0xffff) < (u32)param_1[2]) {
c2 = ((int)(cc[2] + c8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2 + zr;
c2 = ((int)(cc[2] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2;
if ((c2 & 0xffff) < (u32)param_1[3])
goto do_mult;
return 0;
@@ -2687,10 +2686,13 @@ s32 func_801345F8(s32 arg)
cnt = (u32)ptmp[1];
v14 = *(int *)(param_1 + 10);
puVar4 = (u16 *)(v14 + (u32)*ptmp + cnt * 2) - 1;
while (((cnt-- + zr) & 0xffff) != 0) {
for (;;) {
rem = cnt--;
if (rem == 0)
break;
uVar1 = *puVar4;
hi = uVar1 & 0x8000;
harg = hi + zr;
harg = hi;
if (hi == 0)
puVar7 = (u16 *)(iVar9 + (u32)uVar1 * 0x12);
else
src/ov_SC02_011/ov_SC02_011_jr_80140608.c
+3 -5
View File
@@ -1350,15 +1350,13 @@ extern unsigned short D_80115112;
void func_80141874(void) {
extern u16 D_8011511C;
extern u16 D_8011511C[];
extern u16 D_80115116;
extern void (*D_80192130[])(void);
register void (*fp)(void) __asm__("$2"); /* pin fn-ptr to $v0 → store retires early */ // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B tus2)
func_801754A8();
D_8011511E = func_80014ED4(0);
D_8011511C = func_80015018(0);
fp = D_80192130[D_80115112];
fp();
D_8011511C[0] = func_80015018(0);
D_80192130[D_80115112]();
func_80141C04();
D_80115116 += 1;
}
src/ov_SC02_011/ov_SC02_011_jr_8015C32C.c
+4 -5
View File
@@ -3933,16 +3933,15 @@ void func_80162760(void)
void func_801627E8(void)
{
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_801938D4[])(void); /* word-stride table of dispatch fn pointers */
register u8 *p __asm__("$4") = (u8 *)&D_8011F750; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_801938D4[])(u8 *); /* word-stride table of dispatch fn pointers; each takes the ctl block */
u8 *p = (u8 *)&D_8011F750;
s32 idx;
__asm__ __volatile__("" : "=r"(p) : "0"(p)); /* materialize &D_8011F750 into $a0 (defeat %lo-fold of the lbu) */ // !FAKE: launder — NEEDED DIFFERS (P36 rung B tus2)
idx = *p;
if (idx != 0) {
idx = idx - 1;
D_801938D4[idx]();
D_801938D4[idx](p);
}
}
src/ov_SC02_015/ov_SC02_015_jr_8012ACE0.c
+15 -13
View File
@@ -2658,19 +2658,18 @@ s32 func_801345F8(s32 arg)
extern u16 * D_8017E7D4;
extern u16 D_8018F070;
register u16 *param_1 __asm__("$5") = ((u16 *)arg); // !FAKE: pin $5 — NEEDED DIFFERS (P36 rung B tus2)
register u16 *cc __asm__("$4") = D_8017E7D4; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
int c8000 = 0x8000;
register int zr __asm__("$0"); // !FAKE: pin $0 — NEEDED DIFFERS (P36 rung B tus2)
u32 c1, c2, uVar6, uVar2, cnt, v14;
u16 *ptmp, *puVar4, *puVar7, uVar1;
int hi, harg, iVar9, iVar8, uVar3, uVar10, tbl;
u16 *cc = D_8017E7D4;
u16 *param_1 = ((u16 *)arg);
u32 c1, c2, cnt, v14;
u16 uVar6, uVar2, rem;
u16 *ptmp, *puVar4, *puVar7, uVar1, harg;
int hi, iVar9, iVar8, uVar3, uVar10, tbl;
c1 = ((int)(cc[0] + c8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1 + zr;
c1 = ((int)(cc[0] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1;
if ((c1 & 0xffff) < (u32)param_1[2]) {
c2 = ((int)(cc[2] + c8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2 + zr;
c2 = ((int)(cc[2] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2;
if ((c2 & 0xffff) < (u32)param_1[3])
goto do_mult;
return 0;
@@ -2687,10 +2686,13 @@ s32 func_801345F8(s32 arg)
cnt = (u32)ptmp[1];
v14 = *(int *)(param_1 + 10);
puVar4 = (u16 *)(v14 + (u32)*ptmp + cnt * 2) - 1;
while (((cnt-- + zr) & 0xffff) != 0) {
for (;;) {
rem = cnt--;
if (rem == 0)
break;
uVar1 = *puVar4;
hi = uVar1 & 0x8000;
harg = hi + zr;
harg = hi;
if (hi == 0)
puVar7 = (u16 *)(iVar9 + (u32)uVar1 * 0x12);
else
src/ov_SC02_015/ov_SC02_015_jr_80140608.c
+3 -5
View File
@@ -1350,15 +1350,13 @@ extern unsigned short D_80115112;
void func_80141874(void) {
extern u16 D_8011511C;
extern u16 D_8011511C[];
extern u16 D_80115116;
extern void (*D_8017F644[])(void);
register void (*fp)(void) __asm__("$2"); /* pin fn-ptr to $v0 → store retires early */ // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B tus2)
func_801754A8();
D_8011511E = func_80014ED4(0);
D_8011511C = func_80015018(0);
fp = D_8017F644[D_80115112];
fp();
D_8011511C[0] = func_80015018(0);
D_8017F644[D_80115112]();
func_80141C04();
D_80115116 += 1;
}
src/ov_SC02_015/ov_SC02_015_jr_8015C32C.c
+4 -5
View File
@@ -3931,16 +3931,15 @@ void func_80162760(void)
void func_801627E8(void)
{
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_80180DE8[])(void); /* word-stride table of dispatch fn pointers */
register u8 *p __asm__("$4") = (u8 *)&D_8011F750; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_80180DE8[])(u8 *); /* word-stride table of dispatch fn pointers; each takes the ctl block */
u8 *p = (u8 *)&D_8011F750;
s32 idx;
__asm__ __volatile__("" : "=r"(p) : "0"(p)); /* materialize &D_8011F750 into $a0 (defeat %lo-fold of the lbu) */ // !FAKE: launder — NEEDED DIFFERS (P36 rung B tus2)
idx = *p;
if (idx != 0) {
idx = idx - 1;
D_80180DE8[idx]();
D_80180DE8[idx](p);
}
}
src/ov_SC02_015/ov_SC02_015_jr_80178D40.c
+2 -2
View File
@@ -3503,10 +3503,10 @@ int func_8017A3D8(void)
return 0;
case 100:
{
register int a __asm__("$4"); // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus8)
int a;
a = D_801902C0;
if (a != -1) {
return func_8001AAA0() != 0;
return ((int (*)(int))func_8001AAA0)(a) != 0;
}
return func_800D0CE0() == 1;
}
src/ov_SC02_016/ov_SC02_016_jr_8012ACE0.c
+15 -13
View File
@@ -2658,19 +2658,18 @@ s32 func_801345F8(s32 arg)
extern u16 * D_80184A0C;
extern u16 D_801B2C88;
register u16 *param_1 __asm__("$5") = ((u16 *)arg); // !FAKE: pin $5 — NEEDED DIFFERS (P36 rung B tus2)
register u16 *cc __asm__("$4") = D_80184A0C; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
int c8000 = 0x8000;
register int zr __asm__("$0"); // !FAKE: pin $0 — NEEDED DIFFERS (P36 rung B tus2)
u32 c1, c2, uVar6, uVar2, cnt, v14;
u16 *ptmp, *puVar4, *puVar7, uVar1;
int hi, harg, iVar9, iVar8, uVar3, uVar10, tbl;
u16 *cc = D_80184A0C;
u16 *param_1 = ((u16 *)arg);
u32 c1, c2, cnt, v14;
u16 uVar6, uVar2, rem;
u16 *ptmp, *puVar4, *puVar7, uVar1, harg;
int hi, iVar9, iVar8, uVar3, uVar10, tbl;
c1 = ((int)(cc[0] + c8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1 + zr;
c1 = ((int)(cc[0] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1;
if ((c1 & 0xffff) < (u32)param_1[2]) {
c2 = ((int)(cc[2] + c8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2 + zr;
c2 = ((int)(cc[2] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2;
if ((c2 & 0xffff) < (u32)param_1[3])
goto do_mult;
return 0;
@@ -2687,10 +2686,13 @@ s32 func_801345F8(s32 arg)
cnt = (u32)ptmp[1];
v14 = *(int *)(param_1 + 10);
puVar4 = (u16 *)(v14 + (u32)*ptmp + cnt * 2) - 1;
while (((cnt-- + zr) & 0xffff) != 0) {
for (;;) {
rem = cnt--;
if (rem == 0)
break;
uVar1 = *puVar4;
hi = uVar1 & 0x8000;
harg = hi + zr;
harg = hi;
if (hi == 0)
puVar7 = (u16 *)(iVar9 + (u32)uVar1 * 0x12);
else
src/ov_SC02_016/ov_SC02_016_jr_80140608.c
+3 -5
View File
@@ -1350,15 +1350,13 @@ extern unsigned short D_80115112;
void func_80141874(void) {
extern u16 D_8011511C;
extern u16 D_8011511C[];
extern u16 D_80115116;
extern void (*D_8018587C[])(void);
register void (*fp)(void) __asm__("$2"); /* pin fn-ptr to $v0 → store retires early */ // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B tus2)
func_801754A8();
D_8011511E = func_80014ED4(0);
D_8011511C = func_80015018(0);
fp = D_8018587C[D_80115112];
fp();
D_8011511C[0] = func_80015018(0);
D_8018587C[D_80115112]();
func_80141C04();
D_80115116 += 1;
}
src/ov_SC02_016/ov_SC02_016_jr_8015C32C.c
+4 -5
View File
@@ -3933,16 +3933,15 @@ void func_80162760(void)
void func_801627E8(void)
{
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_80187020[])(void); /* word-stride table of dispatch fn pointers */
register u8 *p __asm__("$4") = (u8 *)&D_8011F750; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_80187020[])(u8 *); /* word-stride table of dispatch fn pointers; each takes the ctl block */
u8 *p = (u8 *)&D_8011F750;
s32 idx;
__asm__ __volatile__("" : "=r"(p) : "0"(p)); /* materialize &D_8011F750 into $a0 (defeat %lo-fold of the lbu) */ // !FAKE: launder — NEEDED DIFFERS (P36 rung B tus2)
idx = *p;
if (idx != 0) {
idx = idx - 1;
D_80187020[idx]();
D_80187020[idx](p);
}
}
src/ov_SC02_016/ov_SC02_016_jr_80178D40.c
+2 -2
View File
@@ -3505,10 +3505,10 @@ int func_8017A3D8(void)
return 0;
case 100:
{
register int a __asm__("$4"); // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus8)
int a;
a = D_801B3ED8;
if (a != -1) {
return func_8001AAA0() != 0;
return ((int (*)(int))func_8001AAA0)(a) != 0;
}
return func_800D0CE0() == 1;
}
src/ov_SC02_017/ov_SC02_017_jr_8012ACE0.c
+15 -13
View File
@@ -2658,19 +2658,18 @@ s32 func_801345F8(s32 arg)
extern u16 * D_8018AA64;
extern u16 D_801EE4B0;
register u16 *param_1 __asm__("$5") = ((u16 *)arg); // !FAKE: pin $5 — NEEDED DIFFERS (P36 rung B tus2)
register u16 *cc __asm__("$4") = D_8018AA64; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
int c8000 = 0x8000;
register int zr __asm__("$0"); // !FAKE: pin $0 — NEEDED DIFFERS (P36 rung B tus2)
u32 c1, c2, uVar6, uVar2, cnt, v14;
u16 *ptmp, *puVar4, *puVar7, uVar1;
int hi, harg, iVar9, iVar8, uVar3, uVar10, tbl;
u16 *cc = D_8018AA64;
u16 *param_1 = ((u16 *)arg);
u32 c1, c2, cnt, v14;
u16 uVar6, uVar2, rem;
u16 *ptmp, *puVar4, *puVar7, uVar1, harg;
int hi, iVar9, iVar8, uVar3, uVar10, tbl;
c1 = ((int)(cc[0] + c8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1 + zr;
c1 = ((int)(cc[0] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1;
if ((c1 & 0xffff) < (u32)param_1[2]) {
c2 = ((int)(cc[2] + c8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2 + zr;
c2 = ((int)(cc[2] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2;
if ((c2 & 0xffff) < (u32)param_1[3])
goto do_mult;
return 0;
@@ -2687,10 +2686,13 @@ s32 func_801345F8(s32 arg)
cnt = (u32)ptmp[1];
v14 = *(int *)(param_1 + 10);
puVar4 = (u16 *)(v14 + (u32)*ptmp + cnt * 2) - 1;
while (((cnt-- + zr) & 0xffff) != 0) {
for (;;) {
rem = cnt--;
if (rem == 0)
break;
uVar1 = *puVar4;
hi = uVar1 & 0x8000;
harg = hi + zr;
harg = hi;
if (hi == 0)
puVar7 = (u16 *)(iVar9 + (u32)uVar1 * 0x12);
else
src/ov_SC02_017/ov_SC02_017_jr_80140608.c
+3 -5
View File
@@ -1350,15 +1350,13 @@ extern unsigned short D_80115112;
void func_80141874(void) {
extern u16 D_8011511C;
extern u16 D_8011511C[];
extern u16 D_80115116;
extern void (*D_8018B8D4[])(void);
register void (*fp)(void) __asm__("$2"); /* pin fn-ptr to $v0 → store retires early */ // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B tus2)
func_801754A8();
D_8011511E = func_80014ED4(0);
D_8011511C = func_80015018(0);
fp = D_8018B8D4[D_80115112];
fp();
D_8011511C[0] = func_80015018(0);
D_8018B8D4[D_80115112]();
func_80141C04();
D_80115116 += 1;
}
src/ov_SC02_017/ov_SC02_017_jr_8015C32C.c
+4 -5
View File
@@ -3933,16 +3933,15 @@ void func_80162760(void)
void func_801627E8(void)
{
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_8018D078[])(void); /* word-stride table of dispatch fn pointers */
register u8 *p __asm__("$4") = (u8 *)&D_8011F750; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_8018D078[])(u8 *); /* word-stride table of dispatch fn pointers; each takes the ctl block */
u8 *p = (u8 *)&D_8011F750;
s32 idx;
__asm__ __volatile__("" : "=r"(p) : "0"(p)); /* materialize &D_8011F750 into $a0 (defeat %lo-fold of the lbu) */ // !FAKE: launder — NEEDED DIFFERS (P36 rung B tus2)
idx = *p;
if (idx != 0) {
idx = idx - 1;
D_8018D078[idx]();
D_8018D078[idx](p);
}
}
src/ov_SC02_021/ov_SC02_021_jr_8012ACE0.c
+15 -13
View File
@@ -2658,19 +2658,18 @@ s32 func_801345F8(s32 arg)
extern u16 * D_80180058;
extern u16 D_80191A20;
register u16 *param_1 __asm__("$5") = ((u16 *)arg); // !FAKE: pin $5 — NEEDED DIFFERS (P36 rung B tus2)
register u16 *cc __asm__("$4") = D_80180058; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
int c8000 = 0x8000;
register int zr __asm__("$0"); // !FAKE: pin $0 — NEEDED DIFFERS (P36 rung B tus2)
u32 c1, c2, uVar6, uVar2, cnt, v14;
u16 *ptmp, *puVar4, *puVar7, uVar1;
int hi, harg, iVar9, iVar8, uVar3, uVar10, tbl;
u16 *cc = D_80180058;
u16 *param_1 = ((u16 *)arg);
u32 c1, c2, cnt, v14;
u16 uVar6, uVar2, rem;
u16 *ptmp, *puVar4, *puVar7, uVar1, harg;
int hi, iVar9, iVar8, uVar3, uVar10, tbl;
c1 = ((int)(cc[0] + c8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1 + zr;
c1 = ((int)(cc[0] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1;
if ((c1 & 0xffff) < (u32)param_1[2]) {
c2 = ((int)(cc[2] + c8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2 + zr;
c2 = ((int)(cc[2] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2;
if ((c2 & 0xffff) < (u32)param_1[3])
goto do_mult;
return 0;
@@ -2687,10 +2686,13 @@ s32 func_801345F8(s32 arg)
cnt = (u32)ptmp[1];
v14 = *(int *)(param_1 + 10);
puVar4 = (u16 *)(v14 + (u32)*ptmp + cnt * 2) - 1;
while (((cnt-- + zr) & 0xffff) != 0) {
for (;;) {
rem = cnt--;
if (rem == 0)
break;
uVar1 = *puVar4;
hi = uVar1 & 0x8000;
harg = hi + zr;
harg = hi;
if (hi == 0)
puVar7 = (u16 *)(iVar9 + (u32)uVar1 * 0x12);
else
src/ov_SC02_021/ov_SC02_021_jr_80140608.c
+3 -5
View File
@@ -1350,15 +1350,13 @@ extern unsigned short D_80115112;
void func_80141874(void) {
extern u16 D_8011511C;
extern u16 D_8011511C[];
extern u16 D_80115116;
extern void (*D_80180EC8[])(void);
register void (*fp)(void) __asm__("$2"); /* pin fn-ptr to $v0 → store retires early */ // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B tus2)
func_801754A8();
D_8011511E = func_80014ED4(0);
D_8011511C = func_80015018(0);
fp = D_80180EC8[D_80115112];
fp();
D_8011511C[0] = func_80015018(0);
D_80180EC8[D_80115112]();
func_80141C04();
D_80115116 += 1;
}
src/ov_SC02_021/ov_SC02_021_jr_8015C32C.c
+4 -5
View File
@@ -3933,16 +3933,15 @@ void func_80162760(void)
void func_801627E8(void)
{
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_8018266C[])(void); /* word-stride table of dispatch fn pointers */
register u8 *p __asm__("$4") = (u8 *)&D_8011F750; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_8018266C[])(u8 *); /* word-stride table of dispatch fn pointers; each takes the ctl block */
u8 *p = (u8 *)&D_8011F750;
s32 idx;
__asm__ __volatile__("" : "=r"(p) : "0"(p)); /* materialize &D_8011F750 into $a0 (defeat %lo-fold of the lbu) */ // !FAKE: launder — NEEDED DIFFERS (P36 rung B tus2)
idx = *p;
if (idx != 0) {
idx = idx - 1;
D_8018266C[idx]();
D_8018266C[idx](p);
}
}
src/ov_SC02_021/ov_SC02_021_jr_80178D40.c
+2 -2
View File
@@ -3505,10 +3505,10 @@ int func_8017A3D8(void)
return 0;
case 100:
{
register int a __asm__("$4"); // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus8)
int a;
a = D_80192C70;
if (a != -1) {
return func_8001AAA0() != 0;
return ((int (*)(int))func_8001AAA0)(a) != 0;
}
return func_800D0CE0() == 1;
}
src/ov_SC02_026/ov_SC02_026_jr_8012ACE0.c
+15 -13
View File
@@ -2658,19 +2658,18 @@ s32 func_801345F8(s32 arg)
extern u16 * D_801866AC;
extern u16 D_801CEE60;
register u16 *param_1 __asm__("$5") = ((u16 *)arg); // !FAKE: pin $5 — NEEDED DIFFERS (P36 rung B tus2)
register u16 *cc __asm__("$4") = D_801866AC; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
int c8000 = 0x8000;
register int zr __asm__("$0"); // !FAKE: pin $0 — NEEDED DIFFERS (P36 rung B tus2)
u32 c1, c2, uVar6, uVar2, cnt, v14;
u16 *ptmp, *puVar4, *puVar7, uVar1;
int hi, harg, iVar9, iVar8, uVar3, uVar10, tbl;
u16 *cc = D_801866AC;
u16 *param_1 = ((u16 *)arg);
u32 c1, c2, cnt, v14;
u16 uVar6, uVar2, rem;
u16 *ptmp, *puVar4, *puVar7, uVar1, harg;
int hi, iVar9, iVar8, uVar3, uVar10, tbl;
c1 = ((int)(cc[0] + c8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1 + zr;
c1 = ((int)(cc[0] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1;
if ((c1 & 0xffff) < (u32)param_1[2]) {
c2 = ((int)(cc[2] + c8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2 + zr;
c2 = ((int)(cc[2] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2;
if ((c2 & 0xffff) < (u32)param_1[3])
goto do_mult;
return 0;
@@ -2687,10 +2686,13 @@ s32 func_801345F8(s32 arg)
cnt = (u32)ptmp[1];
v14 = *(int *)(param_1 + 10);
puVar4 = (u16 *)(v14 + (u32)*ptmp + cnt * 2) - 1;
while (((cnt-- + zr) & 0xffff) != 0) {
for (;;) {
rem = cnt--;
if (rem == 0)
break;
uVar1 = *puVar4;
hi = uVar1 & 0x8000;
harg = hi + zr;
harg = hi;
if (hi == 0)
puVar7 = (u16 *)(iVar9 + (u32)uVar1 * 0x12);
else
src/ov_SC02_026/ov_SC02_026_jr_80140608.c
+3 -5
View File
@@ -1350,15 +1350,13 @@ extern unsigned short D_80115112;
void func_80141874(void) {
extern u16 D_8011511C;
extern u16 D_8011511C[];
extern u16 D_80115116;
extern void (*D_8018751C[])(void);
register void (*fp)(void) __asm__("$2"); /* pin fn-ptr to $v0 → store retires early */ // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B tus2)
func_801754A8();
D_8011511E = func_80014ED4(0);
D_8011511C = func_80015018(0);
fp = D_8018751C[D_80115112];
fp();
D_8011511C[0] = func_80015018(0);
D_8018751C[D_80115112]();
func_80141C04();
D_80115116 += 1;
}
src/ov_SC02_026/ov_SC02_026_jr_8015C32C.c
+4 -5
View File
@@ -3933,16 +3933,15 @@ void func_80162760(void)
void func_801627E8(void)
{
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_80188CC0[])(void); /* word-stride table of dispatch fn pointers */
register u8 *p __asm__("$4") = (u8 *)&D_8011F750; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_80188CC0[])(u8 *); /* word-stride table of dispatch fn pointers; each takes the ctl block */
u8 *p = (u8 *)&D_8011F750;
s32 idx;
__asm__ __volatile__("" : "=r"(p) : "0"(p)); /* materialize &D_8011F750 into $a0 (defeat %lo-fold of the lbu) */ // !FAKE: launder — NEEDED DIFFERS (P36 rung B tus2)
idx = *p;
if (idx != 0) {
idx = idx - 1;
D_80188CC0[idx]();
D_80188CC0[idx](p);
}
}
src/ov_SC02_026/ov_SC02_026_jr_80178D40.c
+2 -2
View File
@@ -3505,10 +3505,10 @@ int func_8017A3D8(void)
return 0;
case 100:
{
register int a __asm__("$4"); // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus8)
int a;
a = D_801D00B0;
if (a != -1) {
return func_8001AAA0() != 0;
return ((int (*)(int))func_8001AAA0)(a) != 0;
}
return func_800D0CE0() == 1;
}
src/ov_SC02_027/ov_SC02_027_jr_8012ACE0.c
+15 -13
View File
@@ -2658,19 +2658,18 @@ s32 func_801345F8(s32 arg)
extern u16 * D_8018B7D0;
extern u16 D_801D8BD0;
register u16 *param_1 __asm__("$5") = ((u16 *)arg); // !FAKE: pin $5 — NEEDED DIFFERS (P36 rung B tus2)
register u16 *cc __asm__("$4") = D_8018B7D0; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
int c8000 = 0x8000;
register int zr __asm__("$0"); // !FAKE: pin $0 — NEEDED DIFFERS (P36 rung B tus2)
u32 c1, c2, uVar6, uVar2, cnt, v14;
u16 *ptmp, *puVar4, *puVar7, uVar1;
int hi, harg, iVar9, iVar8, uVar3, uVar10, tbl;
u16 *cc = D_8018B7D0;
u16 *param_1 = ((u16 *)arg);
u32 c1, c2, cnt, v14;
u16 uVar6, uVar2, rem;
u16 *ptmp, *puVar4, *puVar7, uVar1, harg;
int hi, iVar9, iVar8, uVar3, uVar10, tbl;
c1 = ((int)(cc[0] + c8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1 + zr;
c1 = ((int)(cc[0] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1;
if ((c1 & 0xffff) < (u32)param_1[2]) {
c2 = ((int)(cc[2] + c8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2 + zr;
c2 = ((int)(cc[2] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2;
if ((c2 & 0xffff) < (u32)param_1[3])
goto do_mult;
return 0;
@@ -2687,10 +2686,13 @@ s32 func_801345F8(s32 arg)
cnt = (u32)ptmp[1];
v14 = *(int *)(param_1 + 10);
puVar4 = (u16 *)(v14 + (u32)*ptmp + cnt * 2) - 1;
while (((cnt-- + zr) & 0xffff) != 0) {
for (;;) {
rem = cnt--;
if (rem == 0)
break;
uVar1 = *puVar4;
hi = uVar1 & 0x8000;
harg = hi + zr;
harg = hi;
if (hi == 0)
puVar7 = (u16 *)(iVar9 + (u32)uVar1 * 0x12);
else
src/ov_SC02_027/ov_SC02_027_jr_80140608.c
+3 -5
View File
@@ -1350,15 +1350,13 @@ extern unsigned short D_80115112;
void func_80141874(void) {
extern u16 D_8011511C;
extern u16 D_8011511C[];
extern u16 D_80115116;
extern void (*D_8018C640[])(void);
register void (*fp)(void) __asm__("$2"); /* pin fn-ptr to $v0 → store retires early */ // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B tus2)
func_801754A8();
D_8011511E = func_80014ED4(0);
D_8011511C = func_80015018(0);
fp = D_8018C640[D_80115112];
fp();
D_8011511C[0] = func_80015018(0);
D_8018C640[D_80115112]();
func_80141C04();
D_80115116 += 1;
}
src/ov_SC02_027/ov_SC02_027_jr_8015C32C.c
+4 -5
View File
@@ -3933,16 +3933,15 @@ void func_80162760(void)
void func_801627E8(void)
{
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_8018DDE4[])(void); /* word-stride table of dispatch fn pointers */
register u8 *p __asm__("$4") = (u8 *)&D_8011F750; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_8018DDE4[])(u8 *); /* word-stride table of dispatch fn pointers; each takes the ctl block */
u8 *p = (u8 *)&D_8011F750;
s32 idx;
__asm__ __volatile__("" : "=r"(p) : "0"(p)); /* materialize &D_8011F750 into $a0 (defeat %lo-fold of the lbu) */ // !FAKE: launder — NEEDED DIFFERS (P36 rung B tus2)
idx = *p;
if (idx != 0) {
idx = idx - 1;
D_8018DDE4[idx]();
D_8018DDE4[idx](p);
}
}
src/ov_SC02_027/ov_SC02_027_jr_80178D40.c
+2 -2
View File
@@ -3505,10 +3505,10 @@ int func_8017A3D8(void)
return 0;
case 100:
{
register int a __asm__("$4"); // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus8)
int a;
a = D_801D9E20;
if (a != -1) {
return func_8001AAA0() != 0;
return ((int (*)(int))func_8001AAA0)(a) != 0;
}
return func_800D0CE0() == 1;
}
src/ov_SC02_028/ov_SC02_028_jr_8012ACE0.c
+15 -13
View File
@@ -2658,19 +2658,18 @@ s32 func_801345F8(s32 arg)
extern u16 * D_8018B9D4;
extern u16 D_801D1B70;
register u16 *param_1 __asm__("$5") = ((u16 *)arg); // !FAKE: pin $5 — NEEDED DIFFERS (P36 rung B tus2)
register u16 *cc __asm__("$4") = D_8018B9D4; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
int c8000 = 0x8000;
register int zr __asm__("$0"); // !FAKE: pin $0 — NEEDED DIFFERS (P36 rung B tus2)
u32 c1, c2, uVar6, uVar2, cnt, v14;
u16 *ptmp, *puVar4, *puVar7, uVar1;
int hi, harg, iVar9, iVar8, uVar3, uVar10, tbl;
u16 *cc = D_8018B9D4;
u16 *param_1 = ((u16 *)arg);
u32 c1, c2, cnt, v14;
u16 uVar6, uVar2, rem;
u16 *ptmp, *puVar4, *puVar7, uVar1, harg;
int hi, iVar9, iVar8, uVar3, uVar10, tbl;
c1 = ((int)(cc[0] + c8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1 + zr;
c1 = ((int)(cc[0] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1;
if ((c1 & 0xffff) < (u32)param_1[2]) {
c2 = ((int)(cc[2] + c8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2 + zr;
c2 = ((int)(cc[2] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2;
if ((c2 & 0xffff) < (u32)param_1[3])
goto do_mult;
return 0;
@@ -2687,10 +2686,13 @@ s32 func_801345F8(s32 arg)
cnt = (u32)ptmp[1];
v14 = *(int *)(param_1 + 10);
puVar4 = (u16 *)(v14 + (u32)*ptmp + cnt * 2) - 1;
while (((cnt-- + zr) & 0xffff) != 0) {
for (;;) {
rem = cnt--;
if (rem == 0)
break;
uVar1 = *puVar4;
hi = uVar1 & 0x8000;
harg = hi + zr;
harg = hi;
if (hi == 0)
puVar7 = (u16 *)(iVar9 + (u32)uVar1 * 0x12);
else
src/ov_SC02_028/ov_SC02_028_jr_80140608.c
+3 -5
View File
@@ -1350,15 +1350,13 @@ extern unsigned short D_80115112;
void func_80141874(void) {
extern u16 D_8011511C;
extern u16 D_8011511C[];
extern u16 D_80115116;
extern void (*D_8018C844[])(void);
register void (*fp)(void) __asm__("$2"); /* pin fn-ptr to $v0 → store retires early */ // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B tus2)
func_801754A8();
D_8011511E = func_80014ED4(0);
D_8011511C = func_80015018(0);
fp = D_8018C844[D_80115112];
fp();
D_8011511C[0] = func_80015018(0);
D_8018C844[D_80115112]();
func_80141C04();
D_80115116 += 1;
}
src/ov_SC02_028/ov_SC02_028_jr_8015C32C.c
+4 -5
View File
@@ -3933,16 +3933,15 @@ void func_80162760(void)
void func_801627E8(void)
{
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_8018DFE8[])(void); /* word-stride table of dispatch fn pointers */
register u8 *p __asm__("$4") = (u8 *)&D_8011F750; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_8018DFE8[])(u8 *); /* word-stride table of dispatch fn pointers; each takes the ctl block */
u8 *p = (u8 *)&D_8011F750;
s32 idx;
__asm__ __volatile__("" : "=r"(p) : "0"(p)); /* materialize &D_8011F750 into $a0 (defeat %lo-fold of the lbu) */ // !FAKE: launder — NEEDED DIFFERS (P36 rung B tus2)
idx = *p;
if (idx != 0) {
idx = idx - 1;
D_8018DFE8[idx]();
D_8018DFE8[idx](p);
}
}
src/ov_SC02_028/ov_SC02_028_jr_80178D40.c
+2 -2
View File
@@ -3505,10 +3505,10 @@ int func_8017A3D8(void)
return 0;
case 100:
{
register int a __asm__("$4"); // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus8)
int a;
a = D_801D2DC0;
if (a != -1) {
return func_8001AAA0() != 0;
return ((int (*)(int))func_8001AAA0)(a) != 0;
}
return func_800D0CE0() == 1;
}
src/ov_SC02_031/ov_SC02_031_jr_8012ACE0.c
+15 -13
View File
@@ -2658,19 +2658,18 @@ s32 func_801345F8(s32 arg)
extern u16 * D_80185200;
extern u16 D_801B62E8;
register u16 *param_1 __asm__("$5") = ((u16 *)arg); // !FAKE: pin $5 — NEEDED DIFFERS (P36 rung B tus2)
register u16 *cc __asm__("$4") = D_80185200; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
int c8000 = 0x8000;
register int zr __asm__("$0"); // !FAKE: pin $0 — NEEDED DIFFERS (P36 rung B tus2)
u32 c1, c2, uVar6, uVar2, cnt, v14;
u16 *ptmp, *puVar4, *puVar7, uVar1;
int hi, harg, iVar9, iVar8, uVar3, uVar10, tbl;
u16 *cc = D_80185200;
u16 *param_1 = ((u16 *)arg);
u32 c1, c2, cnt, v14;
u16 uVar6, uVar2, rem;
u16 *ptmp, *puVar4, *puVar7, uVar1, harg;
int hi, iVar9, iVar8, uVar3, uVar10, tbl;
c1 = ((int)(cc[0] + c8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1 + zr;
c1 = ((int)(cc[0] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1;
if ((c1 & 0xffff) < (u32)param_1[2]) {
c2 = ((int)(cc[2] + c8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2 + zr;
c2 = ((int)(cc[2] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2;
if ((c2 & 0xffff) < (u32)param_1[3])
goto do_mult;
return 0;
@@ -2687,10 +2686,13 @@ s32 func_801345F8(s32 arg)
cnt = (u32)ptmp[1];
v14 = *(int *)(param_1 + 10);
puVar4 = (u16 *)(v14 + (u32)*ptmp + cnt * 2) - 1;
while (((cnt-- + zr) & 0xffff) != 0) {
for (;;) {
rem = cnt--;
if (rem == 0)
break;
uVar1 = *puVar4;
hi = uVar1 & 0x8000;
harg = hi + zr;
harg = hi;
if (hi == 0)
puVar7 = (u16 *)(iVar9 + (u32)uVar1 * 0x12);
else
src/ov_SC02_031/ov_SC02_031_jr_80140608.c
+3 -5
View File
@@ -1350,15 +1350,13 @@ extern unsigned short D_80115112;
void func_80141874(void) {
extern u16 D_8011511C;
extern u16 D_8011511C[];
extern u16 D_80115116;
extern void (*D_80186070[])(void);
register void (*fp)(void) __asm__("$2"); /* pin fn-ptr to $v0 → store retires early */ // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B tus2)
func_801754A8();
D_8011511E = func_80014ED4(0);
D_8011511C = func_80015018(0);
fp = D_80186070[D_80115112];
fp();
D_8011511C[0] = func_80015018(0);
D_80186070[D_80115112]();
func_80141C04();
D_80115116 += 1;
}
src/ov_SC02_031/ov_SC02_031_jr_8015C32C.c
+4 -5
View File
@@ -3933,16 +3933,15 @@ void func_80162760(void)
void func_801627E8(void)
{
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_80187814[])(void); /* word-stride table of dispatch fn pointers */
register u8 *p __asm__("$4") = (u8 *)&D_8011F750; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_80187814[])(u8 *); /* word-stride table of dispatch fn pointers; each takes the ctl block */
u8 *p = (u8 *)&D_8011F750;
s32 idx;
__asm__ __volatile__("" : "=r"(p) : "0"(p)); /* materialize &D_8011F750 into $a0 (defeat %lo-fold of the lbu) */ // !FAKE: launder — NEEDED DIFFERS (P36 rung B tus2)
idx = *p;
if (idx != 0) {
idx = idx - 1;
D_80187814[idx]();
D_80187814[idx](p);
}
}
src/ov_SC02_031/ov_SC02_031_jr_80178D40.c
+2 -2
View File
@@ -3505,10 +3505,10 @@ int func_8017A3D8(void)
return 0;
case 100:
{
register int a __asm__("$4"); // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus8)
int a;
a = D_801B7538;
if (a != -1) {
return func_8001AAA0() != 0;
return ((int (*)(int))func_8001AAA0)(a) != 0;
}
return func_800D0CE0() == 1;
}
src/ov_SC02_035/ov_SC02_035_jr_8012ACE0.c
+15 -13
View File
@@ -2658,19 +2658,18 @@ s32 func_801345F8(s32 arg)
extern u16 * D_80184A60;
extern u16 D_801BD618;
register u16 *param_1 __asm__("$5") = ((u16 *)arg); // !FAKE: pin $5 — NEEDED DIFFERS (P36 rung B tus2)
register u16 *cc __asm__("$4") = D_80184A60; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
int c8000 = 0x8000;
register int zr __asm__("$0"); // !FAKE: pin $0 — NEEDED DIFFERS (P36 rung B tus2)
u32 c1, c2, uVar6, uVar2, cnt, v14;
u16 *ptmp, *puVar4, *puVar7, uVar1;
int hi, harg, iVar9, iVar8, uVar3, uVar10, tbl;
u16 *cc = D_80184A60;
u16 *param_1 = ((u16 *)arg);
u32 c1, c2, cnt, v14;
u16 uVar6, uVar2, rem;
u16 *ptmp, *puVar4, *puVar7, uVar1, harg;
int hi, iVar9, iVar8, uVar3, uVar10, tbl;
c1 = ((int)(cc[0] + c8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1 + zr;
c1 = ((int)(cc[0] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1;
if ((c1 & 0xffff) < (u32)param_1[2]) {
c2 = ((int)(cc[2] + c8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2 + zr;
c2 = ((int)(cc[2] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2;
if ((c2 & 0xffff) < (u32)param_1[3])
goto do_mult;
return 0;
@@ -2687,10 +2686,13 @@ s32 func_801345F8(s32 arg)
cnt = (u32)ptmp[1];
v14 = *(int *)(param_1 + 10);
puVar4 = (u16 *)(v14 + (u32)*ptmp + cnt * 2) - 1;
while (((cnt-- + zr) & 0xffff) != 0) {
for (;;) {
rem = cnt--;
if (rem == 0)
break;
uVar1 = *puVar4;
hi = uVar1 & 0x8000;
harg = hi + zr;
harg = hi;
if (hi == 0)
puVar7 = (u16 *)(iVar9 + (u32)uVar1 * 0x12);
else
src/ov_SC02_035/ov_SC02_035_jr_80140608.c
+3 -5
View File
@@ -1350,15 +1350,13 @@ extern unsigned short D_80115112;
void func_80141874(void) {
extern u16 D_8011511C;
extern u16 D_8011511C[];
extern u16 D_80115116;
extern void (*D_801858D0[])(void);
register void (*fp)(void) __asm__("$2"); /* pin fn-ptr to $v0 → store retires early */ // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B tus2)
func_801754A8();
D_8011511E = func_80014ED4(0);
D_8011511C = func_80015018(0);
fp = D_801858D0[D_80115112];
fp();
D_8011511C[0] = func_80015018(0);
D_801858D0[D_80115112]();
func_80141C04();
D_80115116 += 1;
}
src/ov_SC02_035/ov_SC02_035_jr_8015C32C.c
+4 -5
View File
@@ -3933,16 +3933,15 @@ void func_80162760(void)
void func_801627E8(void)
{
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_80187074[])(void); /* word-stride table of dispatch fn pointers */
register u8 *p __asm__("$4") = (u8 *)&D_8011F750; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_80187074[])(u8 *); /* word-stride table of dispatch fn pointers; each takes the ctl block */
u8 *p = (u8 *)&D_8011F750;
s32 idx;
__asm__ __volatile__("" : "=r"(p) : "0"(p)); /* materialize &D_8011F750 into $a0 (defeat %lo-fold of the lbu) */ // !FAKE: launder — NEEDED DIFFERS (P36 rung B tus2)
idx = *p;
if (idx != 0) {
idx = idx - 1;
D_80187074[idx]();
D_80187074[idx](p);
}
}
src/ov_SC02_035/ov_SC02_035_jr_80178D40.c
+2 -2
View File
@@ -3505,10 +3505,10 @@ int func_8017A3D8(void)
return 0;
case 100:
{
register int a __asm__("$4"); // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus8)
int a;
a = D_801BE868;
if (a != -1) {
return func_8001AAA0() != 0;
return ((int (*)(int))func_8001AAA0)(a) != 0;
}
return func_800D0CE0() == 1;
}
src/ov_SC02_037/ov_SC02_037_jr_80131340.c
+15 -13
View File
@@ -1884,19 +1884,18 @@ s32 func_801345F8(s32 arg)
extern u16 * D_8018419C;
extern u16 D_801C8428;
register u16 *param_1 __asm__("$5") = ((u16 *)arg); // !FAKE: pin $5 — NEEDED DIFFERS (P36 rung B tus2)
register u16 *cc __asm__("$4") = D_8018419C; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
int c8000 = 0x8000;
register int zr __asm__("$0"); // !FAKE: pin $0 — NEEDED DIFFERS (P36 rung B tus2)
u32 c1, c2, uVar6, uVar2, cnt, v14;
u16 *ptmp, *puVar4, *puVar7, uVar1;
int hi, harg, iVar9, iVar8, uVar3, uVar10, tbl;
u16 *cc = D_8018419C;
u16 *param_1 = ((u16 *)arg);
u32 c1, c2, cnt, v14;
u16 uVar6, uVar2, rem;
u16 *ptmp, *puVar4, *puVar7, uVar1, harg;
int hi, iVar9, iVar8, uVar3, uVar10, tbl;
c1 = ((int)(cc[0] + c8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1 + zr;
c1 = ((int)(cc[0] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1;
if ((c1 & 0xffff) < (u32)param_1[2]) {
c2 = ((int)(cc[2] + c8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2 + zr;
c2 = ((int)(cc[2] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2;
if ((c2 & 0xffff) < (u32)param_1[3])
goto do_mult;
return 0;
@@ -1913,10 +1912,13 @@ s32 func_801345F8(s32 arg)
cnt = (u32)ptmp[1];
v14 = *(int *)(param_1 + 10);
puVar4 = (u16 *)(v14 + (u32)*ptmp + cnt * 2) - 1;
while (((cnt-- + zr) & 0xffff) != 0) {
for (;;) {
rem = cnt--;
if (rem == 0)
break;
uVar1 = *puVar4;
hi = uVar1 & 0x8000;
harg = hi + zr;
harg = hi;
if (hi == 0)
puVar7 = (u16 *)(iVar9 + (u32)uVar1 * 0x12);
else
src/ov_SC02_037/ov_SC02_037_jr_8015A3C8.c
+4 -5
View File
@@ -6172,16 +6172,15 @@ extern void func_801627C0(void);
void func_801627E8(void)
{
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_801867B0[])(void); /* word-stride table of dispatch fn pointers */
register u8 *p __asm__("$4") = (u8 *)&D_8011F750; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
extern s32 D_8011F750; /* canonical: engine_core.h `extern s32 D_8011F750;` (read here as a byte) */
extern void (*D_801867B0[])(u8 *); /* word-stride table of dispatch fn pointers; each takes the ctl block */
u8 *p = (u8 *)&D_8011F750;
s32 idx;
__asm__ __volatile__("" : "=r"(p) : "0"(p)); /* materialize &D_8011F750 into $a0 (defeat %lo-fold of the lbu) */ // !FAKE: launder — NEEDED DIFFERS (P36 rung B tus2)
idx = *p;
if (idx != 0) {
idx = idx - 1;
D_801867B0[idx]();
D_801867B0[idx](p);
}
}
src/ov_SC02_039/ov_SC02_039_jr_8012ACE0.c
+15 -13
View File
@@ -2659,19 +2659,18 @@ s32 func_801345F8(s32 arg)
extern u16 * D_8017F68C;
extern u16 D_8019F9C8;
register u16 *param_1 __asm__("$5") = ((u16 *)arg); // !FAKE: pin $5 — NEEDED DIFFERS (P36 rung B tus2)
register u16 *cc __asm__("$4") = D_8017F68C; // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus2)
int c8000 = 0x8000;
register int zr __asm__("$0"); // !FAKE: pin $0 — NEEDED DIFFERS (P36 rung B tus2)
u32 c1, c2, uVar6, uVar2, cnt, v14;
u16 *ptmp, *puVar4, *puVar7, uVar1;
int hi, harg, iVar9, iVar8, uVar3, uVar10, tbl;
u16 *cc = D_8017F68C;
u16 *param_1 = ((u16 *)arg);
u32 c1, c2, cnt, v14;
u16 uVar6, uVar2, rem;
u16 *ptmp, *puVar4, *puVar7, uVar1, harg;
int hi, iVar9, iVar8, uVar3, uVar10, tbl;
c1 = ((int)(cc[0] + c8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1 + zr;
c1 = ((int)(cc[0] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[0];
uVar6 = c1;
if ((c1 & 0xffff) < (u32)param_1[2]) {
c2 = ((int)(cc[2] + c8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2 + zr;
c2 = ((int)(cc[2] + 0x8000) >> 7 & 0x1ff) - (u32)param_1[1];
uVar2 = c2;
if ((c2 & 0xffff) < (u32)param_1[3])
goto do_mult;
return 0;
@@ -2688,10 +2687,13 @@ s32 func_801345F8(s32 arg)
cnt = (u32)ptmp[1];
v14 = *(int *)(param_1 + 10);
puVar4 = (u16 *)(v14 + (u32)*ptmp + cnt * 2) - 1;
while (((cnt-- + zr) & 0xffff) != 0) {
for (;;) {
rem = cnt--;
if (rem == 0)
break;
uVar1 = *puVar4;
hi = uVar1 & 0x8000;
harg = hi + zr;
harg = hi;
if (hi == 0)
puVar7 = (u16 *)(iVar9 + (u32)uVar1 * 0x12);
else
src/ov_SC02_039/ov_SC02_039_jr_80140608.c
+3 -5
View File
@@ -1347,15 +1347,13 @@ extern unsigned short D_80115112;
void func_80141874(void) {
extern u16 D_8011511C;
extern u16 D_8011511C[];
extern u16 D_80115116;
extern void (*D_801804FC[])(void);
register void (*fp)(void) __asm__("$2"); /* pin fn-ptr to $v0 → store retires early */ // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B tus2)
func_801754A8();
D_8011511E = func_80014ED4(0);
D_8011511C = func_80015018(0);
fp = D_801804FC[D_80115112];
fp();
D_8011511C[0] = func_80015018(0);
D_801804FC[D_80115112]();
func_80141C04();
D_80115116 += 1;
}

Some files were not shown because too many files have changed in this diff Show More