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feat(phase-30 S48-T6): propagate func_80185F58 to its zero-crack siblings

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This commit is contained in:
Drew T
2026-08-11 18:35:20 -06:00
parent 65204c205a
commit c824c19a3d
11 changed files with 874 additions and 26 deletions
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src/ov_SC06_020/ov_SC06_020_jr_8017C24C.c
+171 -1
View File
@@ -4204,4 +4204,174 @@ extern void func_801811A8(void);
INCLUDE_ASM("asm/ov_SC06_020/nonmatchings/ov_SC06_020_jr_8017C24C", func_8017FF48);
INCLUDE_ASM("asm/ov_SC06_020/nonmatchings/ov_SC06_020_jr_8017C24C", func_801800C8);
/* func_801800C8 (ov_SC06_018_jr_8017C24C) — MATCH 198/198, relocation-masked.
* @class: regalloc-copy + schedule
* @stuck: none. Three load-bearing idioms:
* 1. ONE shared scratch `t` for all three `sll 16` compares. Three separate temps let
* local-alloc TIE the short temp to `iVar1` (no `addu $s1,$v0,$zero` at all, 197 ins);
* the shared `t` conflicts with `iVar1` so the copy survives.
* 2. `t = t << 16; if (t <= 0)` instead of `if ((s16)t <= 0)` at the FIRST site only.
* With the natural cast the shift lands in a fresh pseudo, so local-alloc's
* `optimize_reg_copy_1` (local-alloc.c:700, called at :1007 — MIPS never defines
* SMALL_REGISTER_CLASSES so pins cannot block it) finds `t` dying there and rewrites the
* use to the copy's destination -> `sll $v0,$s1,16`. Shifting IN PLACE makes the insn
* SET `t`, which trips the `reg_set_p (src, p)` break in the forward scan (and flow emits
* no REG_DEAD when a reg is set in the insn that last uses it, cookbook §45 Lever B)
* -> the scan aborts, the use stays on `$v0`: `sll $v0,$v0,16`. Cookbook §25 triage tell.
* Sites 2 and 3 (0xFE / 0x76) have no copy insn, so `(s16)t <= 0` is correct there.
* 3. case 8 assigns `ptr` AFTER the func_8012A828 call. Assigning it first gives the
* `la $s1,D_8019E9FC` a low enough LUID to win the `lhu 0x70` load-delay slot, which
* eats the target's `nop` (-1 ins). $s1 is callee-saved, so sched1 still hoists the
* `la` back above the call — just not into the delay slot.
* Also: `D_8019E994 + 8` (not a separate D_801B516C symbol) is what produces the CSE'd
* `addiu $a1,$s2,0x8` off the $s2 base; two symbols would emit a second lui/addiu pair.
* The `| 0x40000000 | 0x20000000` must stay as TWO ors — gcc-2.7.2 fold has no associate
* step for BIT_IOR_EXPR, and a folded `| 0x60000000` emits only one lui/or.
*/
extern u8 D_8019E994[];
extern u8 D_8019E8B4[];
extern u8 D_801A4EAC;
extern u8 D_8019EA1C[];
extern u8 D_8019E9FC[];
extern u8 D_8019EA0C[];
extern u8 D_8019E9EC[];
extern u8 D_801B6598[];
extern void *D_8019EB7C[];
extern void func_8012E9C0(s32 a0);
extern void func_8012B23C(s32 a0);
extern void func_8012F214(s32, s32, s32);
extern s32 func_801833F4(void *a0, s32 a1, s32 a2);
extern s32 func_80146A6C(s32 a0, void *a1, s32 a2, s32 a3, s32 a4, s32 a5, s32 a6);
extern void func_801834F0(s32 a0, void *a1, void *a2, s32 a3);
extern void func_8018348C(s32 a0, void *a1, s32 a2, s32 a3, s32 a4, s32 a5);
extern void func_8001C924(s32 a0, void *a1);
extern void func_8012B14C(s32 a0, s32 a1); /* TU-canonical: matches the decl at ov_SC06_018_jr_8017C24C.c:7883 */
extern void func_8002A520(s32 a0);
extern void func_8002A790(s32 a0);
extern void func_80131E00(s32 a0, s32 a1);
extern void func_8012B2CC(s32 a0);
extern void func_80183FD0(s32 a0, s32 a1);
extern void func_8012A828(s32 a0, void *a1);
extern void func_80181654(s32 a0, s32 a1);
void func_801800C8(s32 p) {
s32 buf20[2];
s32 iVar1;
s32 iVar2;
s32 t;
void *ptr;
func_8012E9C0(p);
*(s32 *)(p + 0x1C) = 0;
*(u16 *)(p + 0x5C) = *(u16 *)(p + 0x5C) & 0xFFFE;
func_8012B23C(p);
t = (*(s16 *)(p + 0x60) * *(s16 *)(*(s32 *)(p + 0x78) + 0x30)) >> 12;
iVar1 = t;
t = t << 16;
if (t <= 0) {
iVar1 = 1;
}
if (*(u32 *)(p + 0xE0) & 1) {
((void (*)(s32, void *, void *))func_8012F214)(p, D_8019E994, buf20);
if (func_801833F4(buf20, *(s16 *)(*(s32 *)(p + 0x20) + 0x12), 0x400) != 0) {
func_80146A6C(6, (void *)p, *(s16 *)(p + 0x7C), *(s16 *)(p + 0x7E),
*(s16 *)(p + 0x80), 0, 0);
t = *(u16 *)(p + 0xFE) - iVar1;
*(s16 *)(p + 0xFE) = t;
if ((s16)t <= 0) {
func_801834F0(p, D_8019E994 + 8, buf20, 0xC);
func_8018348C(p, buf20, 0x27F, 0, 0, 0);
*(s32 *)(p + 0x58) = (s32)D_8019E8B4 | 0x40000000 | 0x20000000;
*(u32 *)(p + 0xE0) = *(u32 *)(p + 0xE0) & 0xFFFFFFFE;
func_8001C924(*(s32 *)(p + 0x20), &D_801A4EAC);
}
func_8012B14C(p, (s32)D_8019EA1C);
*(s16 *)(p + 0x34) = 3;
return;
}
}
if (*(u16 *)(p + 0x5E) != 0x1D) {
if (*(u8 *)(p + 0xC8) != 0) {
func_8002A520(p);
}
if (*(u8 *)(p + 0xC9) != 0) {
func_8002A790(p);
}
}
t = *(u16 *)(p + 0x76) - iVar1;
*(s16 *)(p + 0x76) = t;
if ((s16)t <= 0) {
func_80131E00(p, 0xC);
return;
}
*(s16 *)(p + 0x98) = 0;
*(u16 *)(*(s32 *)(p + 0x20) + 0x12) = (*(u16 *)(p + 0x62) + 0x800) & 0xFFF;
iVar2 = *(s32 *)(p + 0x20);
*(s16 *)(iVar2 + 0x14) = 0;
*(s16 *)(iVar2 + 0x10) = 0;
func_8012B2CC(p);
func_80183FD0(p, 0x9B7);
switch (*(u16 *)(p + 0x5E)) {
case 1:
case 2:
case 3:
case 4:
case 6:
case 7:
case 0xB:
case 0xC:
case 0x10:
case 0x13:
case 0x14:
case 0x15:
case 0x16:
case 0x17:
case 0x18:
case 0x19:
case 0x1A:
case 0x23:
case 0x24:
case 0x25:
case 0x28:
case 0x2B:
case 0x2C:
case 0x2D:
case 0x2E:
case 0x2F:
case 0x30:
case 0x31:
case 0x32:
*(s16 *)(p + 0x34) = 4;
func_8012A828(p, D_8019EB7C[*(u16 *)(p + 0x70) & 0xF]);
return;
case 8:
func_8012A828(p, D_8019EB7C[*(u16 *)(p + 0x70) & 0xF]);
ptr = D_8019E9FC;
break;
case 5:
case 0x1D:
case 0x20:
case 0x26:
case 0x2A:
ptr = D_8019EA0C;
func_8012A828(p, D_801B6598);
*(u32 *)(p + 0xE0) = *(u32 *)(p + 0xE0) | 8;
*(u16 *)(p + 0xAE) = *(u16 *)(p + 0xAE) | 1;
func_80181654(p, -0x8000);
break;
default:
ptr = D_8019E9EC;
break;
}
func_8012B14C(p, (s32)ptr);
*(s16 *)(p + 0x34) = 0;
}
src/ov_SC06_022/ov_SC06_022_jr_80182D08.c
+171 -1
View File
@@ -3259,4 +3259,174 @@ extern void func_801850CC(void);
INCLUDE_ASM("asm/ov_SC06_022/nonmatchings/ov_SC06_022_jr_80182D08", func_80183E6C);
INCLUDE_ASM("asm/ov_SC06_022/nonmatchings/ov_SC06_022_jr_80182D08", func_80183FEC);
/* func_80183FEC (ov_SC06_018_jr_8017C24C) — MATCH 198/198, relocation-masked.
* @class: regalloc-copy + schedule
* @stuck: none. Three load-bearing idioms:
* 1. ONE shared scratch `t` for all three `sll 16` compares. Three separate temps let
* local-alloc TIE the short temp to `iVar1` (no `addu $s1,$v0,$zero` at all, 197 ins);
* the shared `t` conflicts with `iVar1` so the copy survives.
* 2. `t = t << 16; if (t <= 0)` instead of `if ((s16)t <= 0)` at the FIRST site only.
* With the natural cast the shift lands in a fresh pseudo, so local-alloc's
* `optimize_reg_copy_1` (local-alloc.c:700, called at :1007 — MIPS never defines
* SMALL_REGISTER_CLASSES so pins cannot block it) finds `t` dying there and rewrites the
* use to the copy's destination -> `sll $v0,$s1,16`. Shifting IN PLACE makes the insn
* SET `t`, which trips the `reg_set_p (src, p)` break in the forward scan (and flow emits
* no REG_DEAD when a reg is set in the insn that last uses it, cookbook §45 Lever B)
* -> the scan aborts, the use stays on `$v0`: `sll $v0,$v0,16`. Cookbook §25 triage tell.
* Sites 2 and 3 (0xFE / 0x76) have no copy insn, so `(s16)t <= 0` is correct there.
* 3. case 8 assigns `ptr` AFTER the func_8012A828 call. Assigning it first gives the
* `la $s1,D_801BD124` a low enough LUID to win the `lhu 0x70` load-delay slot, which
* eats the target's `nop` (-1 ins). $s1 is callee-saved, so sched1 still hoists the
* `la` back above the call — just not into the delay slot.
* Also: `D_801BD0BC + 8` (not a separate D_801B516C symbol) is what produces the CSE'd
* `addiu $a1,$s2,0x8` off the $s2 base; two symbols would emit a second lui/addiu pair.
* The `| 0x40000000 | 0x20000000` must stay as TWO ors — gcc-2.7.2 fold has no associate
* step for BIT_IOR_EXPR, and a folded `| 0x60000000` emits only one lui/or.
*/
extern u8 D_801BD0BC[];
extern u8 D_801BCFDC[];
extern u8 D_801C35D4;
extern u8 D_801BD144[];
extern u8 D_801BD124[];
extern u8 D_801BD134[];
extern u8 D_801BD114[];
extern u8 D_801D4CC0[];
extern void *D_801BD2A4[];
extern void func_8012E9C0(s32 a0);
extern void func_8012B23C(s32 a0);
extern void func_8012F214(s32, s32, s32);
extern s32 func_80187318(void *a0, s32 a1, s32 a2);
extern s32 func_80146A6C(s32 a0, void *a1, s32 a2, s32 a3, s32 a4, s32 a5, s32 a6);
extern void func_80187414(s32 a0, void *a1, void *a2, s32 a3);
extern void func_801873B0(s32 a0, void *a1, s32 a2, s32 a3, s32 a4, s32 a5);
extern void func_8001C924(s32 a0, void *a1);
extern void func_8012B14C(s32 a0, s32 a1); /* TU-canonical: matches the decl at ov_SC06_018_jr_8017C24C.c:7883 */
extern void func_8002A520(s32 a0);
extern void func_8002A790(s32 a0);
extern void func_80131E00(s32 a0, s32 a1);
extern void func_8012B2CC(s32 a0);
extern void func_80187EF4(s32 a0, s32 a1);
extern void func_8012A828(s32 a0, void *a1);
extern void func_80185578(s32 a0, s32 a1);
void func_80183FEC(s32 p) {
s32 buf20[2];
s32 iVar1;
s32 iVar2;
s32 t;
void *ptr;
func_8012E9C0(p);
*(s32 *)(p + 0x1C) = 0;
*(u16 *)(p + 0x5C) = *(u16 *)(p + 0x5C) & 0xFFFE;
func_8012B23C(p);
t = (*(s16 *)(p + 0x60) * *(s16 *)(*(s32 *)(p + 0x78) + 0x30)) >> 12;
iVar1 = t;
t = t << 16;
if (t <= 0) {
iVar1 = 1;
}
if (*(u32 *)(p + 0xE0) & 1) {
((void (*)(s32, void *, void *))func_8012F214)(p, D_801BD0BC, buf20);
if (func_80187318(buf20, *(s16 *)(*(s32 *)(p + 0x20) + 0x12), 0x400) != 0) {
func_80146A6C(6, (void *)p, *(s16 *)(p + 0x7C), *(s16 *)(p + 0x7E),
*(s16 *)(p + 0x80), 0, 0);
t = *(u16 *)(p + 0xFE) - iVar1;
*(s16 *)(p + 0xFE) = t;
if ((s16)t <= 0) {
func_80187414(p, D_801BD0BC + 8, buf20, 0xC);
func_801873B0(p, buf20, 0x27F, 0, 0, 0);
*(s32 *)(p + 0x58) = (s32)D_801BCFDC | 0x40000000 | 0x20000000;
*(u32 *)(p + 0xE0) = *(u32 *)(p + 0xE0) & 0xFFFFFFFE;
func_8001C924(*(s32 *)(p + 0x20), &D_801C35D4);
}
func_8012B14C(p, (s32)D_801BD144);
*(s16 *)(p + 0x34) = 3;
return;
}
}
if (*(u16 *)(p + 0x5E) != 0x1D) {
if (*(u8 *)(p + 0xC8) != 0) {
func_8002A520(p);
}
if (*(u8 *)(p + 0xC9) != 0) {
func_8002A790(p);
}
}
t = *(u16 *)(p + 0x76) - iVar1;
*(s16 *)(p + 0x76) = t;
if ((s16)t <= 0) {
func_80131E00(p, 0xC);
return;
}
*(s16 *)(p + 0x98) = 0;
*(u16 *)(*(s32 *)(p + 0x20) + 0x12) = (*(u16 *)(p + 0x62) + 0x800) & 0xFFF;
iVar2 = *(s32 *)(p + 0x20);
*(s16 *)(iVar2 + 0x14) = 0;
*(s16 *)(iVar2 + 0x10) = 0;
func_8012B2CC(p);
func_80187EF4(p, 0x9B7);
switch (*(u16 *)(p + 0x5E)) {
case 1:
case 2:
case 3:
case 4:
case 6:
case 7:
case 0xB:
case 0xC:
case 0x10:
case 0x13:
case 0x14:
case 0x15:
case 0x16:
case 0x17:
case 0x18:
case 0x19:
case 0x1A:
case 0x23:
case 0x24:
case 0x25:
case 0x28:
case 0x2B:
case 0x2C:
case 0x2D:
case 0x2E:
case 0x2F:
case 0x30:
case 0x31:
case 0x32:
*(s16 *)(p + 0x34) = 4;
func_8012A828(p, D_801BD2A4[*(u16 *)(p + 0x70) & 0xF]);
return;
case 8:
func_8012A828(p, D_801BD2A4[*(u16 *)(p + 0x70) & 0xF]);
ptr = D_801BD124;
break;
case 5:
case 0x1D:
case 0x20:
case 0x26:
case 0x2A:
ptr = D_801BD134;
func_8012A828(p, D_801D4CC0);
*(u32 *)(p + 0xE0) = *(u32 *)(p + 0xE0) | 8;
*(u16 *)(p + 0xAE) = *(u16 *)(p + 0xAE) | 1;
func_80185578(p, -0x8000);
break;
default:
ptr = D_801BD114;
break;
}
func_8012B14C(p, (s32)ptr);
*(s16 *)(p + 0x34) = 0;
}
src/ov_SC06_024/ov_SC06_024_jr_801851E0.c
+171 -1
View File
@@ -3203,4 +3203,174 @@ extern void func_801875A4(void);
INCLUDE_ASM("asm/ov_SC06_024/nonmatchings/ov_SC06_024_jr_801851E0", func_80186344);
INCLUDE_ASM("asm/ov_SC06_024/nonmatchings/ov_SC06_024_jr_801851E0", func_801864C4);
/* func_801864C4 (ov_SC06_018_jr_8017C24C) — MATCH 198/198, relocation-masked.
* @class: regalloc-copy + schedule
* @stuck: none. Three load-bearing idioms:
* 1. ONE shared scratch `t` for all three `sll 16` compares. Three separate temps let
* local-alloc TIE the short temp to `iVar1` (no `addu $s1,$v0,$zero` at all, 197 ins);
* the shared `t` conflicts with `iVar1` so the copy survives.
* 2. `t = t << 16; if (t <= 0)` instead of `if ((s16)t <= 0)` at the FIRST site only.
* With the natural cast the shift lands in a fresh pseudo, so local-alloc's
* `optimize_reg_copy_1` (local-alloc.c:700, called at :1007 — MIPS never defines
* SMALL_REGISTER_CLASSES so pins cannot block it) finds `t` dying there and rewrites the
* use to the copy's destination -> `sll $v0,$s1,16`. Shifting IN PLACE makes the insn
* SET `t`, which trips the `reg_set_p (src, p)` break in the forward scan (and flow emits
* no REG_DEAD when a reg is set in the insn that last uses it, cookbook §45 Lever B)
* -> the scan aborts, the use stays on `$v0`: `sll $v0,$v0,16`. Cookbook §25 triage tell.
* Sites 2 and 3 (0xFE / 0x76) have no copy insn, so `(s16)t <= 0` is correct there.
* 3. case 8 assigns `ptr` AFTER the func_8012A828 call. Assigning it first gives the
* `la $s1,D_801BC268` a low enough LUID to win the `lhu 0x70` load-delay slot, which
* eats the target's `nop` (-1 ins). $s1 is callee-saved, so sched1 still hoists the
* `la` back above the call — just not into the delay slot.
* Also: `D_801BC200 + 8` (not a separate D_801B516C symbol) is what produces the CSE'd
* `addiu $a1,$s2,0x8` off the $s2 base; two symbols would emit a second lui/addiu pair.
* The `| 0x40000000 | 0x20000000` must stay as TWO ors — gcc-2.7.2 fold has no associate
* step for BIT_IOR_EXPR, and a folded `| 0x60000000` emits only one lui/or.
*/
extern u8 D_801BC200[];
extern u8 D_801BC120[];
extern u8 D_801C2718;
extern u8 D_801BC288[];
extern u8 D_801BC268[];
extern u8 D_801BC278[];
extern u8 D_801BC258[];
extern u8 D_801D3E04[];
extern void *D_801BC3E8[];
extern void func_8012E9C0(s32 a0);
extern void func_8012B23C(s32 a0);
extern void func_8012F214(s32, s32, s32);
extern s32 func_801897F0(void *a0, s32 a1, s32 a2);
extern s32 func_80146A6C(s32 a0, void *a1, s32 a2, s32 a3, s32 a4, s32 a5, s32 a6);
extern void func_801898EC(s32 a0, void *a1, void *a2, s32 a3);
extern void func_80189888(s32 a0, void *a1, s32 a2, s32 a3, s32 a4, s32 a5);
extern void func_8001C924(s32 a0, void *a1);
extern void func_8012B14C(s32 a0, s32 a1); /* TU-canonical: matches the decl at ov_SC06_018_jr_8017C24C.c:7883 */
extern void func_8002A520(s32 a0);
extern void func_8002A790(s32 a0);
extern void func_80131E00(s32 a0, s32 a1);
extern void func_8012B2CC(s32 a0);
extern void func_8018A3CC(s32 a0, s32 a1);
extern void func_8012A828(s32 a0, void *a1);
extern void func_80187A50(s32 a0, s32 a1);
void func_801864C4(s32 p) {
s32 buf20[2];
s32 iVar1;
s32 iVar2;
s32 t;
void *ptr;
func_8012E9C0(p);
*(s32 *)(p + 0x1C) = 0;
*(u16 *)(p + 0x5C) = *(u16 *)(p + 0x5C) & 0xFFFE;
func_8012B23C(p);
t = (*(s16 *)(p + 0x60) * *(s16 *)(*(s32 *)(p + 0x78) + 0x30)) >> 12;
iVar1 = t;
t = t << 16;
if (t <= 0) {
iVar1 = 1;
}
if (*(u32 *)(p + 0xE0) & 1) {
((void (*)(s32, void *, void *))func_8012F214)(p, D_801BC200, buf20);
if (func_801897F0(buf20, *(s16 *)(*(s32 *)(p + 0x20) + 0x12), 0x400) != 0) {
func_80146A6C(6, (void *)p, *(s16 *)(p + 0x7C), *(s16 *)(p + 0x7E),
*(s16 *)(p + 0x80), 0, 0);
t = *(u16 *)(p + 0xFE) - iVar1;
*(s16 *)(p + 0xFE) = t;
if ((s16)t <= 0) {
func_801898EC(p, D_801BC200 + 8, buf20, 0xC);
func_80189888(p, buf20, 0x27F, 0, 0, 0);
*(s32 *)(p + 0x58) = (s32)D_801BC120 | 0x40000000 | 0x20000000;
*(u32 *)(p + 0xE0) = *(u32 *)(p + 0xE0) & 0xFFFFFFFE;
func_8001C924(*(s32 *)(p + 0x20), &D_801C2718);
}
func_8012B14C(p, (s32)D_801BC288);
*(s16 *)(p + 0x34) = 3;
return;
}
}
if (*(u16 *)(p + 0x5E) != 0x1D) {
if (*(u8 *)(p + 0xC8) != 0) {
func_8002A520(p);
}
if (*(u8 *)(p + 0xC9) != 0) {
func_8002A790(p);
}
}
t = *(u16 *)(p + 0x76) - iVar1;
*(s16 *)(p + 0x76) = t;
if ((s16)t <= 0) {
func_80131E00(p, 0xC);
return;
}
*(s16 *)(p + 0x98) = 0;
*(u16 *)(*(s32 *)(p + 0x20) + 0x12) = (*(u16 *)(p + 0x62) + 0x800) & 0xFFF;
iVar2 = *(s32 *)(p + 0x20);
*(s16 *)(iVar2 + 0x14) = 0;
*(s16 *)(iVar2 + 0x10) = 0;
func_8012B2CC(p);
func_8018A3CC(p, 0x9B7);
switch (*(u16 *)(p + 0x5E)) {
case 1:
case 2:
case 3:
case 4:
case 6:
case 7:
case 0xB:
case 0xC:
case 0x10:
case 0x13:
case 0x14:
case 0x15:
case 0x16:
case 0x17:
case 0x18:
case 0x19:
case 0x1A:
case 0x23:
case 0x24:
case 0x25:
case 0x28:
case 0x2B:
case 0x2C:
case 0x2D:
case 0x2E:
case 0x2F:
case 0x30:
case 0x31:
case 0x32:
*(s16 *)(p + 0x34) = 4;
func_8012A828(p, D_801BC3E8[*(u16 *)(p + 0x70) & 0xF]);
return;
case 8:
func_8012A828(p, D_801BC3E8[*(u16 *)(p + 0x70) & 0xF]);
ptr = D_801BC268;
break;
case 5:
case 0x1D:
case 0x20:
case 0x26:
case 0x2A:
ptr = D_801BC278;
func_8012A828(p, D_801D3E04);
*(u32 *)(p + 0xE0) = *(u32 *)(p + 0xE0) | 8;
*(u16 *)(p + 0xAE) = *(u16 *)(p + 0xAE) | 1;
func_80187A50(p, -0x8000);
break;
default:
ptr = D_801BC258;
break;
}
func_8012B14C(p, (s32)ptr);
*(s16 *)(p + 0x34) = 0;
}
src/ov_SC06_032/ov_SC06_032_jr_8017C24C.c
+171 -1
View File
@@ -4629,4 +4629,174 @@ extern void func_80181DDC(void);
INCLUDE_ASM("asm/ov_SC06_032/nonmatchings/ov_SC06_032_jr_8017C24C", func_80180B7C);
INCLUDE_ASM("asm/ov_SC06_032/nonmatchings/ov_SC06_032_jr_8017C24C", func_80180CFC);
/* func_80180CFC (ov_SC06_018_jr_8017C24C) — MATCH 198/198, relocation-masked.
* @class: regalloc-copy + schedule
* @stuck: none. Three load-bearing idioms:
* 1. ONE shared scratch `t` for all three `sll 16` compares. Three separate temps let
* local-alloc TIE the short temp to `iVar1` (no `addu $s1,$v0,$zero` at all, 197 ins);
* the shared `t` conflicts with `iVar1` so the copy survives.
* 2. `t = t << 16; if (t <= 0)` instead of `if ((s16)t <= 0)` at the FIRST site only.
* With the natural cast the shift lands in a fresh pseudo, so local-alloc's
* `optimize_reg_copy_1` (local-alloc.c:700, called at :1007 — MIPS never defines
* SMALL_REGISTER_CLASSES so pins cannot block it) finds `t` dying there and rewrites the
* use to the copy's destination -> `sll $v0,$s1,16`. Shifting IN PLACE makes the insn
* SET `t`, which trips the `reg_set_p (src, p)` break in the forward scan (and flow emits
* no REG_DEAD when a reg is set in the insn that last uses it, cookbook §45 Lever B)
* -> the scan aborts, the use stays on `$v0`: `sll $v0,$v0,16`. Cookbook §25 triage tell.
* Sites 2 and 3 (0xFE / 0x76) have no copy insn, so `(s16)t <= 0` is correct there.
* 3. case 8 assigns `ptr` AFTER the func_8012A828 call. Assigning it first gives the
* `la $s1,D_801A665C` a low enough LUID to win the `lhu 0x70` load-delay slot, which
* eats the target's `nop` (-1 ins). $s1 is callee-saved, so sched1 still hoists the
* `la` back above the call — just not into the delay slot.
* Also: `D_801A65F4 + 8` (not a separate D_801B516C symbol) is what produces the CSE'd
* `addiu $a1,$s2,0x8` off the $s2 base; two symbols would emit a second lui/addiu pair.
* The `| 0x40000000 | 0x20000000` must stay as TWO ors — gcc-2.7.2 fold has no associate
* step for BIT_IOR_EXPR, and a folded `| 0x60000000` emits only one lui/or.
*/
extern u8 D_801A65F4[];
extern u8 D_801A6514[];
extern u8 D_801ACB0C;
extern u8 D_801A667C[];
extern u8 D_801A665C[];
extern u8 D_801A666C[];
extern u8 D_801A664C[];
extern u8 D_801BE1F8[];
extern void *D_801A67DC[];
extern void func_8012E9C0(s32 a0);
extern void func_8012B23C(s32 a0);
extern void func_8012F214(s32, s32, s32);
extern s32 func_80184028(void *a0, s32 a1, s32 a2);
extern s32 func_80146A6C(s32 a0, void *a1, s32 a2, s32 a3, s32 a4, s32 a5, s32 a6);
extern void func_80184124(s32 a0, void *a1, void *a2, s32 a3);
extern void func_801840C0(s32 a0, void *a1, s32 a2, s32 a3, s32 a4, s32 a5);
extern void func_8001C924(s32 a0, void *a1);
extern void func_8012B14C(s32 a0, s32 a1); /* TU-canonical: matches the decl at ov_SC06_018_jr_8017C24C.c:7883 */
extern void func_8002A520(s32 a0);
extern void func_8002A790(s32 a0);
extern void func_80131E00(s32 a0, s32 a1);
extern void func_8012B2CC(s32 a0);
extern void func_80184C04(s32 a0, s32 a1);
extern void func_8012A828(s32 a0, void *a1);
extern void func_80182288(s32 a0, s32 a1);
void func_80180CFC(s32 p) {
s32 buf20[2];
s32 iVar1;
s32 iVar2;
s32 t;
void *ptr;
func_8012E9C0(p);
*(s32 *)(p + 0x1C) = 0;
*(u16 *)(p + 0x5C) = *(u16 *)(p + 0x5C) & 0xFFFE;
func_8012B23C(p);
t = (*(s16 *)(p + 0x60) * *(s16 *)(*(s32 *)(p + 0x78) + 0x30)) >> 12;
iVar1 = t;
t = t << 16;
if (t <= 0) {
iVar1 = 1;
}
if (*(u32 *)(p + 0xE0) & 1) {
((void (*)(s32, void *, void *))func_8012F214)(p, D_801A65F4, buf20);
if (func_80184028(buf20, *(s16 *)(*(s32 *)(p + 0x20) + 0x12), 0x400) != 0) {
func_80146A6C(6, (void *)p, *(s16 *)(p + 0x7C), *(s16 *)(p + 0x7E),
*(s16 *)(p + 0x80), 0, 0);
t = *(u16 *)(p + 0xFE) - iVar1;
*(s16 *)(p + 0xFE) = t;
if ((s16)t <= 0) {
func_80184124(p, D_801A65F4 + 8, buf20, 0xC);
func_801840C0(p, buf20, 0x27F, 0, 0, 0);
*(s32 *)(p + 0x58) = (s32)D_801A6514 | 0x40000000 | 0x20000000;
*(u32 *)(p + 0xE0) = *(u32 *)(p + 0xE0) & 0xFFFFFFFE;
func_8001C924(*(s32 *)(p + 0x20), &D_801ACB0C);
}
func_8012B14C(p, (s32)D_801A667C);
*(s16 *)(p + 0x34) = 3;
return;
}
}
if (*(u16 *)(p + 0x5E) != 0x1D) {
if (*(u8 *)(p + 0xC8) != 0) {
func_8002A520(p);
}
if (*(u8 *)(p + 0xC9) != 0) {
func_8002A790(p);
}
}
t = *(u16 *)(p + 0x76) - iVar1;
*(s16 *)(p + 0x76) = t;
if ((s16)t <= 0) {
func_80131E00(p, 0xC);
return;
}
*(s16 *)(p + 0x98) = 0;
*(u16 *)(*(s32 *)(p + 0x20) + 0x12) = (*(u16 *)(p + 0x62) + 0x800) & 0xFFF;
iVar2 = *(s32 *)(p + 0x20);
*(s16 *)(iVar2 + 0x14) = 0;
*(s16 *)(iVar2 + 0x10) = 0;
func_8012B2CC(p);
func_80184C04(p, 0x9B7);
switch (*(u16 *)(p + 0x5E)) {
case 1:
case 2:
case 3:
case 4:
case 6:
case 7:
case 0xB:
case 0xC:
case 0x10:
case 0x13:
case 0x14:
case 0x15:
case 0x16:
case 0x17:
case 0x18:
case 0x19:
case 0x1A:
case 0x23:
case 0x24:
case 0x25:
case 0x28:
case 0x2B:
case 0x2C:
case 0x2D:
case 0x2E:
case 0x2F:
case 0x30:
case 0x31:
case 0x32:
*(s16 *)(p + 0x34) = 4;
func_8012A828(p, D_801A67DC[*(u16 *)(p + 0x70) & 0xF]);
return;
case 8:
func_8012A828(p, D_801A67DC[*(u16 *)(p + 0x70) & 0xF]);
ptr = D_801A665C;
break;
case 5:
case 0x1D:
case 0x20:
case 0x26:
case 0x2A:
ptr = D_801A666C;
func_8012A828(p, D_801BE1F8);
*(u32 *)(p + 0xE0) = *(u32 *)(p + 0xE0) | 8;
*(u16 *)(p + 0xAE) = *(u16 *)(p + 0xAE) | 1;
func_80182288(p, -0x8000);
break;
default:
ptr = D_801A664C;
break;
}
func_8012B14C(p, (s32)ptr);
*(s16 *)(p + 0x34) = 0;
}
src/ov_SC06_033/ov_SC06_033_jr_801836FC.c
+171 -1
View File
@@ -3327,4 +3327,174 @@ extern void func_80185AC0(void);
INCLUDE_ASM("asm/ov_SC06_033/nonmatchings/ov_SC06_033_jr_801836FC", func_80184860);
INCLUDE_ASM("asm/ov_SC06_033/nonmatchings/ov_SC06_033_jr_801836FC", func_801849E0);
/* func_801849E0 (ov_SC06_018_jr_8017C24C) — MATCH 198/198, relocation-masked.
* @class: regalloc-copy + schedule
* @stuck: none. Three load-bearing idioms:
* 1. ONE shared scratch `t` for all three `sll 16` compares. Three separate temps let
* local-alloc TIE the short temp to `iVar1` (no `addu $s1,$v0,$zero` at all, 197 ins);
* the shared `t` conflicts with `iVar1` so the copy survives.
* 2. `t = t << 16; if (t <= 0)` instead of `if ((s16)t <= 0)` at the FIRST site only.
* With the natural cast the shift lands in a fresh pseudo, so local-alloc's
* `optimize_reg_copy_1` (local-alloc.c:700, called at :1007 — MIPS never defines
* SMALL_REGISTER_CLASSES so pins cannot block it) finds `t` dying there and rewrites the
* use to the copy's destination -> `sll $v0,$s1,16`. Shifting IN PLACE makes the insn
* SET `t`, which trips the `reg_set_p (src, p)` break in the forward scan (and flow emits
* no REG_DEAD when a reg is set in the insn that last uses it, cookbook §45 Lever B)
* -> the scan aborts, the use stays on `$v0`: `sll $v0,$v0,16`. Cookbook §25 triage tell.
* Sites 2 and 3 (0xFE / 0x76) have no copy insn, so `(s16)t <= 0` is correct there.
* 3. case 8 assigns `ptr` AFTER the func_8012A828 call. Assigning it first gives the
* `la $s1,D_801AF9F0` a low enough LUID to win the `lhu 0x70` load-delay slot, which
* eats the target's `nop` (-1 ins). $s1 is callee-saved, so sched1 still hoists the
* `la` back above the call — just not into the delay slot.
* Also: `D_801AF988 + 8` (not a separate D_801B516C symbol) is what produces the CSE'd
* `addiu $a1,$s2,0x8` off the $s2 base; two symbols would emit a second lui/addiu pair.
* The `| 0x40000000 | 0x20000000` must stay as TWO ors — gcc-2.7.2 fold has no associate
* step for BIT_IOR_EXPR, and a folded `| 0x60000000` emits only one lui/or.
*/
extern u8 D_801AF988[];
extern u8 D_801AF8A8[];
extern u8 D_801B5EA0;
extern u8 D_801AFA10[];
extern u8 D_801AF9F0[];
extern u8 D_801AFA00[];
extern u8 D_801AF9E0[];
extern u8 D_801C758C[];
extern void *D_801AFB70[];
extern void func_8012E9C0(s32 a0);
extern void func_8012B23C(s32 a0);
extern void func_8012F214(s32, s32, s32);
extern s32 func_80187D0C(void *a0, s32 a1, s32 a2);
extern s32 func_80146A6C(s32 a0, void *a1, s32 a2, s32 a3, s32 a4, s32 a5, s32 a6);
extern void func_80187E08(s32 a0, void *a1, void *a2, s32 a3);
extern void func_80187DA4(s32 a0, void *a1, s32 a2, s32 a3, s32 a4, s32 a5);
extern void func_8001C924(s32 a0, void *a1);
extern void func_8012B14C(s32 a0, s32 a1); /* TU-canonical: matches the decl at ov_SC06_018_jr_8017C24C.c:7883 */
extern void func_8002A520(s32 a0);
extern void func_8002A790(s32 a0);
extern void func_80131E00(s32 a0, s32 a1);
extern void func_8012B2CC(s32 a0);
extern void func_801888E8(s32 a0, s32 a1);
extern void func_8012A828(s32 a0, void *a1);
extern void func_80185F6C(s32 a0, s32 a1);
void func_801849E0(s32 p) {
s32 buf20[2];
s32 iVar1;
s32 iVar2;
s32 t;
void *ptr;
func_8012E9C0(p);
*(s32 *)(p + 0x1C) = 0;
*(u16 *)(p + 0x5C) = *(u16 *)(p + 0x5C) & 0xFFFE;
func_8012B23C(p);
t = (*(s16 *)(p + 0x60) * *(s16 *)(*(s32 *)(p + 0x78) + 0x30)) >> 12;
iVar1 = t;
t = t << 16;
if (t <= 0) {
iVar1 = 1;
}
if (*(u32 *)(p + 0xE0) & 1) {
((void (*)(s32, void *, void *))func_8012F214)(p, D_801AF988, buf20);
if (func_80187D0C(buf20, *(s16 *)(*(s32 *)(p + 0x20) + 0x12), 0x400) != 0) {
func_80146A6C(6, (void *)p, *(s16 *)(p + 0x7C), *(s16 *)(p + 0x7E),
*(s16 *)(p + 0x80), 0, 0);
t = *(u16 *)(p + 0xFE) - iVar1;
*(s16 *)(p + 0xFE) = t;
if ((s16)t <= 0) {
func_80187E08(p, D_801AF988 + 8, buf20, 0xC);
func_80187DA4(p, buf20, 0x27F, 0, 0, 0);
*(s32 *)(p + 0x58) = (s32)D_801AF8A8 | 0x40000000 | 0x20000000;
*(u32 *)(p + 0xE0) = *(u32 *)(p + 0xE0) & 0xFFFFFFFE;
func_8001C924(*(s32 *)(p + 0x20), &D_801B5EA0);
}
func_8012B14C(p, (s32)D_801AFA10);
*(s16 *)(p + 0x34) = 3;
return;
}
}
if (*(u16 *)(p + 0x5E) != 0x1D) {
if (*(u8 *)(p + 0xC8) != 0) {
func_8002A520(p);
}
if (*(u8 *)(p + 0xC9) != 0) {
func_8002A790(p);
}
}
t = *(u16 *)(p + 0x76) - iVar1;
*(s16 *)(p + 0x76) = t;
if ((s16)t <= 0) {
func_80131E00(p, 0xC);
return;
}
*(s16 *)(p + 0x98) = 0;
*(u16 *)(*(s32 *)(p + 0x20) + 0x12) = (*(u16 *)(p + 0x62) + 0x800) & 0xFFF;
iVar2 = *(s32 *)(p + 0x20);
*(s16 *)(iVar2 + 0x14) = 0;
*(s16 *)(iVar2 + 0x10) = 0;
func_8012B2CC(p);
func_801888E8(p, 0x9B7);
switch (*(u16 *)(p + 0x5E)) {
case 1:
case 2:
case 3:
case 4:
case 6:
case 7:
case 0xB:
case 0xC:
case 0x10:
case 0x13:
case 0x14:
case 0x15:
case 0x16:
case 0x17:
case 0x18:
case 0x19:
case 0x1A:
case 0x23:
case 0x24:
case 0x25:
case 0x28:
case 0x2B:
case 0x2C:
case 0x2D:
case 0x2E:
case 0x2F:
case 0x30:
case 0x31:
case 0x32:
*(s16 *)(p + 0x34) = 4;
func_8012A828(p, D_801AFB70[*(u16 *)(p + 0x70) & 0xF]);
return;
case 8:
func_8012A828(p, D_801AFB70[*(u16 *)(p + 0x70) & 0xF]);
ptr = D_801AF9F0;
break;
case 5:
case 0x1D:
case 0x20:
case 0x26:
case 0x2A:
ptr = D_801AFA00;
func_8012A828(p, D_801C758C);
*(u32 *)(p + 0xE0) = *(u32 *)(p + 0xE0) | 8;
*(u16 *)(p + 0xAE) = *(u16 *)(p + 0xAE) | 1;
func_80185F6C(p, -0x8000);
break;
default:
ptr = D_801AF9E0;
break;
}
func_8012B14C(p, (s32)ptr);
*(s16 *)(p + 0x34) = 0;
}