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https://github.com/Druthulu/BFM-decomp
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feat(decomp): parallel gate — 1 fns across 1 binaries (1 workers)
ov_SC03_105 func_801818E8
This commit is contained in:
Drew T
@@ -2430,6 +2430,7 @@ build/src/ov_SC03_105/ov_SC03_105_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (
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build/src/ov_SC03_105/ov_SC03_105_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20
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build/src/ov_SC03_105/ov_SC03_105_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178
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build/src/ov_SC03_105/ov_SC03_105_jr_8017C8D0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x34
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build/src/ov_SC03_105/ov_SC03_105_jr_801813BC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x30
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build/src/ov_SC03_105/ov_SC03_105_jr_8018624C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x38
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build/src/ov_SC03_105/ov_SC03_105_o0c.o: JTBL_PADS := 0,4,4,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x38,+0xa8,+0x118
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ov_SC03_105_CHECK_SHA := config/check.ov_SC03_105.sha
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@@ -176,7 +176,7 @@ segments:
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- [0x8ffa8, .rodata, ov_SC03_105_jr_8017C8D0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
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- [0x8fff4, data, tail19]
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- [0x9005c, .rodata, ov_SC03_105_jr_801813BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
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- [0x90088, data, tail20]
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- [0x900a0, data, tail20]
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- [0x900a4, .rodata, ov_SC03_105_jr_80181C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
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- [0x900d4, data, tail21]
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- [0x900e8, .rodata, ov_SC03_105_jr_8018624C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
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@@ -3106,5 +3106,162 @@ void func_801813BC(s32 a0) {
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}
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INCLUDE_ASM("asm/ov_SC03_105/nonmatchings/ov_SC03_105_jr_801813BC", func_801818E8);
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#include "common.h"
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/* func_801818E8 @ 0x801818E8 (ov_SC03_105, 231 ins) -- MATCH
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*
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* Boss/NPC state machine, 5-arm jump table on the u16 state word at +0x34
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* (jtbl_801B81E4, cases 0..4 contiguous, default falls through to the shared
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* tail). 0 = pick a random destination row out of D_8018E87C and aim at it,
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* 1 = walk until func_80013478 reports range <= 0x100 then latch the row's
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* XYZ into +0x6/+0xA/+0xE, 2/4 = drive the +0x14 turn field via func_8012B608,
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* 3 = attack (func_8018383C on the D_801BCBBC-selected D_8018E84C row) then
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* re-aim, 4 = retreat and, once func_80013350 reports <= 0x40, reset via
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* func_80183F0C and return EARLY (skipping the tail).
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*
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* Notes for the banker:
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* - `s32 sp10[3]; s32 sp20;` in that order is what gives the 0x48 frame
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* (§TU:3846 idiom, same as func_8017E7E8): 0x00..0x13 outgoing args (5 for
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* func_801824CC), sp10 at 0x18, sp20 at 0x28 on its 8-byte stride.
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* - LOAD-BEARING (§3-F / sched.c:817 true_dependence): the three table reads
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* in case 0 MUST be written as `*(u16 *)(t + K)` with `t` an s32, NOT as
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* `t[K/2]` on a `u16 *`. expr.c's INDIRECT_REF case sets MEM_IN_STRUCT_P
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* whenever the address expression is a PLUS_EXPR, so `t[1]`/`t[2]` become
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* `/s` MEMs at a varying address; paired against the NON-`/s` sh's at the
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* FIXED frame address sp+0x1A/0x1E/0x22 that is exactly true_dependence's
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* struct-vs-fixed-scalar escape, the dependence is dropped and sched1
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* hoists all three lhu above all three sh (16 mismatches). The cast makes
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* the address a CONVERT_EXPR, MEM_IN_STRUCT_P stays 0, the edge comes back
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* and the lhu/sh pairs interleave as the target has them. Zero bytes.
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* - the +0x20 object pointer is deliberately re-read after every call rather
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* than cached: the target has the second `lw 0x20($s0)` in cases 2/3/4.
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* - func_80183C20 / func_80183D38 are declared `void` in this TU but do
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* return a value here; taken through the TU's house function-pointer cast.
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*/
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/* ---- callees: TU spellings where the TU already has one, fleet-modal otherwise ---- */
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extern s32 rand(void); /* TU:958 */
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extern s32 func_8012B77C(s32 out, s32 from, s32 to); /* TU:3842 */
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extern s32 func_8012B608(s32 a0, s32 a1, s32 a2); /* fleet modal x1803 */
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extern s32 func_8012BEE8(s32 a0); /* TU:3924 */
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extern s32 func_8012CBF4(s32 a0); /* TU:3927 */
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extern s32 func_80013478(s32 a0, s32 a1); /* fleet modal x1374 */
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extern s32 func_80013350(s32 a0, s32 a1);
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extern void func_8018373C(void *a0, s32 a1); /* defined in this TU */
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extern void func_8018383C(s32 a0, s32 a1); /* defined in this TU */
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extern s32 func_801839A4(s32 a0, s32 a1); /* defined in this TU */
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extern s32 func_80183A98(void *a0); /* defined in this TU */
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extern void func_80183C20(void *a0); /* defined in this TU (return via cast) */
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extern void func_80183D38(void *a0, s16 a1, s32 a2); /* defined in this TU (return via cast) */
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extern void func_80183DA0(s32 a0); /* defined in this TU */
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extern void func_80183F0C(void *a0); /* defined in this TU */
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extern s32 func_8018233C(s32 arg0); /* defined in this TU */
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extern void func_801824CC(s32, s32, s32, s32, s32); /* TU:5009 spelling */
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/* ---- data ---- */
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extern s32 D_801BA5A0; /* TU:5021 */
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extern s32 D_801BA5A2; /* TU:5022 */
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extern s32 D_801BA5A4; /* TU:5023 */
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extern s32 D_801BCBBC; /* TU:5024 */
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extern u8 D_8018E84C[]; /* 16-byte stride, indexed by D_801BCBBC */
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extern u8 D_8018E87C[]; /* 8-byte stride, 3 x s16 vector rows */
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extern u16 *D_801BA594; /* latched row pointer into D_8018E87C */
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void func_801818E8(s32 a0) {
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s32 s0 = a0;
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s32 sp10[3]; /* world-space "to" vector handed to func_8012B77C */
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s32 sp20; /* func_8012B77C output (packed angle pair) */
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s32 t;
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s32 v;
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s32 p;
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switch (*(u16 *)(s0 + 0x34)) {
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case 0:
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*(s16 *)&D_801BA5A4 = 0;
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t = (s32)&D_8018E87C[(rand() & 1) * 8];
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*(s16 *)((s32)sp10 + 0x2) = *(u16 *)(t + 0x0);
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*(s16 *)((s32)sp10 + 0x6) = *(u16 *)(t + 0x2);
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*(s16 *)((s32)sp10 + 0xA) = *(u16 *)(t + 0x4);
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D_801BA594 = (u16 *)t;
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func_8012B77C((s32)&sp20, s0 + 4, (s32)sp10);
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*(s16 *)&D_801BA5A0 = sp20;
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*(s16 *)&D_801BA5A2 = sp20 >> 16;
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func_8018373C((void *)s0, 0xFFFC0000);
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*(u16 *)(s0 + 0x34) += 1;
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break;
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case 1:
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func_8012CBF4(s0);
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if (func_80013478(s0 + 4, (s32)D_801BA594) < 0x101) {
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*(u16 *)(s0 + 0x6) = D_801BA594[0];
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*(u16 *)(s0 + 0xA) = D_801BA594[1];
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*(u16 *)(s0 + 0xE) = D_801BA594[2];
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*(u16 *)(s0 + 0x34) += 1;
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*(s32 *)(s0 + 0x1C) = 0x10;
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*(s16 *)&D_801BA5A0 = 0;
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*(s16 *)&D_801BA5A2 = 0;
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v = ((s32 (*)(void *))func_80183C20)((void *)s0);
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*(s32 *)(s0 + 0xF0) = v;
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*(s16 *)&D_801BA5A4 = v;
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}
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break;
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case 2:
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v = func_8012B608(*(s16 *)(*(s32 *)(s0 + 0x20) + 0x14), *(s32 *)(s0 + 0xF0), 0x8);
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*(u16 *)(*(s32 *)(s0 + 0x20) + 0x14) += v;
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if (func_8012BEE8(s0) != 0) {
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*(s32 *)(s0 + 0x1C) = 0x100;
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*(u16 *)(s0 + 0x34) += 1;
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}
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break;
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case 3:
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func_8018383C(s0, (s32)&D_8018E84C[D_801BCBBC * 16]);
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if (func_80183A98((void *)s0) == 1 && D_801BCBBC == 2) {
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p = ((s32 (*)(void *, s16, s32))func_80183D38)((void *)s0, 0, 0);
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if (p != 0) {
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*(u16 *)(p + 0xA) += 0x20;
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}
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}
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v = func_8012B608(*(s16 *)(*(s32 *)(s0 + 0x20) + 0x14), *(s32 *)(s0 + 0xF0), 0x10);
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*(u16 *)(*(s32 *)(s0 + 0x20) + 0x14) += v;
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*(s16 *)&D_801BA5A4 = *(s32 *)(s0 + 0xF0);
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if (func_8012BEE8(s0) != 0) {
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*(s32 *)(s0 + 0xF0) = 0;
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*(s32 *)(s0 + 0x1C) = 0x10;
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*(u16 *)(s0 + 0x34) += 1;
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*(s16 *)&D_801BA5A4 = 0;
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sp10[0] = 0xFFF80000;
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sp10[1] = 0xFE5E0000;
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sp10[2] = 0xFE380000;
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func_8012B77C((s32)&sp20, s0 + 4, (s32)sp10);
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*(s16 *)&D_801BA5A0 = sp20;
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*(s16 *)&D_801BA5A2 = sp20 >> 16;
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func_8018373C((void *)s0, 0xFFFC0000);
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}
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break;
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case 4:
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v = func_8012B608(*(s16 *)(*(s32 *)(s0 + 0x20) + 0x14), *(s32 *)(s0 + 0xF0), 0x8);
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*(u16 *)(*(s32 *)(s0 + 0x20) + 0x14) += v;
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func_8012CBF4(s0);
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sp10[0] = 0xFFF80000;
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sp10[1] = 0xFE5E0000;
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sp10[2] = 0xFE380000;
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if (func_80013350(s0 + 4, (s32)sp10) < 0x41) {
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func_80183F0C((void *)s0);
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*(s32 *)(s0 + 0x4) = 0xFFF80000;
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*(s32 *)(s0 + 0x8) = 0xFE5E0000;
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*(s32 *)(s0 + 0xC) = 0xFE380000;
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return;
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}
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break;
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}
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func_80183DA0(s0);
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func_801824CC(s0, 0x1800, 0, -0x20, 0xA00000);
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func_801839A4(s0, 0x30);
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func_8018233C(s0);
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}
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