mirror of
https://github.com/Druthulu/BFM-decomp
synced 2026-09-28 06:49:47 -04:00
feat(phase-29): ALL THREE BEHEMOTHS BANKED — func_80183814 (5,122), func_8017DC1C (1,518), func_8017D2DC (1,586)
Zero functions >1000 ins remain unmatched anywhere in the fleet. func_80183814 (5,122 ins — the LARGEST function in the game) — round 2 closed it: length 5127->5122 exact, structural residual 36->0, register-sensitive 1201->0, frame -256 -> -0xF8 exact, saves 10 -> .mask 0x807f0000 exact. Verified independently (R14): match_one MATCH (5122 ins). ROUND 1's DIAGNOSIS WAS WRONG and the agent refuted it properly: the +5 length was a SYMPTOM, not the lever, and the §83d max_reg/cse.c:8340 story does not hold — a 15-line reproducer reproduced the case-0/3 CSE exactly (so it cannot be max_reg-gated), max_qty only gates extension ACROSS blocks, and the target leaves $s7/$fp unused (no pressure story). Confirmed from a second direction: C01 has the identical two groups over the identical symbols with ZERO residual, because a `break` puts a CODE_LABEL between them. The two biggest levers were pure DECLARATION SCOPE (§45/§76), not pins. func_8017DC1C (1,518) — MATCH first round, pin-free, zero __asm__ dials. NOT a jr fn (0 mid-fn jr). func_8017D2DC (1,586) — MATCH first round (banked in the previous commit). BANKING ORDER MATTERS — a new failure mode found and worked around: banking func_8017DC1C BEFORE the carve chain broke the build. Its draft establishes the canon for 39 previously-undeclared externs; jr_isolate_all's re-partition (overlay_src_split) then DROPPED ALL 39 across the new split boundary (`D_801C1EB0 undeclared`), leaving them in NEITHER file. The §77 preamble-drop class, in a third tool. FIX = ordering, not patching: run the §81 carve chain FIRST on a clean tree (gated BYTE-IDENTICAL), then bank. Reverted, re-sequenced, both banked clean. R22 clean-fleet 140/140 BYTE-IDENTICAL; tools-health OK; dedup 1886/0; 0 NON_MATCHING (G4). Fleet: instr 81.6 -> 81.7% · distinct-code 69.1 -> 69.3% · fn-count 89.52%.
This commit is contained in:
Drew T
+1
-1
@@ -3639,7 +3639,7 @@ ov_SC07_006_ELF := $(ov_SC07_006_OUT).elf
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ov_SC07_006_MAPFILE := $(ov_SC07_006_OUT).map
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ov_SC07_006_LD_SCRIPT := $(ov_SC07_006_OUT).ld
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ov_SC07_006_SPLAT_YAML := config/splat.ov_SC07_006.yaml
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ov_SC07_006_JTBL_INTERLEAVE := --order tail.data.o,ov_SC07_006.o,tail2.data.o,ov_SC07_006_jr_80131340.o,tail3.data.o,ov_SC07_006_jr_80135888.o,tail4.data.o,ov_SC07_006_jr_80135A4C.o,tail5.data.o,ov_SC07_006_jr_80135D20.o,tail6.data.o,ov_SC07_006_jr_8013F350.o,tail7.data.o,ov_SC07_006_jr_80140608.o,tail8.data.o,ov_SC07_006_jr_80154C24.o,ov_SC07_006_jr_801588CC.o,tail9.data.o,ov_SC07_006_jr_8015C32C.o,tail10.data.o,ov_SC07_006_jr_8017AE2C.o,ov_SC07_006_jr_8017BEBC.o,tail11.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve
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ov_SC07_006_JTBL_INTERLEAVE := --order tail.data.o,ov_SC07_006.o,tail2.data.o,ov_SC07_006_jr_80131340.o,tail3.data.o,ov_SC07_006_jr_80135888.o,tail4.data.o,ov_SC07_006_jr_80135A4C.o,tail5.data.o,ov_SC07_006_jr_80135D20.o,tail6.data.o,ov_SC07_006_jr_8013F350.o,tail7.data.o,ov_SC07_006_jr_80140608.o,tail8.data.o,ov_SC07_006_jr_80154C24.o,ov_SC07_006_jr_801588CC.o,tail9.data.o,ov_SC07_006_jr_8015C32C.o,tail10.data.o,ov_SC07_006_jr_8017AE2C.o,ov_SC07_006_jr_8017BEBC.o,tail11.data.o,ov_SC07_006_jr_80183814.o,tail12.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve
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build/src/ov_SC07_006/ov_SC07_006_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20
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build/src/ov_SC07_006/ov_SC07_006_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24
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build/src/ov_SC07_006/ov_SC07_006_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28
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@@ -105,6 +105,7 @@ segments:
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- [0x341d4, c, ov_SC07_006_jr_8015C32C]
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- [0x52cd4, c, ov_SC07_006_jr_8017AE2C]
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- [0x53d64, c, ov_SC07_006_jr_8017BEBC]
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- [0x5b6bc, c, ov_SC07_006_jr_80183814]
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- [0x62268, data, tail]
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- [0xcba20, .rodata, ov_SC07_006] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
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- [0xcba34, data, tail2]
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@@ -128,6 +129,8 @@ segments:
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- [0xccb40, .rodata, ov_SC07_006_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
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- [0xccb54, .rodata, ov_SC07_006_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
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- [0xccb74, data, tail11]
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- [0xccb8c, .rodata, ov_SC07_006_jr_80183814] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
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- [0xccbe0, data, tail12]
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- [0xCE214, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word)
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- [0xCE217] # EOF marker = the 0.4.dec byte length
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# @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes
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@@ -4,17 +4,17 @@
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# cross-binary collapsible-byte leverage: docs/duplicates.cross.md.
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# THREE progress metrics (all matter — see the labels):
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FLEET fn-count byte-ident: 316656 / 353719 = 89.52% (REAL+LINKED+empties; FUNCTION-count, ×134-inflated — one crack counts per overlay)
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FLEET instr-weighted : 10729648 / 13141652 = 81.6% (shipped .text across main + resident + 138 overlays; the decomp.dev-DISPLAY number)
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FLEET distinct-code(uniq): 3895626 / 5634875 = 69.1% (65197/87459 unique fns; the DISTINCT-RE number)
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FLEET fn-count byte-ident: 316659 / 353720 = 89.52% (REAL+LINKED+empties; FUNCTION-count, ×134-inflated — one crack counts per overlay)
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FLEET instr-weighted : 10736288 / 13141652 = 81.7% (shipped .text across main + resident + 138 overlays; the decomp.dev-DISPLAY number)
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FLEET distinct-code(uniq): 3902266 / 5634875 = 69.3% (65199/87459 unique fns; the DISTINCT-RE number)
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MAIN game-code weighted : 436 / 60201 = 0.7% (INCLUDED in the fleet numbers above since 2026-07-22 — roadmap §1 metrics contract; LINKED-excluding Ghidra sig dated 2026-06-14; caveat is R34: no independent second oracle for a PS-X EXE, NOT drift)
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(fleet EXCLUDING main, for continuity with pre-2026-07-22 readings: 10729212 / 13081451 = 82.0%)
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(fleet EXCLUDING main, for continuity with pre-2026-07-22 readings: 10735852 / 13081451 = 82.1%)
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FLEET REAL substantive : 314801 (of which dedup-shared 239530 via 1886 groups / 239604 instances)
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FLEET REAL substantive : 314804 (of which dedup-shared 239530 via 1886 groups / 239604 instances)
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FLEET LINKED PsyQ objs : 959
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FLEET NON_MATCHING : 7 (0 in any default build — G4)
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FLEET INCLUDE_ASM stubs : 37056
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FLEET matchable : 353719
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FLEET INCLUDE_ASM stubs : 37054
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FLEET matchable : 353720
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| binary | REAL | shared | LINKED | byte-ident | matchable | byte-ident % |
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|---|---:|---:|---:|---:|---:|---:|
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@@ -152,7 +152,7 @@ FLEET matchable : 353719
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| ov_SC07_000 | 2279 | 1742 | 0 | 2281 | 2521 | 90.5% |
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| ov_SC07_001 | 2263 | 1738 | 0 | 2265 | 2454 | 92.3% |
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| ov_SC07_002 | 2291 | 1738 | 0 | 2295 | 2579 | 89.0% |
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| ov_SC07_006 | 2061 | 1555 | 0 | 2141 | 2455 | 87.2% |
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| ov_SC07_006 | 2064 | 1555 | 0 | 2144 | 2456 | 87.3% |
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| ov_SC07_007 | 2058 | 1586 | 0 | 2142 | 2613 | 82.0% |
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| ov_SC07_008 | 2248 | 1738 | 0 | 2248 | 2386 | 94.2% |
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| ov_SC07_009 | 2257 | 1738 | 0 | 2259 | 2430 | 93.0% |
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@@ -3777,7 +3777,216 @@ INCLUDE_ASM("asm/ov_SC07_006/nonmatchings/ov_SC07_006_jr_8017BEBC", func_8017D8A
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INCLUDE_ASM("asm/ov_SC07_006/nonmatchings/ov_SC07_006_jr_8017BEBC", func_8017DA30);
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INCLUDE_ASM("asm/ov_SC07_006/nonmatchings/ov_SC07_006_jr_8017BEBC", func_8017DC1C);
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/* func_8017DC1C @ ov_SC07_006 (subseg ov_SC07_006_jr_8017BEBC) — behemoth #8, 1,518 ins.
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*
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* GATE: .venv/bin/python tools/match_one.py func_8017DC1C \
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* --c .run/giants/s21_func_8017DC1C_b1.c \
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* --asm-subdir asm/ov_SC07_006/nonmatchings/ov_SC07_006_jr_8017BEBC
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* => MATCH (1518 ins) [pin-free; run through the §77 probe copy,
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* see "PROBE" below — SVECTOR2 is a SHARED type]
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*
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* NOT BANKED. match_one masks jal/HI16/LO16 and never links. Independently checked
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* here (the three things match_one is blind to):
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* §81 0 `jr $vX` — no jump table, NO carve chain needed. (`jr $ra` only.)
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* §84 0 `%lo(SYM+N)` in the emitted asm — no derived offsets.
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* §87 all 64 D_ symbols resolve as dlabels in asm/ov_SC07_006/data/tail.data.s.
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*
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* PROBE (§77): SVECTOR2 lives in src/shared/engine_types.h, which match_one cannot see
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* (-Iinclude only). Gate through:
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* { echo '#include "common.h"';
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* echo '#include "../src/shared/engine_types.h"';
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* cat this_file; } > probe.c
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* The include is deliberately NOT in this file: the real TU
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* src/ov_SC07_006/ov_SC07_006_jr_8017BEBC.c already reaches engine_types.h via
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* `#include "../shared/engine_core.h"`, so adding it here would be a double include.
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*
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* ------------------------------------------------------------------ what it is
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* A morph/keyframe blender. 25 statements, each interpolating one model's vertex
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* block from keyframe `b` toward keyframe `a` by the 1.12 fixed-point factor `t`.
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* ZERO `jal`: the 25 statements are 25 expansions of ONE `static inline` helper.
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*
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* ------------------------------------------------------------------ the levers
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* L1 `static inline`, NOT a macro and NOT an out-of-line static. THE structural
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* lever. What each piece of evidence actually proves — stated honestly:
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* (a) 0 jal + 25 byte-identical 60-ins bodies => the body is EXPANDED in
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* place 25 times, not called. Rules out the out-of-line `static`
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* (measured: func_8017DC1C collapses to 199 ins, 25 real calls).
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* (b) FRAME 0x258 = 600 = 25 * 24. Each expansion of the body's block-scope
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* locals gets its OWN 24 bytes of frame (measured: 1 body = 24,
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* 2 expansions = 48, 25 = 600). This confirms 25 in-place expansions
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* and means the frame is FREE — no padding hack is needed. It does NOT
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* discriminate inline-vs-macro: the macro spelling ALSO frames 600.
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* (c) the DISCRIMINATOR is the instruction count. `static inline` = 1518
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* (MATCH); the equivalent macro = 1537 (+19, LENGTH-DRIFT). Do not
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* "simplify" this into a macro.
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* (d) the `addu $a3,$a2,$zero` in the same-symbol blocks (1,2,3,4,8,9,10,11,
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* 15,16) is integrate.c's copy_to_mode_reg of the SECOND argument after
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* cse folded the two identical global loads into one register.
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* L2 the body assigns the two pointer PARAMS to LOCALS (`pb = b; pa = a;`) and
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* walks the locals. Incrementing the params directly loses BOTH preheader
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* moves (`addu $t2,$a3,$zero` / `addu $t0,$a2,$zero`): with the params readonly
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* the arg reg and the loop biv are one pseudo and combine folds the copy into
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* the load. 2 moves x 25 blocks = 50 ins.
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* L3 `i = o->n;` is read BEFORE the two copies. Source order here survives into
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* the schedule: the target fills the `lw $t3,0x10($a1)` load-delay with the
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* `pb` copy and the `beqz` delay with the `pa` copy. With the copies first,
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* the count load needs a `nop` AND the reorg pass steals the `pb` copy into
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* the `j` delay slot (which the target leaves as `nop`).
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* L4 increment order `d++; pb++; pa++;` — the reverse of the read order.
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* loop.c PREPENDS each biv to loop_iv_list, so the preheader giv-init order
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* (`$a3=pa+4`, `$a2=pb+4`, `$a1=d+4`) is the reverse of the increment order.
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* All 6 permutations measured; this is the only one that puts the three
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* `+4` givs in the target's registers. See the report's table.
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* L5 the else-branch is INDEX arithmetic, not a mask: `(u32 *)&o->dst + (o->dst >> 2)`
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* gives `srl 2; sll 2; addiu 0xC; addu` — 4 separate insns. `o->dst & ~3`
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* would collapse to a single `andi 0xfffc`. `dst` must be UNSIGNED (`srl`, not `sra`).
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* L6 `o->mode == 1` is a literal and stays one: an EQUALITY test has no `slti`
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* form on MIPS, so the 1 is always materialised (`addiu $vX,$zero,1`). The
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* §78/`slti` literal-position law does NOT apply to `==` — do not "fix" this
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* into a variable.
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*
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* Drop-one ablations (all on the b1 base, all measured) — see s21_8017DC1C_report.md.
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*/
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/* ---- the object ---------------------------------------------------------- *
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* mode == 1 : `dst` (+0x0C) is a POINTER to the vertex block.
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* otherwise : the vertex block is INLINE and `dst` is a byte count; the data
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* starts at ((u32 *)&o->dst)[o->dst >> 2].
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* `n` (+0x10) is the vertex count either way. */
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typedef struct {
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s32 unk0; /* 0x00 */
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s32 mode; /* 0x04 */
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s32 unk8; /* 0x08 */
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u32 dst; /* 0x0C */
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s32 n; /* 0x10 */
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} Morph_8017DC1C;
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/* ---- per-overlay globals (ov_SC07_006 tail.data) ------------------------- *
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* Every one of these is an initialised POINTER word in asm/ov_SC07_006/data/
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* tail.data.s (e.g. D_801BF4F4 = .word D_801AD4DC, D_801C1E14 = .word D_801BFD0C).
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* None of them is declared anywhere in the tree today — these spellings are free
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* choices and establish the canon. */
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extern Morph_8017DC1C *D_801BF4F4;
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extern Morph_8017DC1C *D_801BF4F8;
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extern Morph_8017DC1C *D_801BF4FC;
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extern Morph_8017DC1C *D_801BF500;
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extern Morph_8017DC1C *D_801BF504;
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extern Morph_8017DC1C *D_801BF508;
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extern Morph_8017DC1C *D_801BF50C;
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extern Morph_8017DC1C *D_801BF510;
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extern Morph_8017DC1C *D_801BF514;
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extern Morph_8017DC1C *D_801BF518;
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extern Morph_8017DC1C *D_801BF51C;
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extern Morph_8017DC1C *D_801BF520;
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extern Morph_8017DC1C *D_801BF524;
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extern Morph_8017DC1C *D_801BF528;
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extern Morph_8017DC1C *D_801BF52C;
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extern Morph_8017DC1C *D_801BF530;
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extern Morph_8017DC1C *D_801BF534;
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extern Morph_8017DC1C *D_801BF538;
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extern Morph_8017DC1C *D_801BF650;
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extern Morph_8017DC1C *D_801BF65C;
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extern Morph_8017DC1C *D_801BF660;
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extern Morph_8017DC1C *D_801BF684;
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extern Morph_8017DC1C *D_801BF6A4;
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extern Morph_8017DC1C *D_801BF6A8;
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extern Morph_8017DC1C *D_801BF6AC;
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extern SVECTOR2 *D_801C1E14;
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extern SVECTOR2 *D_801C1E18;
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extern SVECTOR2 *D_801C1E1C;
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extern SVECTOR2 *D_801C1E20;
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extern SVECTOR2 *D_801C1E24;
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extern SVECTOR2 *D_801C1E28;
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extern SVECTOR2 *D_801C1E2C;
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extern SVECTOR2 *D_801C1E30;
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extern SVECTOR2 *D_801C1E34;
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extern SVECTOR2 *D_801C1E38;
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extern SVECTOR2 *D_801C1E3C;
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extern SVECTOR2 *D_801C1E40;
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extern SVECTOR2 *D_801C1E44;
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extern SVECTOR2 *D_801C1E48;
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extern SVECTOR2 *D_801C1E4C;
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extern SVECTOR2 *D_801C1E50;
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extern SVECTOR2 *D_801C1E54;
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extern SVECTOR2 *D_801C1E58;
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extern SVECTOR2 *D_801C1E60;
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extern SVECTOR2 *D_801C1E64;
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extern SVECTOR2 *D_801C1E68;
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extern SVECTOR2 *D_801C1E6C;
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extern SVECTOR2 *D_801C1E70;
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extern SVECTOR2 *D_801C1E74;
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extern SVECTOR2 *D_801C1E78;
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extern SVECTOR2 *D_801C1E7C;
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extern SVECTOR2 *D_801C1E80;
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extern SVECTOR2 *D_801C1E84;
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extern SVECTOR2 *D_801C1E88;
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extern SVECTOR2 *D_801C1E8C;
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extern SVECTOR2 *D_801C1E90;
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extern SVECTOR2 *D_801C1E94;
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extern SVECTOR2 *D_801C1E98;
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extern SVECTOR2 *D_801C1E9C;
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extern SVECTOR2 *D_801C1EA0;
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extern SVECTOR2 *D_801C1EA4;
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extern SVECTOR2 *D_801C1EA8;
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extern SVECTOR2 *D_801C1EAC;
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extern SVECTOR2 *D_801C1EB0;
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/* MUST be `inline` — see L1. 25 expansions == 1518 ins, 0 jal, frame 25*24=0x258. */
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static inline void morph_lerp(Morph_8017DC1C *o, SVECTOR2 *b, SVECTOR2 *a, s32 t)
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{
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SVECTOR2 *d;
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SVECTOR2 *pa;
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SVECTOR2 *pb;
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s32 i;
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if (o->mode == 1) {
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d = (SVECTOR2 *)o->dst;
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} else {
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d = (SVECTOR2 *)((u32 *)&o->dst + (o->dst >> 2));
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}
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i = o->n; /* L3: before the copies */
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pb = b; /* L2 */
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pa = a; /* L2 */
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for (; i != 0; i--) {
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d->vx = pb->vx + (((pa->vx - pb->vx) * t) >> 12);
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d->vy = pb->vy + (((pa->vy - pb->vy) * t) >> 12);
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d->vz = pb->vz + (((pa->vz - pb->vz) * t) >> 12);
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d++; /* L4: reverse of the read order */
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pb++;
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pa++;
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}
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}
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void func_8017DC1C(s32 t)
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{
|
||||
morph_lerp(D_801BF4F4, D_801C1E14, D_801C1E18, t);
|
||||
morph_lerp(D_801BF4F8, D_801C1E1C, D_801C1E1C, t);
|
||||
morph_lerp(D_801BF4FC, D_801C1E20, D_801C1E20, t);
|
||||
morph_lerp(D_801BF500, D_801C1E24, D_801C1E24, t);
|
||||
morph_lerp(D_801BF504, D_801C1E28, D_801C1E28, t);
|
||||
morph_lerp(D_801BF508, D_801C1E40, D_801C1E50, t);
|
||||
morph_lerp(D_801BF50C, D_801C1E44, D_801C1E54, t);
|
||||
morph_lerp(D_801BF510, D_801C1E48, D_801C1E58, t);
|
||||
morph_lerp(D_801BF514, D_801C1E4C, D_801C1E4C, t);
|
||||
morph_lerp(D_801BF518, D_801C1E60, D_801C1E60, t);
|
||||
morph_lerp(D_801BF51C, D_801C1E64, D_801C1E64, t);
|
||||
morph_lerp(D_801BF520, D_801C1E68, D_801C1E68, t);
|
||||
morph_lerp(D_801BF524, D_801C1E80, D_801C1E90, t);
|
||||
morph_lerp(D_801BF528, D_801C1E84, D_801C1E94, t);
|
||||
morph_lerp(D_801BF52C, D_801C1E88, D_801C1E98, t);
|
||||
morph_lerp(D_801BF530, D_801C1E8C, D_801C1E8C, t);
|
||||
morph_lerp(D_801BF534, D_801C1E9C, D_801C1E9C, t);
|
||||
morph_lerp(D_801BF538, D_801C1EA0, D_801C1EA4, t);
|
||||
morph_lerp(D_801BF650, D_801C1EA4, D_801C1EA8, t);
|
||||
morph_lerp(D_801BF65C, D_801C1E2C, D_801C1E38, t);
|
||||
morph_lerp(D_801BF660, D_801C1E30, D_801C1E3C, t);
|
||||
morph_lerp(D_801BF684, D_801C1EAC, D_801C1E34, t);
|
||||
morph_lerp(D_801BF6A4, D_801C1E6C, D_801C1E78, t);
|
||||
morph_lerp(D_801BF6A8, D_801C1E70, D_801C1E7C, t);
|
||||
morph_lerp(D_801BF6AC, D_801C1E74, D_801C1EB0, t);
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC07_006/nonmatchings/ov_SC07_006_jr_8017BEBC", func_8017F3D4);
|
||||
|
||||
@@ -3824,112 +4033,3 @@ INCLUDE_ASM("asm/ov_SC07_006/nonmatchings/ov_SC07_006_jr_8017BEBC", func_80182D4
|
||||
INCLUDE_ASM("asm/ov_SC07_006/nonmatchings/ov_SC07_006_jr_8017BEBC", func_80182F3C);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC07_006/nonmatchings/ov_SC07_006_jr_8017BEBC", func_80183374);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC07_006/nonmatchings/ov_SC07_006_jr_8017BEBC", func_80183814);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC07_006/nonmatchings/ov_SC07_006_jr_8017BEBC", func_8018881C);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC07_006/nonmatchings/ov_SC07_006_jr_8017BEBC", func_80189098);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC07_006/nonmatchings/ov_SC07_006_jr_8017BEBC", func_801890FC);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC07_006/nonmatchings/ov_SC07_006_jr_8017BEBC", func_80189708);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC07_006/nonmatchings/ov_SC07_006_jr_8017BEBC", func_8018984C);
|
||||
|
||||
|
||||
|
||||
void func_80189AC8(void *a0) {
|
||||
|
||||
extern void (*D_8018EB2C[])(void);
|
||||
D_8018EB2C[*(u16 *)((s32)a0 + 0x2)]();
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
void func_80189B04(void *a0) {
|
||||
|
||||
extern void (*D_8018EB44[])(void);
|
||||
D_8018EB44[*(u16 *)((s32)a0 + 0x2)]();
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC07_006/nonmatchings/ov_SC07_006_jr_8017BEBC", func_80189B40);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC07_006/nonmatchings/ov_SC07_006_jr_8017BEBC", func_80189C00);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC07_006/nonmatchings/ov_SC07_006_jr_8017BEBC", func_80189C14);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC07_006/nonmatchings/ov_SC07_006_jr_8017BEBC", func_80189C28);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC07_006/nonmatchings/ov_SC07_006_jr_8017BEBC", func_80189C3C);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC07_006/nonmatchings/ov_SC07_006_jr_8017BEBC", func_80189C50);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC07_006/nonmatchings/ov_SC07_006_jr_8017BEBC", func_80189C64);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC07_006/nonmatchings/ov_SC07_006_jr_8017BEBC", func_80189C78);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC07_006/nonmatchings/ov_SC07_006_jr_8017BEBC", func_80189C8C);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC07_006/nonmatchings/ov_SC07_006_jr_8017BEBC", func_80189CA0);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC07_006/nonmatchings/ov_SC07_006_jr_8017BEBC", func_80189CB4);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC07_006/nonmatchings/ov_SC07_006_jr_8017BEBC", func_80189CC8);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC07_006/nonmatchings/ov_SC07_006_jr_8017BEBC", func_80189CDC);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC07_006/nonmatchings/ov_SC07_006_jr_8017BEBC", func_80189CF0);
|
||||
|
||||
extern void func_8017D040(s8 a0);
|
||||
void func_80189D18(void) {
|
||||
func_8017D040(0);
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC07_006/nonmatchings/ov_SC07_006_jr_8017BEBC", func_80189D38);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC07_006/nonmatchings/ov_SC07_006_jr_8017BEBC", func_80189D58);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC07_006/nonmatchings/ov_SC07_006_jr_8017BEBC", func_80189D78);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC07_006/nonmatchings/ov_SC07_006_jr_8017BEBC", func_80189D98);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC07_006/nonmatchings/ov_SC07_006_jr_8017BEBC", func_80189DB8);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC07_006/nonmatchings/ov_SC07_006_jr_8017BEBC", func_80189EF4);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC07_006/nonmatchings/ov_SC07_006_jr_8017BEBC", func_80189F70);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC07_006/nonmatchings/ov_SC07_006_jr_8017BEBC", func_80189FDC);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC07_006/nonmatchings/ov_SC07_006_jr_8017BEBC", func_8018A124);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC07_006/nonmatchings/ov_SC07_006_jr_8017BEBC", func_8018A150);
|
||||
|
||||
void func_8018A284(void) {
|
||||
}
|
||||
|
||||
|
||||
|
||||
void func_8018A28C(void *a0) {
|
||||
|
||||
extern void (*D_8018EB54[])(void);
|
||||
D_8018EB54[*(u16 *)((s32)a0 + 0x2)]();
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
extern s32 func_8012AD50(void *a0);
|
||||
void func_8018A2C8(u8 *a0) {
|
||||
*(s16 *)(a0 + 0xFC) = 0;
|
||||
*(u16 *)(a0 + 0x72) |= 0x1000;
|
||||
((void (*)(void))func_8012AD50)();
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC07_006/nonmatchings/ov_SC07_006_jr_8017BEBC", func_8018A2F4);
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user