feat(phase-23): map-wave gate — +1 fns x0 propagated (fleet 64.86%)

This commit is contained in:
Drew T
2026-07-02 21:19:07 -06:00
parent 3b6f2c5f94
commit da4eb3ff6c
+72 -1
View File
@@ -1458,7 +1458,78 @@ void func_80144054(void *a0)
D_801884B0[*(u16 *)((s32)a0 + 0x2)](a0);
}
INCLUDE_ASM("asm/ov_SC01_077/nonmatchings/ov_SC01_077", func_80144090);
// @class: regalloc-order
// @stuck: 154/154 ins structural match (callees/consts/ctrl-flow/stack/GPU-packet all byte-correct); residual 25 = caller-saved temp-reg coalescing in the final ring-vertex block (target reuses dead $s0=iVar3 for iVar3-(iVar4>>6) subu where gcc reuses iVar4>>6's reg; iVar4 mflo -> $a3 vs target $v0) + 2-ins schedule swap of giv-increment vs iVar2*4 -> permuter grinder territory (§27 step-5)
typedef struct { s32 a; s32 b[4]; } OtBlk; /* 0x14 stride */
extern void *func_80010A08(s32);
extern void func_8004914C(void *a0);
extern void func_800491AC(void *a0);
extern s32 RotTransPers(s32, s32, s32 *, s32 *);
extern s32 func_8004787C(s32 a0);
extern s32 func_80047948(s32 a0);
extern s32 AddPrim(s32, void *);
extern OtBlk D_800A651C[];
extern u8 D_800AF648;
extern short D_800B9A02;
void func_80144090(s32 param_1) {
void *iVar1;
s32 iVar2;
s32 iVar3;
s32 iVar4;
s32 iVar5;
s32 iVar6;
struct {
s16 v10[4];
u16 sxy[2];
s32 p;
s32 flag;
} L;
iVar1 = func_80010A08(0x140);
if (iVar1 != 0) {
*(s32 *)(param_1 + 4) = *(s32 *)(param_1 + 4) + *(s32 *)(param_1 + 0x10);
*(s32 *)(param_1 + 8) = *(s32 *)(param_1 + 8) + *(s32 *)(param_1 + 0x14);
*(s32 *)(param_1 + 0xc) = *(s32 *)(param_1 + 0xc) + *(s32 *)(param_1 + 0x18);
L.v10[0] = *(u16 *)(param_1 + 6);
L.v10[1] = *(u16 *)(param_1 + 0xa);
L.v10[2] = *(u16 *)(param_1 + 0xe);
func_8004914C(&D_800AF648);
func_800491AC(&D_800AF648);
iVar2 = RotTransPers((s32)L.v10, (s32)L.sxy, &L.p, &L.flag);
iVar2 = iVar2 + 4;
if (iVar2 < 0) {
iVar2 = 0;
}
iVar6 = 0;
do {
*(s32 *)((u8 *)iVar1 + 4) = 0xffffff;
*(u8 *)((u8 *)iVar1 + 3) = 4;
*(u8 *)((u8 *)iVar1 + 7) = 0x20;
if (*(s32 *)(param_1 + 0x1c) - 6 < 1) {
*(s16 *)((u8 *)iVar1 + 8) = L.sxy[0];
*(s16 *)((u8 *)iVar1 + 0xa) = L.sxy[1];
} else {
iVar5 = func_8004787C(iVar6);
*(s16 *)((u8 *)iVar1 + 8) = L.sxy[0] + ((iVar5 * ((*(s32 *)(param_1 + 0x1c) - 6) << 4)) >> 0xc);
iVar5 = func_80047948(iVar6);
*(s16 *)((u8 *)iVar1 + 0xa) = L.sxy[1] + ((iVar5 * ((*(s32 *)(param_1 + 0x1c) - 6) << 4)) >> 0xc);
}
iVar3 = func_8004787C(iVar6) * (*(s32 *)(param_1 + 0x1c) << 4);
iVar4 = func_80047948(iVar6) * (*(s32 *)(param_1 + 0x1c) << 4);
iVar6 = iVar6 + 0x100;
*(s16 *)((u8 *)iVar1 + 0x10) = L.sxy[0] + ((iVar3 + (iVar4 >> 6)) >> 0xc);
*(s16 *)((u8 *)iVar1 + 0x12) = L.sxy[1] + ((iVar4 + (iVar3 >> 6)) >> 0xc);
*(s16 *)((u8 *)iVar1 + 0xc) = L.sxy[0] + ((iVar3 - (iVar4 >> 6)) >> 0xc);
*(s16 *)((u8 *)iVar1 + 0xe) = L.sxy[1] + ((iVar4 - (iVar3 >> 6)) >> 0xc);
AddPrim(D_800A651C[(u16)D_800B9A02].a + (iVar2 * 4), iVar1);
iVar1 = (u8 *)iVar1 + 0x14;
} while (iVar6 < 0x1000);
}
}
// @class: struct
// @stuck: none — MATCH (relocation-masked match_one); fn-ptr dispatch table + 0x1c counter, sibling idiom (func_801427EC/func_80143B30)