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feat(phase-30 S48-0b): jtbl family func_8017AE2C — 2/2 blocked-binary siblings banked

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Drew T
2026-08-11 15:53:52 -06:00
parent 98d834ebf7
commit dda26a3ea9
5 changed files with 202 additions and 6 deletions
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config/overlays.mk
+2 -2
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@@ -4921,7 +4921,7 @@ build/src/ov_MAIN_012/ov_MAIN_012_jr_80131340.o: JTBL_PADS := 0,0,4 # §8e pads
build/src/ov_MAIN_012/ov_MAIN_012_jr_80135A4C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18
build/src/ov_MAIN_012/ov_MAIN_012_jr_8013F350.o: JTBL_PADS := 0,0,4,0,4,0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58,+0x70,+0x90,+0xa8
build/src/ov_MAIN_012/ov_MAIN_012_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20
build/src/ov_MAIN_012/ov_MAIN_012_jr_801789AC.o: JTBL_PADS := 0,0,0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18,+0x190,+0x220
build/src/ov_MAIN_012/ov_MAIN_012_jr_801789AC.o: JTBL_PADS := 0,0,0,4,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18,+0x190,+0x220,+0x2b0
ov_MAIN_012_CHECK_SHA := config/check.ov_MAIN_012.sha
ov_MAIN_012_SYMBOLS := config/symbols.ov_MAIN_012.txt
ov_MAIN_012_SIG := .run/sig.ov_MAIN_012.jsonl
@@ -4978,7 +4978,7 @@ build/src/ov_SC03_107/ov_SC03_107_jr_80131340.o: JTBL_PADS := 0,0,4 # §8e pads
build/src/ov_SC03_107/ov_SC03_107_jr_80135A4C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18
build/src/ov_SC03_107/ov_SC03_107_jr_8013F350.o: JTBL_PADS := 0,0,4,0,4,0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58,+0x70,+0x90,+0xa8
build/src/ov_SC03_107/ov_SC03_107_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20
build/src/ov_SC03_107/ov_SC03_107_jr_801789AC.o: JTBL_PADS := 0,0,0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18,+0x190,+0x220
build/src/ov_SC03_107/ov_SC03_107_jr_801789AC.o: JTBL_PADS := 0,0,0,4,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18,+0x190,+0x220,+0x2b0
ov_SC03_107_CHECK_SHA := config/check.ov_SC03_107.sha
ov_SC03_107_SYMBOLS := config/symbols.ov_SC03_107.txt
ov_SC03_107_SIG := .run/sig.ov_SC03_107.jsonl
config/splat.ov_MAIN_012.yaml
+1 -1
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@@ -125,7 +125,7 @@ segments:
- [0x5b768, .rodata, ov_MAIN_012_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
- [0x5b784, data, tail10]
- [0x5ba40, .rodata, ov_MAIN_012_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
- [0x5bcec, data, tail11]
- [0x5bd04, data, tail11]
- [0x5DB24, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word)
- [0x5DB27] # EOF marker = the 0.4.dec byte length
# @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes
config/splat.ov_SC03_107.yaml
+1 -1
View File
@@ -125,7 +125,7 @@ segments:
- [0x71f80, .rodata, ov_SC03_107_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
- [0x71f9c, data, tail10]
- [0x72258, .rodata, ov_SC03_107_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
- [0x72504, data, tail11]
- [0x7251c, data, tail11]
- [0x73BE4, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word)
- [0x73BE7] # EOF marker = the 0.4.dec byte length
# @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes
src/ov_MAIN_012/ov_MAIN_012_jr_801789AC.c
+99 -1
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@@ -4979,7 +4979,105 @@ DEFINE_func_8017ADE8() /* dedup: shared engine-core @0x8017ade8 (src/shared) */
DEFINE_func_8017AE08() /* dedup: shared engine-core @0x8017ae08 (src/shared) */
INCLUDE_ASM("asm/ov_MAIN_012/nonmatchings/ov_MAIN_012_jr_801789AC", func_8017AE2C);
typedef struct { s16 m[3][3]; s32 t[3]; } MTX_C974;
extern s32 func_8012B608(s32 a0, s32 a1, s32 a2);
extern void func_8012B178(s32 a0, s32 a1);
extern void func_8012AD80(s32 a0);
extern s32 func_8012B030(u8 *a0);
extern s32 func_8012B744(void *a0, void *a1);
extern void func_8012BE98(s32, u16*);
extern s32 func_80012A60(s32 a0, s32 a1);
void func_8017AE2C(s32 param_1) {
extern s16 D_80185BD8;
extern s16 D_80185BDA;
extern s16 D_80185BE4;
register s32 pv __asm__("$16") = param_1;
register s16 *g __asm__("$17") = &D_80185BD8;
switch (g[0]) {
case 0:
default:
return;
case 1:
g[1] = (u16)g[1] - 1;
if (g[1] <= 0) {
*(u16 *)(*(s32 *)(pv + 0x20) + 0x12) = (u16)g[2];
goto reset_both;
}
{
s32 r = func_8012B608(*(s16 *)(*(s32 *)(pv + 0x20) + 0x12), g[2], 6);
*(u16 *)(*(s32 *)(pv + 0x20) + 0x12) =
*(u16 *)(*(s32 *)(pv + 0x20) + 0x12) + r;
}
return;
case 2:
func_8012B178(pv, (s32)g[4] << 8);
func_8012AD80(pv);
*(u16 *)(pv + 0xA) -= 8;
func_8012B030((u8 *)pv);
break;
case 3:
if (g[1] != 0) {
if (g[5] != 0) {
void *p = (void *)(pv + 4);
if ((s16)func_80012A60(*(s16 *)(*(s32 *)(pv + 0x20) + 0x12),
(s16)func_8012B744(p, &g[6])) < 0x100) {
g[1] = 0;
}
*(s16 *)(*(s32 *)(pv + 0x20) + 0x12) =
func_8012B744(p, &D_80185BE4);
func_8012B178(pv, 0xFFFA0000);
func_8012AD80(pv);
*(u16 *)(pv + 0xA) -= 8;
func_8012B030((u8 *)pv);
/* &D_80185BD8+0xC == &D_80185BE4; distinct rtx defeats gcc's address-CSE
so BE98's arg rematerializes instead of sharing the store's reg (byte-gate). */
if (((s32 (*)(s32, u16 *))func_8012BE98)(pv, (u16 *)((s32)&D_80185BD8 + 0xC)) < 0x101) {
D_80185BD8 = 0;
D_80185BDA = 0;
}
}
{
s32 t = func_8012B744((void *)(pv + 4), &g[6]);
s32 r = func_8012B608(*(s16 *)(*(s32 *)(pv + 0x20) + 0x12), t, g[3]);
*(u16 *)(*(s32 *)(pv + 0x20) + 0x12) =
*(u16 *)(*(s32 *)(pv + 0x20) + 0x12) + r;
}
g[1] = (u16)g[1] - 1;
if (g[1] > 0) {
return;
}
g[1] = 0;
return;
}
*(s16 *)(*(s32 *)(pv + 0x20) + 0x12) =
func_8012B744((void *)(pv + 4), &D_80185BE4);
func_8012B178(pv, 0xFFFA0000);
func_8012AD80(pv);
*(u16 *)(pv + 0xA) -= 8;
func_8012B030((u8 *)pv);
/* see note above: distinct rtx for the same address defeats address-CSE. */
if (((s32 (*)(s32, u16 *))func_8012BE98)(pv, (u16 *)((s32)&D_80185BD8 + 0xC)) < 0x101) {
D_80185BD8 = 0;
D_80185BDA = 0;
}
return;
case 4:
func_8012AD80(pv);
}
g[1] = (u16)g[1] - 1;
if (g[1] > 0) {
return;
}
reset_both:
g[0] = 0;
g[1] = 0;
return;
}
extern s32 func_80012C6C(s32 a0, s32 a1, s32 a2);
src/ov_SC03_107/ov_SC03_107_jr_801789AC.c
+99 -1
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@@ -4984,7 +4984,105 @@ DEFINE_func_8017ADE8() /* dedup: shared engine-core @0x8017ade8 (src/shared) */
DEFINE_func_8017AE08() /* dedup: shared engine-core @0x8017ae08 (src/shared) */
INCLUDE_ASM("asm/ov_SC03_107/nonmatchings/ov_SC03_107_jr_801789AC", func_8017AE2C);
typedef struct { s16 m[3][3]; s32 t[3]; } MTX_C974;
extern s32 func_8012B608(s32 a0, s32 a1, s32 a2);
extern void func_8012B178(s32 a0, s32 a1);
extern void func_8012AD80(s32 a0);
extern s32 func_8012B030(u8 *a0);
extern s32 func_8012B744(void *a0, void *a1);
extern void func_8012BE98(s32, u16*);
extern s32 func_80012A60(s32 a0, s32 a1);
void func_8017AE2C(s32 param_1) {
extern s16 D_8019BC98;
extern s16 D_8019BC9A;
extern s16 D_8019BCA4;
register s32 pv __asm__("$16") = param_1;
register s16 *g __asm__("$17") = &D_8019BC98;
switch (g[0]) {
case 0:
default:
return;
case 1:
g[1] = (u16)g[1] - 1;
if (g[1] <= 0) {
*(u16 *)(*(s32 *)(pv + 0x20) + 0x12) = (u16)g[2];
goto reset_both;
}
{
s32 r = func_8012B608(*(s16 *)(*(s32 *)(pv + 0x20) + 0x12), g[2], 6);
*(u16 *)(*(s32 *)(pv + 0x20) + 0x12) =
*(u16 *)(*(s32 *)(pv + 0x20) + 0x12) + r;
}
return;
case 2:
func_8012B178(pv, (s32)g[4] << 8);
func_8012AD80(pv);
*(u16 *)(pv + 0xA) -= 8;
func_8012B030((u8 *)pv);
break;
case 3:
if (g[1] != 0) {
if (g[5] != 0) {
void *p = (void *)(pv + 4);
if ((s16)func_80012A60(*(s16 *)(*(s32 *)(pv + 0x20) + 0x12),
(s16)func_8012B744(p, &g[6])) < 0x100) {
g[1] = 0;
}
*(s16 *)(*(s32 *)(pv + 0x20) + 0x12) =
func_8012B744(p, &D_8019BCA4);
func_8012B178(pv, 0xFFFA0000);
func_8012AD80(pv);
*(u16 *)(pv + 0xA) -= 8;
func_8012B030((u8 *)pv);
/* &D_8019BC98+0xC == &D_8019BCA4; distinct rtx defeats gcc's address-CSE
so BE98's arg rematerializes instead of sharing the store's reg (byte-gate). */
if (((s32 (*)(s32, u16 *))func_8012BE98)(pv, (u16 *)((s32)&D_8019BC98 + 0xC)) < 0x101) {
D_8019BC98 = 0;
D_8019BC9A = 0;
}
}
{
s32 t = func_8012B744((void *)(pv + 4), &g[6]);
s32 r = func_8012B608(*(s16 *)(*(s32 *)(pv + 0x20) + 0x12), t, g[3]);
*(u16 *)(*(s32 *)(pv + 0x20) + 0x12) =
*(u16 *)(*(s32 *)(pv + 0x20) + 0x12) + r;
}
g[1] = (u16)g[1] - 1;
if (g[1] > 0) {
return;
}
g[1] = 0;
return;
}
*(s16 *)(*(s32 *)(pv + 0x20) + 0x12) =
func_8012B744((void *)(pv + 4), &D_8019BCA4);
func_8012B178(pv, 0xFFFA0000);
func_8012AD80(pv);
*(u16 *)(pv + 0xA) -= 8;
func_8012B030((u8 *)pv);
/* see note above: distinct rtx for the same address defeats address-CSE. */
if (((s32 (*)(s32, u16 *))func_8012BE98)(pv, (u16 *)((s32)&D_8019BC98 + 0xC)) < 0x101) {
D_8019BC98 = 0;
D_8019BC9A = 0;
}
return;
case 4:
func_8012AD80(pv);
}
g[1] = (u16)g[1] - 1;
if (g[1] > 0) {
return;
}
reset_both:
g[0] = 0;
g[1] = 0;
return;
}
extern s32 func_80012C6C(s32 a0, s32 a1, s32 a2);