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https://github.com/Druthulu/BFM-decomp
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feat(phase-30 S48-T6): propagate func_80188E1C to its zero-crack siblings
This commit is contained in:
Drew T
+4
-4
@@ -129,7 +129,7 @@ ov_SC03_001_ELF := $(ov_SC03_001_OUT).elf
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ov_SC03_001_MAPFILE := $(ov_SC03_001_OUT).map
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ov_SC03_001_LD_SCRIPT := $(ov_SC03_001_OUT).ld
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ov_SC03_001_SPLAT_YAML := config/splat.ov_SC03_001.yaml
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ov_SC03_001_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_001.o,ov_SC03_001_jr_8012ACE0.o,tail2.data.o,ov_SC03_001_jr_80135888.o,tail3.data.o,ov_SC03_001_jr_80135A4C.o,tail4.data.o,ov_SC03_001_jr_80135D20.o,tail5.data.o,ov_SC03_001_jr_801380E0.o,ov_SC03_001_o0c.o,tail6.data.o,ov_SC03_001_jr_8013F350.o,tail7.data.o,ov_SC03_001_jr_8013FFD8.o,tail8.data.o,ov_SC03_001_jr_80140608.o,tail9.data.o,ov_SC03_001_jr_8015444C.o,ov_SC03_001_jr_80154C24.o,ov_SC03_001_jr_801588CC.o,ov_SC03_001_jr_80159C84.o,tail10.data.o,ov_SC03_001_jr_8015A3C8.o,tail11.data.o,ov_SC03_001_jr_8015AE2C.o,tail12.data.o,ov_SC03_001_jr_8015C32C.o,tail13.data.o,ov_SC03_001_jr_8016AB6C.o,tail14.data.o,ov_SC03_001_jr_80171B4C.o,ov_SC03_001_jr_801734BC.o,tail15.data.o,ov_SC03_001_jr_801789AC.o,ov_SC03_001_jr_80178D40.o,tail16.data.o,ov_SC03_001_jr_8017A4AC.o,tail17.data.o,ov_SC03_001_jr_8017AE2C.o,tail18.data.o,ov_SC03_001_jr_80188830.o,tail19.data.o,ov_SC03_001_jr_80189030.o,tail20.data.o,ov_SC03_001_jr_8018A3A8.o,tail21.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve
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ov_SC03_001_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_001.o,ov_SC03_001_jr_8012ACE0.o,tail2.data.o,ov_SC03_001_jr_80135888.o,tail3.data.o,ov_SC03_001_jr_80135A4C.o,tail4.data.o,ov_SC03_001_jr_80135D20.o,tail5.data.o,ov_SC03_001_jr_801380E0.o,ov_SC03_001_o0c.o,tail6.data.o,ov_SC03_001_jr_8013F350.o,tail7.data.o,ov_SC03_001_jr_8013FFD8.o,tail8.data.o,ov_SC03_001_jr_80140608.o,tail9.data.o,ov_SC03_001_jr_8015444C.o,ov_SC03_001_jr_80154C24.o,ov_SC03_001_jr_801588CC.o,ov_SC03_001_jr_80159C84.o,tail10.data.o,ov_SC03_001_jr_8015A3C8.o,tail11.data.o,ov_SC03_001_jr_8015AE2C.o,tail12.data.o,ov_SC03_001_jr_8015C32C.o,tail13.data.o,ov_SC03_001_jr_8016AB6C.o,tail14.data.o,ov_SC03_001_jr_80171B4C.o,ov_SC03_001_jr_801734BC.o,tail15.data.o,ov_SC03_001_jr_801789AC.o,ov_SC03_001_jr_80178D40.o,tail16.data.o,ov_SC03_001_jr_8017A4AC.o,tail17.data.o,ov_SC03_001_jr_8017AE2C.o,tail18.data.o,ov_SC03_001_jr_80188830.o,tail19.data.o,ov_SC03_001_jr_80189030.o,tail20.data.o,ov_SC03_001_jr_8018A3A8.o,tail21.data.o,ov_SC03_001_jr_8018B8DC.o,tail22.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve
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build/src/ov_SC03_001/ov_SC03_001.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14
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build/src/ov_SC03_001/ov_SC03_001_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0
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build/src/ov_SC03_001/ov_SC03_001_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18
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@@ -452,7 +452,7 @@ ov_SC04_019_ELF := $(ov_SC04_019_OUT).elf
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ov_SC04_019_MAPFILE := $(ov_SC04_019_OUT).map
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ov_SC04_019_LD_SCRIPT := $(ov_SC04_019_OUT).ld
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ov_SC04_019_SPLAT_YAML := config/splat.ov_SC04_019.yaml
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ov_SC04_019_JTBL_INTERLEAVE := --order tail.data.o,ov_SC04_019.o,ov_SC04_019_jr_8012ACE0.o,tail2.data.o,ov_SC04_019_jr_80135888.o,tail3.data.o,ov_SC04_019_jr_80135A4C.o,tail4.data.o,ov_SC04_019_jr_80135D20.o,tail5.data.o,ov_SC04_019_jr_801380E0.o,ov_SC04_019_o0c.o,tail6.data.o,ov_SC04_019_jr_8013F350.o,tail7.data.o,ov_SC04_019_jr_8013FFD8.o,tail8.data.o,ov_SC04_019_jr_80140608.o,tail9.data.o,ov_SC04_019_jr_8015444C.o,ov_SC04_019_jr_80154C24.o,ov_SC04_019_jr_801588CC.o,ov_SC04_019_jr_80159C84.o,tail10.data.o,ov_SC04_019_jr_8015A3C8.o,tail11.data.o,ov_SC04_019_jr_8015AE2C.o,tail12.data.o,ov_SC04_019_jr_8015C32C.o,tail13.data.o,ov_SC04_019_jr_8016AB6C.o,tail14.data.o,ov_SC04_019_jr_80171B4C.o,ov_SC04_019_jr_801734BC.o,tail15.data.o,ov_SC04_019_jr_801789AC.o,ov_SC04_019_jr_80178D40.o,tail16.data.o,ov_SC04_019_jr_8017A4AC.o,tail17.data.o,ov_SC04_019_jr_8017AE2C.o,tail18.data.o,ov_SC04_019_jr_80185D70.o,tail19.data.o,ov_SC04_019_jr_801878E8.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve
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ov_SC04_019_JTBL_INTERLEAVE := --order tail.data.o,ov_SC04_019.o,ov_SC04_019_jr_8012ACE0.o,tail2.data.o,ov_SC04_019_jr_80135888.o,tail3.data.o,ov_SC04_019_jr_80135A4C.o,tail4.data.o,ov_SC04_019_jr_80135D20.o,tail5.data.o,ov_SC04_019_jr_801380E0.o,ov_SC04_019_o0c.o,tail6.data.o,ov_SC04_019_jr_8013F350.o,tail7.data.o,ov_SC04_019_jr_8013FFD8.o,tail8.data.o,ov_SC04_019_jr_80140608.o,tail9.data.o,ov_SC04_019_jr_8015444C.o,ov_SC04_019_jr_80154C24.o,ov_SC04_019_jr_801588CC.o,ov_SC04_019_jr_80159C84.o,tail10.data.o,ov_SC04_019_jr_8015A3C8.o,tail11.data.o,ov_SC04_019_jr_8015AE2C.o,tail12.data.o,ov_SC04_019_jr_8015C32C.o,tail13.data.o,ov_SC04_019_jr_8016AB6C.o,tail14.data.o,ov_SC04_019_jr_80171B4C.o,ov_SC04_019_jr_801734BC.o,tail15.data.o,ov_SC04_019_jr_801789AC.o,ov_SC04_019_jr_80178D40.o,tail16.data.o,ov_SC04_019_jr_8017A4AC.o,tail17.data.o,ov_SC04_019_jr_8017AE2C.o,tail18.data.o,ov_SC04_019_jr_80185D70.o,tail19.data.o,ov_SC04_019_jr_801878E8.o,tail20.data.o,ov_SC04_019_jr_80188E1C.o,tail21.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve
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build/src/ov_SC04_019/ov_SC04_019.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14
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build/src/ov_SC04_019/ov_SC04_019_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0
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build/src/ov_SC04_019/ov_SC04_019_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18
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@@ -2864,7 +2864,7 @@ ov_SC03_124_ELF := $(ov_SC03_124_OUT).elf
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ov_SC03_124_MAPFILE := $(ov_SC03_124_OUT).map
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ov_SC03_124_LD_SCRIPT := $(ov_SC03_124_OUT).ld
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ov_SC03_124_SPLAT_YAML := config/splat.ov_SC03_124.yaml
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ov_SC03_124_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_124.o,ov_SC03_124_jr_8012ACE0.o,tail2.data.o,ov_SC03_124_jr_80135888.o,tail3.data.o,ov_SC03_124_jr_80135A4C.o,tail4.data.o,ov_SC03_124_jr_80135D20.o,tail5.data.o,ov_SC03_124_jr_801380E0.o,ov_SC03_124_o0c.o,tail6.data.o,ov_SC03_124_jr_8013F350.o,tail7.data.o,ov_SC03_124_jr_8013FFD8.o,tail8.data.o,ov_SC03_124_jr_80140608.o,tail9.data.o,ov_SC03_124_jr_8015444C.o,ov_SC03_124_jr_80154C24.o,ov_SC03_124_jr_801588CC.o,ov_SC03_124_jr_80159C84.o,tail10.data.o,ov_SC03_124_jr_8015A3C8.o,tail11.data.o,ov_SC03_124_jr_8015AE2C.o,tail12.data.o,ov_SC03_124_jr_8015C32C.o,tail13.data.o,ov_SC03_124_jr_8016AB6C.o,tail14.data.o,ov_SC03_124_jr_80171B4C.o,ov_SC03_124_jr_801734BC.o,tail15.data.o,ov_SC03_124_jr_801789AC.o,ov_SC03_124_jr_80178D40.o,tail16.data.o,ov_SC03_124_jr_8017A4AC.o,tail17.data.o,ov_SC03_124_jr_8017AE2C.o,tail18.data.o,ov_SC03_124_jr_80185498.o,tail19.data.o,ov_SC03_124_jr_80187010.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve
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ov_SC03_124_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_124.o,ov_SC03_124_jr_8012ACE0.o,tail2.data.o,ov_SC03_124_jr_80135888.o,tail3.data.o,ov_SC03_124_jr_80135A4C.o,tail4.data.o,ov_SC03_124_jr_80135D20.o,tail5.data.o,ov_SC03_124_jr_801380E0.o,ov_SC03_124_o0c.o,tail6.data.o,ov_SC03_124_jr_8013F350.o,tail7.data.o,ov_SC03_124_jr_8013FFD8.o,tail8.data.o,ov_SC03_124_jr_80140608.o,tail9.data.o,ov_SC03_124_jr_8015444C.o,ov_SC03_124_jr_80154C24.o,ov_SC03_124_jr_801588CC.o,ov_SC03_124_jr_80159C84.o,tail10.data.o,ov_SC03_124_jr_8015A3C8.o,tail11.data.o,ov_SC03_124_jr_8015AE2C.o,tail12.data.o,ov_SC03_124_jr_8015C32C.o,tail13.data.o,ov_SC03_124_jr_8016AB6C.o,tail14.data.o,ov_SC03_124_jr_80171B4C.o,ov_SC03_124_jr_801734BC.o,tail15.data.o,ov_SC03_124_jr_801789AC.o,ov_SC03_124_jr_80178D40.o,tail16.data.o,ov_SC03_124_jr_8017A4AC.o,tail17.data.o,ov_SC03_124_jr_8017AE2C.o,tail18.data.o,ov_SC03_124_jr_80185498.o,tail19.data.o,ov_SC03_124_jr_80187010.o,tail20.data.o,ov_SC03_124_jr_80188544.o,tail21.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve
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build/src/ov_SC03_124/ov_SC03_124.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14
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build/src/ov_SC03_124/ov_SC03_124_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0
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build/src/ov_SC03_124/ov_SC03_124_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18
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@@ -3888,7 +3888,7 @@ ov_SC05_017_ELF := $(ov_SC05_017_OUT).elf
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ov_SC05_017_MAPFILE := $(ov_SC05_017_OUT).map
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ov_SC05_017_LD_SCRIPT := $(ov_SC05_017_OUT).ld
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ov_SC05_017_SPLAT_YAML := config/splat.ov_SC05_017.yaml
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ov_SC05_017_JTBL_INTERLEAVE := --order tail.data.o,ov_SC05_017.o,ov_SC05_017_jr_8012ACE0.o,tail2.data.o,ov_SC05_017_jr_80135888.o,tail3.data.o,ov_SC05_017_jr_80135A4C.o,tail4.data.o,ov_SC05_017_jr_80135D20.o,tail5.data.o,ov_SC05_017_jr_801380E0.o,ov_SC05_017_o0c.o,tail6.data.o,ov_SC05_017_jr_8013F350.o,tail7.data.o,ov_SC05_017_jr_8013FFD8.o,tail8.data.o,ov_SC05_017_jr_80140608.o,tail9.data.o,ov_SC05_017_jr_8015444C.o,ov_SC05_017_jr_80154C24.o,ov_SC05_017_jr_801588CC.o,ov_SC05_017_jr_80159C84.o,tail10.data.o,ov_SC05_017_jr_8015A3C8.o,tail11.data.o,ov_SC05_017_jr_8015AE2C.o,tail12.data.o,ov_SC05_017_jr_8015C32C.o,tail13.data.o,ov_SC05_017_jr_8016AB6C.o,tail14.data.o,ov_SC05_017_jr_80171B4C.o,ov_SC05_017_jr_801734BC.o,tail15.data.o,ov_SC05_017_jr_801789AC.o,ov_SC05_017_jr_80178D40.o,tail16.data.o,ov_SC05_017_jr_8017A4AC.o,tail17.data.o,ov_SC05_017_jr_8017AE2C.o,tail18.data.o,ov_SC05_017_jr_80185A70.o,tail19.data.o,ov_SC05_017_jr_801875E8.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve
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ov_SC05_017_JTBL_INTERLEAVE := --order tail.data.o,ov_SC05_017.o,ov_SC05_017_jr_8012ACE0.o,tail2.data.o,ov_SC05_017_jr_80135888.o,tail3.data.o,ov_SC05_017_jr_80135A4C.o,tail4.data.o,ov_SC05_017_jr_80135D20.o,tail5.data.o,ov_SC05_017_jr_801380E0.o,ov_SC05_017_o0c.o,tail6.data.o,ov_SC05_017_jr_8013F350.o,tail7.data.o,ov_SC05_017_jr_8013FFD8.o,tail8.data.o,ov_SC05_017_jr_80140608.o,tail9.data.o,ov_SC05_017_jr_8015444C.o,ov_SC05_017_jr_80154C24.o,ov_SC05_017_jr_801588CC.o,ov_SC05_017_jr_80159C84.o,tail10.data.o,ov_SC05_017_jr_8015A3C8.o,tail11.data.o,ov_SC05_017_jr_8015AE2C.o,tail12.data.o,ov_SC05_017_jr_8015C32C.o,tail13.data.o,ov_SC05_017_jr_8016AB6C.o,tail14.data.o,ov_SC05_017_jr_80171B4C.o,ov_SC05_017_jr_801734BC.o,tail15.data.o,ov_SC05_017_jr_801789AC.o,ov_SC05_017_jr_80178D40.o,tail16.data.o,ov_SC05_017_jr_8017A4AC.o,tail17.data.o,ov_SC05_017_jr_8017AE2C.o,tail18.data.o,ov_SC05_017_jr_80185A70.o,tail19.data.o,ov_SC05_017_jr_801875E8.o,tail20.data.o,ov_SC05_017_jr_80188B1C.o,tail21.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve
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build/src/ov_SC05_017/ov_SC05_017.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14
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build/src/ov_SC05_017/ov_SC05_017_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0
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build/src/ov_SC05_017/ov_SC05_017_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18
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@@ -123,6 +123,7 @@ segments:
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- [0x606d8, c, ov_SC03_001_jr_80188830]
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- [0x60ed8, c, ov_SC03_001_jr_80189030]
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- [0x62250, c, ov_SC03_001_jr_8018A3A8]
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- [0x63784, c, ov_SC03_001_jr_8018B8DC]
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- [0x650c8, data, tail]
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- [0xc3b1c, .rodata, ov_SC03_001] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
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- [0xc3bf8, .rodata, ov_SC03_001_jr_8012ACE0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
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@@ -171,6 +172,8 @@ segments:
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- [0xc50bc, data, tail20]
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- [0xc5130, .rodata, ov_SC03_001_jr_8018A3A8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
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- [0xc5168, data, tail21]
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- [0xc5188, .rodata, ov_SC03_001_jr_8018B8DC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
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- [0xc51a8, data, tail22]
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- [0xC730C, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word)
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- [0xC730F] # EOF marker = the 0.4.dec byte length
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# @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes
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@@ -122,6 +122,7 @@ segments:
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- [0x52cd4, c, ov_SC03_124_jr_8017AE2C]
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- [0x5d340, c, ov_SC03_124_jr_80185498]
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- [0x5eeb8, c, ov_SC03_124_jr_80187010]
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- [0x603ec, c, ov_SC03_124_jr_80188544]
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- [0x6276c, data, tail]
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- [0xb6dd4, .rodata, ov_SC03_124] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
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- [0xb6eb0, .rodata, ov_SC03_124_jr_8012ACE0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
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@@ -168,6 +169,8 @@ segments:
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- [0xb7f84, data, tail19]
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- [0xb82ac, .rodata, ov_SC03_124_jr_80187010] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
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- [0xb82e4, data, tail20]
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- [0xb8304, .rodata, ov_SC03_124_jr_80188544] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
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- [0xb8324, data, tail21]
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- [0xBA48C, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word)
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- [0xBA48F] # EOF marker = the 0.4.dec byte length
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# @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes
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@@ -122,6 +122,7 @@ segments:
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- [0x52cd4, c, ov_SC04_019_jr_8017AE2C]
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- [0x5dc18, c, ov_SC04_019_jr_80185D70]
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- [0x5f790, c, ov_SC04_019_jr_801878E8]
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- [0x60cc4, c, ov_SC04_019_jr_80188E1C]
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- [0x64dd0, data, tail]
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- [0xbc2e8, .rodata, ov_SC04_019] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
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- [0xbc3c4, .rodata, ov_SC04_019_jr_8012ACE0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
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@@ -168,6 +169,8 @@ segments:
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- [0xbd4c4, data, tail19]
|
||||
- [0xbd7ec, .rodata, ov_SC04_019_jr_801878E8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
|
||||
- [0xbd824, data, tail20]
|
||||
- [0xbd844, .rodata, ov_SC04_019_jr_80188E1C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
|
||||
- [0xbd864, data, tail21]
|
||||
- [0xBF9CC, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word)
|
||||
- [0xBF9CF] # EOF marker = the 0.4.dec byte length
|
||||
# @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes
|
||||
|
||||
@@ -122,6 +122,7 @@ segments:
|
||||
- [0x52cd4, c, ov_SC05_017_jr_8017AE2C]
|
||||
- [0x5d918, c, ov_SC05_017_jr_80185A70]
|
||||
- [0x5f490, c, ov_SC05_017_jr_801875E8]
|
||||
- [0x609c4, c, ov_SC05_017_jr_80188B1C]
|
||||
- [0x64d94, data, tail]
|
||||
- [0xc2124, .rodata, ov_SC05_017] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
|
||||
- [0xc2200, .rodata, ov_SC05_017_jr_8012ACE0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
|
||||
@@ -168,6 +169,8 @@ segments:
|
||||
- [0xc3318, data, tail19]
|
||||
- [0xc3640, .rodata, ov_SC05_017_jr_801875E8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
|
||||
- [0xc3678, data, tail20]
|
||||
- [0xc3698, .rodata, ov_SC05_017_jr_80188B1C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
|
||||
- [0xc36b8, data, tail21]
|
||||
- [0xC582C, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word)
|
||||
- [0xC582F] # EOF marker = the 0.4.dec byte length
|
||||
# @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes
|
||||
|
||||
@@ -3949,514 +3949,3 @@ s32 *func_8018B478(s32 *ot, Panel_8017E978_8018B478 *w0, s16 idx) {
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_001/nonmatchings/ov_SC03_001_jr_8018A3A8", func_8018B644);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_001/nonmatchings/ov_SC03_001_jr_8018A3A8", func_8018B8DC);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/* Duplicate of the TU's own forward decl at ov_SC03_001_jr_8017AE2C.c:9324 (ABOVE the splice
|
||||
* point, §138) — kept verbatim so the K&R definition below is checked against it. The 3rd
|
||||
* parameter is `s32` in that prototype and `s16` here: a K&R identifier-list definition is
|
||||
* compatible with a prototype carrying the DEFAULT-PROMOTED type, and the s16 spelling is what
|
||||
* produces the target's per-use `sll/sra 16` off the raw $a2 kept in $s4. */
|
||||
extern s32 *func_8018BCD4(s32 *, void *, s32, void *, s32);
|
||||
|
||||
s32 *func_8018BCD4(out, src, idx, w, col)
|
||||
s32 *out;
|
||||
void *src;
|
||||
s16 idx;
|
||||
void *w;
|
||||
s32 col;
|
||||
{
|
||||
extern short D_800B9A02; /* TU-visible spelling (file scope, line 2448) */
|
||||
extern s16 func_8014168C(s16 a0);
|
||||
extern u16 D_8011511A;
|
||||
extern u16 D_80115116;
|
||||
extern u8 D_80115138[];
|
||||
extern u8 D_80115140[];
|
||||
extern u8 D_80115148[];
|
||||
extern u8 D_80115158[];
|
||||
extern u16 D_801C11BA;
|
||||
extern u16 D_801C11CE;
|
||||
|
||||
extern Env_8018BCD4 D_800AE7BC[];
|
||||
|
||||
|
||||
/* §37 /s-DEP LATTICE: this store MUST be MEM_IN_STRUCT_P. `out[0] = k` folds `out + 0`
|
||||
* away and expands as a NON-/s mem, which keeps the true_dependence edge to the incoming
|
||||
* 5th-arg slot and pins `lw $v1,0x38($sp)` after it. The target has the arg load AFTER
|
||||
* the out[0] store, i.e. the edge must be DROPPED — sched.c's drop clause needs the store
|
||||
* /s + varying and the load non-/s + fixed-address. A COMPONENT_REF at offset 0 supplies
|
||||
* the /s. (This single bit was the last 10 of 203 instructions.) */
|
||||
|
||||
s32 c;
|
||||
s16 t;
|
||||
u16 *q;
|
||||
s32 m;
|
||||
volatile u16 *pbh;
|
||||
|
||||
c = D_80115138[idx];
|
||||
|
||||
((W_8018BCD4 *)out)->w = 0x04000000;
|
||||
*((u8 *)out + 0xC) = 0x30;
|
||||
*((u8 *)out + 0xD) = 0x48;
|
||||
*(s16 *)((u8 *)out + 0xE) = 0x4056;
|
||||
out[1] = col | 0x64000000;
|
||||
|
||||
if (c < 10) {
|
||||
/* §135 idiom 9/T3: the fleet decl returns s16; cast at the CALL so the return feeds
|
||||
* `sll $v0,$v0,1` with no `andi`/re-extend. */
|
||||
t = ((s32 (*)(s16)) func_8014168C)(idx) * 2;
|
||||
} else {
|
||||
t = (D_80115148[idx * 2] - D_80115140[idx]) * 2;
|
||||
}
|
||||
|
||||
q = (u16 *)(t * 2 + (s32)src);
|
||||
pbh = (volatile u16 *)&D_800B9A02;
|
||||
*(s16 *)((u8 *)out + 0x8) = q[0] - 8;
|
||||
*(s16 *)((u8 *)out + 0xA) = q[1];
|
||||
*(s16 *)((u8 *)out + 0x12) = 8;
|
||||
*(s16 *)((u8 *)out + 0x10) = 8;
|
||||
|
||||
/* §36 BITFIELD STORE = THE MASK-ORDER DECOUPLER. The head materializes 0x00FFFFFF
|
||||
* (lui+ori) BEFORE 0xFF000000 (lui) while the body ANDs the dest first — the signature of
|
||||
* expmed.c's store_fixed_bit_field, not of user-mask C. `volatile` on the index read is
|
||||
* what keeps the SECOND *pbh load alive (a plain read cse-folds and the fn loses 5 ins). */
|
||||
((PTag_8018BCD4 *)out)->addr =
|
||||
((PTag_8018BCD4 *)(D_800AE7BC[*pbh].ot + 2))->addr;
|
||||
((PTag_8018BCD4 *)(D_800AE7BC[*pbh].ot + 2))->addr = (u32)out;
|
||||
|
||||
out += 5;
|
||||
if (c < 10) {
|
||||
return out;
|
||||
}
|
||||
|
||||
m = D_8011511A;
|
||||
if (m == idx) {
|
||||
if ((D_80115116 & 8) != 0) {
|
||||
s16 j;
|
||||
s32 k;
|
||||
s16 y;
|
||||
s16 eight;
|
||||
u16 *pb;
|
||||
/* §137/§36: m24 is a 2-insn constant, but the natural allocno order puts j/k ahead
|
||||
* of it and rotates $a2/$a3/$t0. Pinning m24 alone restores the whole rotation. */
|
||||
register u32 m24 __asm__("$6");
|
||||
u32 mhi;
|
||||
s32 vsum;
|
||||
|
||||
j = 0;
|
||||
k = m;
|
||||
eight = 8;
|
||||
pb = (u16 *)&D_800B9A02;
|
||||
m24 = 0xFFFFFF;
|
||||
mhi = 0xFF000000;
|
||||
/* NOTE: the loop deliberately has NO source pointer of its own. gcc's combine_givs
|
||||
* folds every `out + K` reference into ONE address giv based at out+0x12; adding a
|
||||
* `u8 *p = (u8*)out + 0x12` biv makes `*(s16*)p` use the biv directly, which
|
||||
* survives as a SECOND register (the +1-instruction LENGTH-DRIFT). The giv's base
|
||||
* is the LAST such reference in source order — hence the +8 (`vsum`) store sits
|
||||
* before the 0x10/0x12 stores here even though the scheduler sinks it back. */
|
||||
for (; j < 2; j++) {
|
||||
if (j == 0) {
|
||||
if (D_80115140[k] == 0) {
|
||||
continue;
|
||||
}
|
||||
*((u8 *)out + 0xD) = 0x30;
|
||||
y = D_801C11BA - 2;
|
||||
} else {
|
||||
s32 k2 = k * 2;
|
||||
if ((((s8 *)D_80115158)[k2] - ((s8 *)D_80115140)[k]) < 7) {
|
||||
continue;
|
||||
}
|
||||
*((u8 *)out + 0xD) = 0x38;
|
||||
y = D_801C11CE + 1;
|
||||
}
|
||||
*(s16 *)((u8 *)out + 0xA) = y;
|
||||
__asm__("" ::: "memory"); /* keeps the y store ahead of the 0x64808080 pair */
|
||||
*(u32 *)out = 0x04000000;
|
||||
*((u8 *)out + 0xC) = 0x78;
|
||||
*(u32 *)((u8 *)out + 0x4) = 0x64808080;
|
||||
*(s16 *)((u8 *)out + 0xE) = 0x4056;
|
||||
vsum = *(s32 *)((u8 *)w + 8) + *(s32 *)((u8 *)w + 0xC) - 0xC;
|
||||
*(s16 *)((u8 *)out + 0x8) = vsum;
|
||||
*(s16 *)((u8 *)out + 0x10) = eight;
|
||||
*(s16 *)((u8 *)out + 0x12) = eight;
|
||||
*(u32 *)out = ((*(u32 *)out) & mhi) | (D_800AE7BC[*pb].ot[2] & m24);
|
||||
{
|
||||
register u32 *op __asm__("$4");
|
||||
op = D_800AE7BC[*pb].ot;
|
||||
op[2] = (op[2] & mhi) | (((u32)out) & m24);
|
||||
}
|
||||
out += 5;
|
||||
}
|
||||
}
|
||||
}
|
||||
return out;
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_001/nonmatchings/ov_SC03_001_jr_8018A3A8", func_8018C000);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_001/nonmatchings/ov_SC03_001_jr_8018A3A8", func_8018C89C);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_001/nonmatchings/ov_SC03_001_jr_8018A3A8", func_8018C8D4);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_001/nonmatchings/ov_SC03_001_jr_8018A3A8", func_8018C914);
|
||||
|
||||
#include "common.h"
|
||||
|
||||
/* func_8018C960 — ov_SC03_001 (133 ins), exemplar of a 5-member open-only
|
||||
* h_norm cluster. Builds the full-screen fade overlay: a DR_MODE-style 8-byte
|
||||
* GP0 packet (0xE1000015), a 320x240 semi-transparent gouraud quad (POLY_G4,
|
||||
* code 0x3A), and a second 8-byte GP0 packet (0xE1000240), each linked into the
|
||||
* current OT with the psyq `addPrim` idiom. The type shapes and the
|
||||
* `((PTag *)x)->addr = ((PTag *)ot)->addr; ((PTag *)ot)->addr = (u32)x;` pair
|
||||
* are copied VERBATIM from the already-matched neighbour func_8018BCD4 in this
|
||||
* same TU (§71) — Env_* / PTag_* there are the fleet-canonical shapes.
|
||||
*
|
||||
* Levers that were load-bearing (all byte-tested; the draft is PIN-FREE):
|
||||
* §20 &D_801151D0 / &D_800B9A02 taken into pointer LOCALS -> each address is
|
||||
* force_reg'd once (lui+addiu -> $t2 / $a3) instead of a %lo per use.
|
||||
* §36 the 24-bit BITFIELD store, not a hand-written mask, is what emits
|
||||
* 0x00FFFFFF (lui+ori) ahead of 0xFF000000 (lui) while the body ANDs the
|
||||
* destination first — expmed's store_fixed_bit_field signature.
|
||||
* §37 asm-label aliases for D_801EF1EC/D_801EF1F0: the TU canon is u16/s16
|
||||
* but the target does a bare `lbu %lo(sym)`, and a plain block-scope
|
||||
* `extern u8` would be a conflicting redeclaration.
|
||||
* --- `volatile` on the OT index read keeps all SIX *pbh loads alive; a plain
|
||||
* read cse-folds them and the function loses ~25 instructions.
|
||||
* S1 the whole body is ONE branch-free basic block and every store ties at
|
||||
* the same priority, so forward asm order == source statement order —
|
||||
* the POLY_G4 block below is a literal transcription of the target.
|
||||
* S2 `p` is destructively updated (multi-set -> no birthing boost) so its
|
||||
* `addiu +8` floats up into the preceding load-delay gap, while `r` is a
|
||||
* FRESH single-set local (boosted) so its `addiu +0x24` sinks to sit
|
||||
* immediately before `sb 3($a0)`. Both placements are the target's.
|
||||
* --- the bare `p = r;` before r's uses is a COMBINE BARRIER: without a SET
|
||||
* of `p` between `r = p + 9` and r's first use, `can_combine_p` lets
|
||||
* combine substitute `r` -> `p + 0x24` into every MEM offset and the
|
||||
* `addiu` disappears entirely (and, at the tail, `p += 2` folds to
|
||||
* `addiu $t3,$t3,0x2C` off the stale base instead of `addiu $t3,$a0,8`).
|
||||
* It also fixes the register rotation for free — verified that adding or
|
||||
* removing `register __asm__` pins on p/r/pbh is a byte no-op.
|
||||
*/
|
||||
|
||||
/* ---- TU-visible spellings (file scope of ov_SC03_001_jr_8018A3A8.c) ---- */
|
||||
extern s16 D_800B9A02;
|
||||
extern s32 D_801151D0;
|
||||
extern u16 D_801EF1EC;
|
||||
extern s16 D_801EF1F0;
|
||||
|
||||
void func_8018C960(void) {
|
||||
/* §100/§120: draft-local, uniquely-named types — they live in the BODY so
|
||||
* they cannot collide with the TU's own Env_8018BCD4 / PTag_8018BCD4. */
|
||||
typedef struct { u32 addr : 24; u32 len : 8; } PTag_8018C960;
|
||||
typedef struct { u32 *ot; u32 pad[4]; } Env_8018C960; /* 0x14 stride */
|
||||
typedef struct {
|
||||
u32 tag; /* 0x00 */
|
||||
u8 r0, g0, b0, code; /* 0x04..0x07 */
|
||||
s16 x0, y0; /* 0x08, 0x0A */
|
||||
u8 r1, g1, b1, p1; /* 0x0C..0x0F */
|
||||
s16 x1, y1; /* 0x10, 0x12 */
|
||||
u8 r2, g2, b2, p2; /* 0x14..0x17 */
|
||||
s16 x2, y2; /* 0x18, 0x1A */
|
||||
u8 r3, g3, b3, p3; /* 0x1C..0x1F */
|
||||
s16 x3, y3; /* 0x20, 0x22 */
|
||||
} PG4_8018C960; /* -> 0x24 */
|
||||
|
||||
extern Env_8018C960 D_800AE7BC[];
|
||||
extern u8 aD801EF1EC __asm__("D_801EF1EC");
|
||||
extern u8 aD801EF1F0 __asm__("D_801EF1F0");
|
||||
|
||||
u32 **pp;
|
||||
volatile u16 *pbh;
|
||||
u32 *p;
|
||||
u32 *r;
|
||||
u8 c1, c2;
|
||||
|
||||
pp = (u32 **)&D_801151D0;
|
||||
pbh = (volatile u16 *)&D_800B9A02;
|
||||
|
||||
p = *pp;
|
||||
((PTag_8018C960 *)p)->len = 1;
|
||||
p[1] = 0xE1000015;
|
||||
((PTag_8018C960 *)p)->addr = ((PTag_8018C960 *)D_800AE7BC[*pbh].ot)->addr;
|
||||
((PTag_8018C960 *)D_800AE7BC[*pbh].ot)->addr = (u32)p;
|
||||
|
||||
p += 2;
|
||||
((PG4_8018C960 *)p)->tag = 0x08000000;
|
||||
((PG4_8018C960 *)p)->code = 0x3A;
|
||||
((PG4_8018C960 *)p)->x2 = -160;
|
||||
((PG4_8018C960 *)p)->x0 = -160;
|
||||
((PG4_8018C960 *)p)->x3 = 160;
|
||||
((PG4_8018C960 *)p)->x1 = 160;
|
||||
c1 = aD801EF1EC;
|
||||
((PG4_8018C960 *)p)->b1 = c1;
|
||||
((PG4_8018C960 *)p)->b0 = c1;
|
||||
((PG4_8018C960 *)p)->g1 = c1;
|
||||
((PG4_8018C960 *)p)->g0 = c1;
|
||||
((PG4_8018C960 *)p)->r1 = c1;
|
||||
((PG4_8018C960 *)p)->r0 = c1;
|
||||
c2 = aD801EF1F0;
|
||||
((PG4_8018C960 *)p)->y1 = -120;
|
||||
((PG4_8018C960 *)p)->b3 = c2;
|
||||
((PG4_8018C960 *)p)->b2 = c2;
|
||||
((PG4_8018C960 *)p)->g3 = c2;
|
||||
((PG4_8018C960 *)p)->g2 = c2;
|
||||
((PG4_8018C960 *)p)->r3 = c2;
|
||||
((PG4_8018C960 *)p)->r2 = c2;
|
||||
((PG4_8018C960 *)p)->y0 = -120;
|
||||
((PG4_8018C960 *)p)->y3 = 120;
|
||||
((PG4_8018C960 *)p)->y2 = 120;
|
||||
|
||||
((PTag_8018C960 *)p)->addr = ((PTag_8018C960 *)D_800AE7BC[*pbh].ot)->addr;
|
||||
((PTag_8018C960 *)D_800AE7BC[*pbh].ot)->addr = (u32)p;
|
||||
|
||||
r = p + 9; /* 0x24 */
|
||||
p = r; /* COMBINE BARRIER — see header */
|
||||
((PTag_8018C960 *)r)->len = 1;
|
||||
r[1] = 0xE1000240;
|
||||
((PTag_8018C960 *)r)->addr = ((PTag_8018C960 *)D_800AE7BC[*pbh].ot)->addr;
|
||||
((PTag_8018C960 *)D_800AE7BC[*pbh].ot)->addr = (u32)r;
|
||||
|
||||
p += 2;
|
||||
*pp = p;
|
||||
}
|
||||
|
||||
|
||||
|
||||
extern void (*D_801EB364[])(void);
|
||||
|
||||
void func_8018CB74(void *a0) {
|
||||
D_801EB364[*(u16 *)((s32)a0 + 0x2)]();
|
||||
}
|
||||
|
||||
|
||||
|
||||
// @class: iv-combine
|
||||
// @stuck: none — MATCH (49 ins). gcc folds (v0+0x1800)-0x1000 -> v0+0x800; re-tie barrier on the WORKING reg v0 (NOT a saved local) forces the target chain v0=base+0x1800; s2=copy; v0-=0x1000; s1=v0<<5. NO register pins (pins re-trigger the lhu/lh dual-load CSE collapse and shrink the frame; natural alloc gives s0-s3 + frame 0x38).
|
||||
extern int rand(void);
|
||||
extern u8 *func_8012913C(s32 a0);
|
||||
|
||||
extern unsigned short D_801EB344[];
|
||||
|
||||
void func_8018CBB0(s32 param_1, s32 param_2)
|
||||
{
|
||||
int s3;
|
||||
unsigned short s0;
|
||||
int s2;
|
||||
int s1;
|
||||
int v0;
|
||||
int iVar3;
|
||||
|
||||
s0 = D_801EB344[*(short *)(param_1 + 0xfc)];
|
||||
s3 = param_2;
|
||||
if (((short *)D_801EB344)[*(short *)(param_1 + 0xfc)] == 0) {
|
||||
*(short *)(param_1 + 0xfc) = 0;
|
||||
s0 = D_801EB344[0];
|
||||
}
|
||||
*(short *)(param_1 + 0xfc) = *(short *)(param_1 + 0xfc) + 1;
|
||||
v0 = (rand() & 3) * 0x400 + 0x1800;
|
||||
s2 = v0;
|
||||
__asm__ __volatile__("" : "=r"(v0) : "0"(v0));
|
||||
s1 = (v0 - 0x1000) * 0x20;
|
||||
iVar3 = ((int (*)(int))func_8012913C)(4);
|
||||
if (iVar3 != 0) {
|
||||
*(short *)(iVar3 + 6) = s3;
|
||||
*(short *)(iVar3 + 0xa) = s0;
|
||||
*(short *)(iVar3 + 0xe) = 0;
|
||||
*(int *)(iVar3 + 0x10) = s1;
|
||||
*(short *)(iVar3 + 0x2c) = s2;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
extern void (*D_801EB378[])(void);
|
||||
|
||||
void func_8018CC74(void *a0) {
|
||||
D_801EB378[*(u16 *)((s32)a0 + 0x2)]();
|
||||
}
|
||||
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH
|
||||
|
||||
extern void func_8018CBB0(s32, s32);
|
||||
extern s32 func_8012AD50(void *a0);
|
||||
|
||||
void func_8018CCB0(int param_1) {
|
||||
short uVar1;
|
||||
|
||||
*(short *)(param_1 + 0xfc) = 0;
|
||||
*(int *)(param_1 + 0x1c) = 1;
|
||||
uVar1 = *(unsigned short *)(param_1 + 0x70) & 7;
|
||||
*(short *)(param_1 + 0xfe) = (uVar1 < 2) ? 0x1e : 0xf;
|
||||
if (uVar1 != 0) {
|
||||
func_8018CBB0(param_1, -0x80);
|
||||
func_8018CBB0(param_1, -0x30);
|
||||
func_8018CBB0(param_1, 0x20);
|
||||
func_8018CBB0(param_1, 0x70);
|
||||
func_8018CBB0(param_1, 0xc0);
|
||||
}
|
||||
if (1 < uVar1) {
|
||||
func_8018CBB0(param_1, -0x58);
|
||||
func_8018CBB0(param_1, -0x8);
|
||||
func_8018CBB0(param_1, 0x48);
|
||||
func_8018CBB0(param_1, 0x98);
|
||||
func_8018CBB0(param_1, 0xe8);
|
||||
}
|
||||
((void (*)(int))func_8012AD50)(param_1);
|
||||
}
|
||||
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (param_1 naturally lands in $s0 across the call, mirrors sibling func_80184AEC)
|
||||
|
||||
extern s32 func_8012BEE8(s32 a0);
|
||||
extern void func_8018CBB0(s32, s32);
|
||||
|
||||
void func_8018CD98(s32 arg0) {
|
||||
if (func_8012BEE8(arg0)) {
|
||||
*(s32 *)(arg0 + 0x1c) = (s32)*(s16 *)(arg0 + 0xfe);
|
||||
func_8018CBB0(arg0, 0x110);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
// @class: plumbing
|
||||
// @stuck: none — MATCH (expected)
|
||||
extern void func_8001CB00(int param_1, void *src, int len, int n);
|
||||
|
||||
extern unsigned char D_801EB36C;
|
||||
|
||||
void func_8018CDD8(int param_1)
|
||||
{
|
||||
unsigned short uVar1;
|
||||
int iVar2;
|
||||
|
||||
iVar2 = *(int *)(param_1 + 0x20);
|
||||
func_8001CB00(iVar2, &D_801EB36C, 0x280, 0x100);
|
||||
*(unsigned int *)(iVar2 + 4) = *(unsigned int *)(iVar2 + 4) | 0x70000000;
|
||||
uVar1 = *(unsigned short *)(param_1 + 0x2c);
|
||||
*(unsigned char *)(iVar2 + 0x27) = 0x9e;
|
||||
*(unsigned short *)(iVar2 + 0x2c) = 4;
|
||||
*(unsigned short *)(iVar2 + 0x1c) = uVar1;
|
||||
*(unsigned short *)(iVar2 + 0x1a) = uVar1;
|
||||
*(unsigned short *)(iVar2 + 0x18) = uVar1;
|
||||
*(short *)(param_1 + 2) = *(short *)(param_1 + 2) + 1;
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
|
||||
extern void func_801292C8(u8 *a0);
|
||||
|
||||
void func_8018CE60(u8 *a0) {
|
||||
*(s32 *)(a0 + 0x4) = *(s32 *)(a0 + 0x4) - *(s32 *)(a0 + 0x10);
|
||||
if (*(s16 *)(a0 + 0x6) < -0x110) {
|
||||
func_801292C8(a0);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_001/nonmatchings/ov_SC03_001_jr_8018A3A8", func_8018CEA8);
|
||||
|
||||
|
||||
extern void (*D_801EB48C[])(void);
|
||||
|
||||
void func_8018CF54(void *a0) {
|
||||
D_801EB48C[*(u16 *)((s32)a0 + 0x2)]();
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
/* Declarations conformed to the TU (ov_SC04_018_jr_8017AE2C.c) — lever (A):
|
||||
* func_8012A828 : TU declares `extern void ((void (*)(s32*, s32))func_8012A828)(s32*, s32);`
|
||||
* at L3460 / L4615 / L5083 / L5372 / L5859 / L6004 / L6155 /
|
||||
* L6479 / L6504 / L6529. The draft's `(s32, s32)` form caused
|
||||
* the 7697-vs-6529 conflict. Conformed here; the type
|
||||
* disagreement is pushed to a cast at the call site.
|
||||
* D_8018D838 : TU declares `extern u8 D_8018D838[];` (block scope, L3467).
|
||||
* Conformed; `(s32)D_8018D838` == `(s32)&D_8018D838`.
|
||||
* func_801788B8 : verbatim from TU L2532 / L7756 (below the splice point).
|
||||
* func_8012C354, D_801EB390, func_8018D088, func_8018CF90 : no other
|
||||
* declaration anywhere in the TU (func_8018D088 / func_8018CF90
|
||||
* appear only as INCLUDE_ASM, which emits no C declaration).
|
||||
*
|
||||
* Body: the original draft was NOT byte-correct. `*(u16 *)(x + 2) = 1;` must be
|
||||
* sequenced BEFORE the func_8012A828 call, not after it — with it after, gcc
|
||||
* coalesces the store base onto $a0 (`sh v0,2(a0)`) and re-emits the arg copy,
|
||||
* giving a 6-instruction ADDRESSING/cse diff. Moved above the call; both stores
|
||||
* now retire off $s0 and the sh lands in the jal delay slot, as in the target. */
|
||||
|
||||
extern s32 func_8012C354(s32 a0, s32 a1);
|
||||
extern void func_8012A828(s32, s32);
|
||||
extern s32 func_801788B8(s32 arg0, s32 arg1);
|
||||
|
||||
extern void func_8018D088(void);
|
||||
|
||||
void func_8018CF90(s32 a0) {
|
||||
|
||||
extern M2C_UNK D_801EB390;
|
||||
extern u8 D_8018D838[];
|
||||
s32 s0 = a0;
|
||||
if (func_8012C354(a0, (s32)&D_801EB390)) {
|
||||
*(u8 *)(s0 + 0xC0) = 1;
|
||||
*(u16 *)(s0 + 0x2) = 1;
|
||||
((void (*)(s32*, s32))func_8012A828)((s32 *)s0, (s32)D_8018D838);
|
||||
func_801788B8(s0, (s32)func_8018D088);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void func_8018CFF4(void) {
|
||||
}
|
||||
|
||||
|
||||
extern void func_80178CBC(s32 *a0, s32 a1);
|
||||
|
||||
void func_8018CFFC(s32 *a0)
|
||||
{
|
||||
|
||||
extern signed char D_801EB468[];
|
||||
s32 v0;
|
||||
|
||||
v0 = *(s16 *)((s32)a0 + 0x70);
|
||||
v0 = v0 * 4;
|
||||
func_80178CBC(a0, *(s32 *)((s32)D_801EB468 + v0));
|
||||
*(s16 *)((s32)a0 + 0x2) = 0x3;
|
||||
}
|
||||
|
||||
|
||||
|
||||
extern int func_80178970(void);
|
||||
extern void func_80178D18(void);
|
||||
|
||||
void func_8018D048(s32 a0) {
|
||||
if (func_80178970() != 0) {
|
||||
((void (*)(s32))func_80178D18)(a0);
|
||||
*(s16 *)(a0 + 2) = 1;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_001/nonmatchings/ov_SC03_001_jr_8018A3A8", func_8018D088);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_001/nonmatchings/ov_SC03_001_jr_8018A3A8", func_8018D0E4);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -3632,570 +3632,3 @@ s32 *func_801880E0(s32 *ot, Panel_8017E978_801880E0 *w0, s16 idx) {
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_124/nonmatchings/ov_SC03_124_jr_80187010", func_801882AC);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_124/nonmatchings/ov_SC03_124_jr_80187010", func_80188544);
|
||||
|
||||
/* func_8018893C — twin of the byte-matched func_8018BCD4 in ov_SC03_001/ov_SC03_001_jr_8017AE2C.c
|
||||
* (family of 4: this fn + ov_SC04_018/func_80189214 + ov_SC04_019/func_80189214 +
|
||||
* ov_SC05_017/func_80188F14; all normalize byte-identical to this shape). Only the two
|
||||
* overlay-local data symbols differ (D_801BC522/D_801BC536 here vs D_801C11BA/D_801C11CE
|
||||
* there). Caller in this TU (func_801880E0) already declares the matching prototype:
|
||||
* extern s32 *func_8018893C(s32 *, void *, s32, void *, s32);
|
||||
*/
|
||||
|
||||
extern s32 *func_8018893C(s32 *, void *, s32, void *, s32);
|
||||
|
||||
s32 *func_8018893C(out, src, idx, w, col)
|
||||
s32 *out;
|
||||
void *src;
|
||||
s16 idx;
|
||||
void *w;
|
||||
s32 col;
|
||||
{
|
||||
extern short D_800B9A02; /* TU-visible spelling (file scope) */
|
||||
extern s16 func_8014168C(s16 a0);
|
||||
extern u16 D_8011511A;
|
||||
extern u16 D_80115116;
|
||||
extern u8 D_80115138[];
|
||||
extern u8 D_80115140[];
|
||||
extern u8 D_80115148[];
|
||||
extern u8 D_80115158[];
|
||||
extern u16 D_801BC522;
|
||||
extern u16 D_801BC536;
|
||||
|
||||
extern Env_8018893C D_800AE7BC[];
|
||||
|
||||
|
||||
/* §37 /s-DEP LATTICE: this store MUST be MEM_IN_STRUCT_P. `out[0] = k` folds `out + 0`
|
||||
* away and expands as a NON-/s mem, which keeps the true_dependence edge to the incoming
|
||||
* 5th-arg slot and pins `lw $v1,0x38($sp)` after it. The target has the arg load AFTER
|
||||
* the out[0] store, i.e. the edge must be DROPPED — sched.c's drop clause needs the store
|
||||
* /s + varying and the load non-/s + fixed-address. A COMPONENT_REF at offset 0 supplies
|
||||
* the /s. */
|
||||
|
||||
s32 c;
|
||||
s16 t;
|
||||
u16 *q;
|
||||
s32 m;
|
||||
volatile u16 *pbh;
|
||||
|
||||
c = D_80115138[idx];
|
||||
|
||||
((W_8018893C *)out)->w = 0x04000000;
|
||||
*((u8 *)out + 0xC) = 0x30;
|
||||
*((u8 *)out + 0xD) = 0x48;
|
||||
*(s16 *)((u8 *)out + 0xE) = 0x4056;
|
||||
out[1] = col | 0x64000000;
|
||||
|
||||
if (c < 10) {
|
||||
/* §135 idiom 9/T3: the fleet decl returns s16; cast at the CALL so the return feeds
|
||||
* `sll $v0,$v0,1` with no `andi`/re-extend. */
|
||||
t = ((s32 (*)(s16)) func_8014168C)(idx) * 2;
|
||||
} else {
|
||||
t = (D_80115148[idx * 2] - D_80115140[idx]) * 2;
|
||||
}
|
||||
|
||||
q = (u16 *)(t * 2 + (s32)src);
|
||||
pbh = (volatile u16 *)&D_800B9A02;
|
||||
*(s16 *)((u8 *)out + 0x8) = q[0] - 8;
|
||||
*(s16 *)((u8 *)out + 0xA) = q[1];
|
||||
*(s16 *)((u8 *)out + 0x12) = 8;
|
||||
*(s16 *)((u8 *)out + 0x10) = 8;
|
||||
|
||||
/* §36 BITFIELD STORE = THE MASK-ORDER DECOUPLER. The head materializes 0x00FFFFFF
|
||||
* (lui+ori) BEFORE 0xFF000000 (lui) while the body ANDs the dest first. `volatile` on the
|
||||
* index read is what keeps the SECOND *pbh load alive (a plain read cse-folds and the
|
||||
* fn loses 5 ins). */
|
||||
((PTag_8018893C *)out)->addr =
|
||||
((PTag_8018893C *)(D_800AE7BC[*pbh].ot + 2))->addr;
|
||||
((PTag_8018893C *)(D_800AE7BC[*pbh].ot + 2))->addr = (u32)out;
|
||||
|
||||
out += 5;
|
||||
if (c < 10) {
|
||||
return out;
|
||||
}
|
||||
|
||||
m = D_8011511A;
|
||||
if (m == idx) {
|
||||
if ((D_80115116 & 8) != 0) {
|
||||
s16 j;
|
||||
s32 k;
|
||||
s16 y;
|
||||
s16 eight;
|
||||
u16 *pb;
|
||||
/* §137/§36: m24 is a 2-insn constant, but the natural allocno order puts j/k ahead
|
||||
* of it and rotates $a2/$a3/$t0. Pinning m24 alone restores the whole rotation. */
|
||||
register u32 m24 __asm__("$6");
|
||||
u32 mhi;
|
||||
s32 vsum;
|
||||
|
||||
j = 0;
|
||||
k = m;
|
||||
eight = 8;
|
||||
pb = (u16 *)&D_800B9A02;
|
||||
m24 = 0xFFFFFF;
|
||||
mhi = 0xFF000000;
|
||||
/* NOTE: the loop deliberately has NO source pointer of its own. gcc's combine_givs
|
||||
* folds every `out + K` reference into ONE address giv based at out+0x12; adding a
|
||||
* `u8 *p = (u8*)out + 0x12` biv makes `*(s16*)p` use the biv directly, which
|
||||
* survives as a SECOND register (the +1-instruction LENGTH-DRIFT). The giv's base
|
||||
* is the LAST such reference in source order — hence the +8 (`vsum`) store sits
|
||||
* before the 0x10/0x12 stores here even though the scheduler sinks it back. */
|
||||
for (; j < 2; j++) {
|
||||
if (j == 0) {
|
||||
if (D_80115140[k] == 0) {
|
||||
continue;
|
||||
}
|
||||
*((u8 *)out + 0xD) = 0x30;
|
||||
y = D_801BC522 - 2;
|
||||
} else {
|
||||
s32 k2 = k * 2;
|
||||
if ((((s8 *)D_80115158)[k2] - ((s8 *)D_80115140)[k]) < 7) {
|
||||
continue;
|
||||
}
|
||||
*((u8 *)out + 0xD) = 0x38;
|
||||
y = D_801BC536 + 1;
|
||||
}
|
||||
*(s16 *)((u8 *)out + 0xA) = y;
|
||||
__asm__("" ::: "memory"); /* keeps the y store ahead of the 0x64808080 pair */
|
||||
*(u32 *)out = 0x04000000;
|
||||
*((u8 *)out + 0xC) = 0x78;
|
||||
*(u32 *)((u8 *)out + 0x4) = 0x64808080;
|
||||
*(s16 *)((u8 *)out + 0xE) = 0x4056;
|
||||
vsum = *(s32 *)((u8 *)w + 8) + *(s32 *)((u8 *)w + 0xC) - 0xC;
|
||||
*(s16 *)((u8 *)out + 0x8) = vsum;
|
||||
*(s16 *)((u8 *)out + 0x10) = eight;
|
||||
*(s16 *)((u8 *)out + 0x12) = eight;
|
||||
*(u32 *)out = ((*(u32 *)out) & mhi) | (D_800AE7BC[*pb].ot[2] & m24);
|
||||
{
|
||||
register u32 *op __asm__("$4");
|
||||
op = D_800AE7BC[*pb].ot;
|
||||
op[2] = (op[2] & mhi) | (((u32)out) & m24);
|
||||
}
|
||||
out += 5;
|
||||
}
|
||||
}
|
||||
}
|
||||
return out;
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_124/nonmatchings/ov_SC03_124_jr_80187010", func_80188C68);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_124/nonmatchings/ov_SC03_124_jr_80187010", func_80189504);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_124/nonmatchings/ov_SC03_124_jr_80187010", func_8018953C);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_124/nonmatchings/ov_SC03_124_jr_80187010", func_8018957C);
|
||||
|
||||
|
||||
/* func_801895C8 — ov_SC03_001 (133 ins), exemplar of a 5-member open-only
|
||||
* h_norm cluster. Builds the full-screen fade overlay: a DR_MODE-style 8-byte
|
||||
* GP0 packet (0xE1000015), a 320x240 semi-transparent gouraud quad (POLY_G4,
|
||||
* code 0x3A), and a second 8-byte GP0 packet (0xE1000240), each linked into the
|
||||
* current OT with the psyq `addPrim` idiom. The type shapes and the
|
||||
* `((PTag *)x)->addr = ((PTag *)ot)->addr; ((PTag *)ot)->addr = (u32)x;` pair
|
||||
* are copied VERBATIM from the already-matched neighbour func_8018BCD4 in this
|
||||
* same TU (§71) — Env_* / PTag_* there are the fleet-canonical shapes.
|
||||
*
|
||||
* Levers that were load-bearing (all byte-tested; the draft is PIN-FREE):
|
||||
* §20 &D_801151D0 / &D_800B9A02 taken into pointer LOCALS -> each address is
|
||||
* force_reg'd once (lui+addiu -> $t2 / $a3) instead of a %lo per use.
|
||||
* §36 the 24-bit BITFIELD store, not a hand-written mask, is what emits
|
||||
* 0x00FFFFFF (lui+ori) ahead of 0xFF000000 (lui) while the body ANDs the
|
||||
* destination first — expmed's store_fixed_bit_field signature.
|
||||
* §37 asm-label aliases for D_801E2364/D_801E2368: the TU canon is u16/s16
|
||||
* but the target does a bare `lbu %lo(sym)`, and a plain block-scope
|
||||
* `extern u8` would be a conflicting redeclaration.
|
||||
* --- `volatile` on the OT index read keeps all SIX *pbh loads alive; a plain
|
||||
* read cse-folds them and the function loses ~25 instructions.
|
||||
* S1 the whole body is ONE branch-free basic block and every store ties at
|
||||
* the same priority, so forward asm order == source statement order —
|
||||
* the POLY_G4 block below is a literal transcription of the target.
|
||||
* S2 `p` is destructively updated (multi-set -> no birthing boost) so its
|
||||
* `addiu +8` floats up into the preceding load-delay gap, while `r` is a
|
||||
* FRESH single-set local (boosted) so its `addiu +0x24` sinks to sit
|
||||
* immediately before `sb 3($a0)`. Both placements are the target's.
|
||||
* --- the bare `p = r;` before r's uses is a COMBINE BARRIER: without a SET
|
||||
* of `p` between `r = p + 9` and r's first use, `can_combine_p` lets
|
||||
* combine substitute `r` -> `p + 0x24` into every MEM offset and the
|
||||
* `addiu` disappears entirely (and, at the tail, `p += 2` folds to
|
||||
* `addiu $t3,$t3,0x2C` off the stale base instead of `addiu $t3,$a0,8`).
|
||||
* It also fixes the register rotation for free — verified that adding or
|
||||
* removing `register __asm__` pins on p/r/pbh is a byte no-op.
|
||||
*/
|
||||
|
||||
/* ---- TU-visible spellings (file scope of ov_SC03_001_jr_8018A3A8.c) ---- */
|
||||
|
||||
void func_801895C8(void) {
|
||||
|
||||
extern s32 D_801151D0;
|
||||
extern u16 D_801E2364;
|
||||
extern s16 D_801E2368;
|
||||
/* §100/§120: draft-local, uniquely-named types — they live in the BODY so
|
||||
* they cannot collide with the TU's own Env_8018BCD4 / PTag_8018BCD4. */
|
||||
typedef struct { u32 addr : 24; u32 len : 8; } PTag_8018C960_801895C8;
|
||||
typedef struct { u32 *ot; u32 pad[4]; } Env_8018C960_801895C8; /* 0x14 stride */
|
||||
typedef struct {
|
||||
u32 tag; /* 0x00 */
|
||||
u8 r0, g0, b0, code; /* 0x04..0x07 */
|
||||
s16 x0, y0; /* 0x08, 0x0A */
|
||||
u8 r1, g1, b1, p1; /* 0x0C..0x0F */
|
||||
s16 x1, y1; /* 0x10, 0x12 */
|
||||
u8 r2, g2, b2, p2; /* 0x14..0x17 */
|
||||
s16 x2, y2; /* 0x18, 0x1A */
|
||||
u8 r3, g3, b3, p3; /* 0x1C..0x1F */
|
||||
s16 x3, y3; /* 0x20, 0x22 */
|
||||
} PG4_8018C960_801895C8; /* -> 0x24 */
|
||||
|
||||
extern Env_8018C960_801895C8 D_800AE7BC[];
|
||||
extern u8 aD801EF1EC __asm__("D_801E2364");
|
||||
extern u8 aD801EF1F0 __asm__("D_801E2368");
|
||||
|
||||
u32 **pp;
|
||||
volatile u16 *pbh;
|
||||
u32 *p;
|
||||
u32 *r;
|
||||
u8 c1, c2;
|
||||
|
||||
pp = (u32 **)&D_801151D0;
|
||||
pbh = (volatile u16 *)&D_800B9A02;
|
||||
|
||||
p = *pp;
|
||||
((PTag_8018C960_801895C8 *)p)->len = 1;
|
||||
p[1] = 0xE1000015;
|
||||
((PTag_8018C960_801895C8 *)p)->addr = ((PTag_8018C960_801895C8 *)D_800AE7BC[*pbh].ot)->addr;
|
||||
((PTag_8018C960_801895C8 *)D_800AE7BC[*pbh].ot)->addr = (u32)p;
|
||||
|
||||
p += 2;
|
||||
((PG4_8018C960_801895C8 *)p)->tag = 0x08000000;
|
||||
((PG4_8018C960_801895C8 *)p)->code = 0x3A;
|
||||
((PG4_8018C960_801895C8 *)p)->x2 = -160;
|
||||
((PG4_8018C960_801895C8 *)p)->x0 = -160;
|
||||
((PG4_8018C960_801895C8 *)p)->x3 = 160;
|
||||
((PG4_8018C960_801895C8 *)p)->x1 = 160;
|
||||
c1 = aD801EF1EC;
|
||||
((PG4_8018C960_801895C8 *)p)->b1 = c1;
|
||||
((PG4_8018C960_801895C8 *)p)->b0 = c1;
|
||||
((PG4_8018C960_801895C8 *)p)->g1 = c1;
|
||||
((PG4_8018C960_801895C8 *)p)->g0 = c1;
|
||||
((PG4_8018C960_801895C8 *)p)->r1 = c1;
|
||||
((PG4_8018C960_801895C8 *)p)->r0 = c1;
|
||||
c2 = aD801EF1F0;
|
||||
((PG4_8018C960_801895C8 *)p)->y1 = -120;
|
||||
((PG4_8018C960_801895C8 *)p)->b3 = c2;
|
||||
((PG4_8018C960_801895C8 *)p)->b2 = c2;
|
||||
((PG4_8018C960_801895C8 *)p)->g3 = c2;
|
||||
((PG4_8018C960_801895C8 *)p)->g2 = c2;
|
||||
((PG4_8018C960_801895C8 *)p)->r3 = c2;
|
||||
((PG4_8018C960_801895C8 *)p)->r2 = c2;
|
||||
((PG4_8018C960_801895C8 *)p)->y0 = -120;
|
||||
((PG4_8018C960_801895C8 *)p)->y3 = 120;
|
||||
((PG4_8018C960_801895C8 *)p)->y2 = 120;
|
||||
|
||||
((PTag_8018C960_801895C8 *)p)->addr = ((PTag_8018C960_801895C8 *)D_800AE7BC[*pbh].ot)->addr;
|
||||
((PTag_8018C960_801895C8 *)D_800AE7BC[*pbh].ot)->addr = (u32)p;
|
||||
|
||||
r = p + 9; /* 0x24 */
|
||||
p = r; /* COMBINE BARRIER — see header */
|
||||
((PTag_8018C960_801895C8 *)r)->len = 1;
|
||||
r[1] = 0xE1000240;
|
||||
((PTag_8018C960_801895C8 *)r)->addr = ((PTag_8018C960_801895C8 *)D_800AE7BC[*pbh].ot)->addr;
|
||||
((PTag_8018C960_801895C8 *)D_800AE7BC[*pbh].ot)->addr = (u32)r;
|
||||
|
||||
p += 2;
|
||||
*pp = p;
|
||||
}
|
||||
|
||||
|
||||
|
||||
extern void (*D_801D52BC[])(void);
|
||||
|
||||
void func_801897DC(void *a0) {
|
||||
D_801D52BC[*(u16 *)((s32)a0 + 0x2)]();
|
||||
}
|
||||
|
||||
|
||||
|
||||
// @class: iv-combine
|
||||
// @stuck: none — MATCH (49 ins). gcc folds (v0+0x1800)-0x1000 -> v0+0x800; re-tie barrier on the WORKING reg v0 (NOT a saved local) forces the target chain v0=base+0x1800; s2=copy; v0-=0x1000; s1=v0<<5. NO register pins (pins re-trigger the lhu/lh dual-load CSE collapse and shrink the frame; natural alloc gives s0-s3 + frame 0x38).
|
||||
extern int rand(void);
|
||||
extern u8 *func_8012913C(s32 a0);
|
||||
|
||||
extern unsigned short D_801D529C[];
|
||||
|
||||
void func_80189818(s32 param_1, s32 param_2)
|
||||
{
|
||||
int s3;
|
||||
unsigned short s0;
|
||||
int s2;
|
||||
int s1;
|
||||
int v0;
|
||||
int iVar3;
|
||||
|
||||
s0 = D_801D529C[*(short *)(param_1 + 0xfc)];
|
||||
s3 = param_2;
|
||||
if (((short *)D_801D529C)[*(short *)(param_1 + 0xfc)] == 0) {
|
||||
*(short *)(param_1 + 0xfc) = 0;
|
||||
s0 = D_801D529C[0];
|
||||
}
|
||||
*(short *)(param_1 + 0xfc) = *(short *)(param_1 + 0xfc) + 1;
|
||||
v0 = (rand() & 3) * 0x400 + 0x1800;
|
||||
s2 = v0;
|
||||
__asm__ __volatile__("" : "=r"(v0) : "0"(v0));
|
||||
s1 = (v0 - 0x1000) * 0x20;
|
||||
iVar3 = ((int (*)(int))func_8012913C)(4);
|
||||
if (iVar3 != 0) {
|
||||
*(short *)(iVar3 + 6) = s3;
|
||||
*(short *)(iVar3 + 0xa) = s0;
|
||||
*(short *)(iVar3 + 0xe) = 0;
|
||||
*(int *)(iVar3 + 0x10) = s1;
|
||||
*(short *)(iVar3 + 0x2c) = s2;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
extern void (*D_801D52D0[])(void);
|
||||
|
||||
void func_801898DC(void *a0) {
|
||||
D_801D52D0[*(u16 *)((s32)a0 + 0x2)]();
|
||||
}
|
||||
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH
|
||||
|
||||
extern void func_80189818(s32, s32);
|
||||
extern s32 func_8012AD50(void *a0);
|
||||
|
||||
void func_80189918(int param_1) {
|
||||
short uVar1;
|
||||
|
||||
*(short *)(param_1 + 0xfc) = 0;
|
||||
*(int *)(param_1 + 0x1c) = 1;
|
||||
uVar1 = *(unsigned short *)(param_1 + 0x70) & 7;
|
||||
*(short *)(param_1 + 0xfe) = (uVar1 < 2) ? 0x1e : 0xf;
|
||||
if (uVar1 != 0) {
|
||||
func_80189818(param_1, -0x80);
|
||||
func_80189818(param_1, -0x30);
|
||||
func_80189818(param_1, 0x20);
|
||||
func_80189818(param_1, 0x70);
|
||||
func_80189818(param_1, 0xc0);
|
||||
}
|
||||
if (1 < uVar1) {
|
||||
func_80189818(param_1, -0x58);
|
||||
func_80189818(param_1, -0x8);
|
||||
func_80189818(param_1, 0x48);
|
||||
func_80189818(param_1, 0x98);
|
||||
func_80189818(param_1, 0xe8);
|
||||
}
|
||||
((void (*)(int))func_8012AD50)(param_1);
|
||||
}
|
||||
|
||||
|
||||
|
||||
// @class: regalloc-order
|
||||
// @stuck: none — MATCH (param_1 naturally lands in $s0 across the call, mirrors sibling func_80184AEC)
|
||||
|
||||
extern s32 func_8012BEE8(s32 a0);
|
||||
extern void func_80189818(s32, s32);
|
||||
|
||||
void func_80189A00(s32 arg0) {
|
||||
if (func_8012BEE8(arg0)) {
|
||||
*(s32 *)(arg0 + 0x1c) = (s32)*(s16 *)(arg0 + 0xfe);
|
||||
func_80189818(arg0, 0x110);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
// @class: plumbing
|
||||
// @stuck: none — MATCH (expected)
|
||||
extern void func_8001CB00(int param_1, void *src, int len, int n);
|
||||
|
||||
extern unsigned char D_801D52C4;
|
||||
|
||||
void func_80189A40(int param_1)
|
||||
{
|
||||
unsigned short uVar1;
|
||||
int iVar2;
|
||||
|
||||
iVar2 = *(int *)(param_1 + 0x20);
|
||||
func_8001CB00(iVar2, &D_801D52C4, 0x280, 0x100);
|
||||
*(unsigned int *)(iVar2 + 4) = *(unsigned int *)(iVar2 + 4) | 0x70000000;
|
||||
uVar1 = *(unsigned short *)(param_1 + 0x2c);
|
||||
*(unsigned char *)(iVar2 + 0x27) = 0x9e;
|
||||
*(unsigned short *)(iVar2 + 0x2c) = 4;
|
||||
*(unsigned short *)(iVar2 + 0x1c) = uVar1;
|
||||
*(unsigned short *)(iVar2 + 0x1a) = uVar1;
|
||||
*(unsigned short *)(iVar2 + 0x18) = uVar1;
|
||||
*(short *)(param_1 + 2) = *(short *)(param_1 + 2) + 1;
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
|
||||
extern void func_801292C8(u8 *a0);
|
||||
|
||||
void func_80189AC8(u8 *a0) {
|
||||
*(s32 *)(a0 + 0x4) = *(s32 *)(a0 + 0x4) - *(s32 *)(a0 + 0x10);
|
||||
if (*(s16 *)(a0 + 0x6) < -0x110) {
|
||||
func_801292C8(a0);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_124/nonmatchings/ov_SC03_124_jr_80187010", func_80189B10);
|
||||
|
||||
|
||||
extern void (*D_801DE38C[])(void);
|
||||
|
||||
void func_80189BBC(void *a0) {
|
||||
D_801DE38C[*(u16 *)((s32)a0 + 0x2)]();
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
/* Declarations conformed to the TU (ov_SC04_018_jr_8017AE2C.c) — lever (A):
|
||||
* func_8012A828 : TU declares `extern void ((void (*)(s32*, s32))func_8012A828)(s32*, s32);`
|
||||
* at L3460 / L4615 / L5083 / L5372 / L5859 / L6004 / L6155 /
|
||||
* L6479 / L6504 / L6529. The draft's `(s32, s32)` form caused
|
||||
* the 7697-vs-6529 conflict. Conformed here; the type
|
||||
* disagreement is pushed to a cast at the call site.
|
||||
* D_8018AEDC : TU declares `extern u8 D_8018AEDC[];` (block scope, L3467).
|
||||
* Conformed; `(s32)D_8018AEDC` == `(s32)&D_8018AEDC`.
|
||||
* func_801788B8 : verbatim from TU L2532 / L7756 (below the splice point).
|
||||
* func_8012C354, D_801DE278, func_80189CF0, func_80189BF8 : no other
|
||||
* declaration anywhere in the TU (func_80189CF0 / func_80189BF8
|
||||
* appear only as INCLUDE_ASM, which emits no C declaration).
|
||||
*
|
||||
* Body: the original draft was NOT byte-correct. `*(u16 *)(x + 2) = 1;` must be
|
||||
* sequenced BEFORE the func_8012A828 call, not after it — with it after, gcc
|
||||
* coalesces the store base onto $a0 (`sh v0,2(a0)`) and re-emits the arg copy,
|
||||
* giving a 6-instruction ADDRESSING/cse diff. Moved above the call; both stores
|
||||
* now retire off $s0 and the sh lands in the jal delay slot, as in the target. */
|
||||
|
||||
extern s32 func_8012C354(s32 a0, s32 a1);
|
||||
extern void func_8012A828(s32, s32);
|
||||
extern s32 func_801788B8(s32 arg0, s32 arg1);
|
||||
|
||||
extern void func_80189CF0(void);
|
||||
|
||||
void func_80189BF8(s32 a0) {
|
||||
|
||||
extern M2C_UNK D_801DE278;
|
||||
extern u8 D_8018AEDC[];
|
||||
s32 s0 = a0;
|
||||
if (func_8012C354(a0, (s32)&D_801DE278)) {
|
||||
*(u8 *)(s0 + 0xC0) = 1;
|
||||
*(u16 *)(s0 + 0x2) = 1;
|
||||
((void (*)(s32*, s32))func_8012A828)((s32 *)s0, (s32)D_8018AEDC);
|
||||
func_801788B8(s0, (s32)func_80189CF0);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void func_80189C5C(void) {
|
||||
}
|
||||
|
||||
|
||||
extern void func_80178CBC(s32 *a0, s32 a1);
|
||||
|
||||
void func_80189C64(s32 *a0)
|
||||
{
|
||||
|
||||
extern signed char D_801DE368[];
|
||||
s32 v0;
|
||||
|
||||
v0 = *(s16 *)((s32)a0 + 0x70);
|
||||
v0 = v0 * 4;
|
||||
func_80178CBC(a0, *(s32 *)((s32)D_801DE368 + v0));
|
||||
*(s16 *)((s32)a0 + 0x2) = 0x3;
|
||||
}
|
||||
|
||||
|
||||
|
||||
extern int func_80178970(void);
|
||||
extern void func_80178D18(void);
|
||||
|
||||
void func_80189CB0(s32 a0) {
|
||||
if (func_80178970() != 0) {
|
||||
((void (*)(s32))func_80178D18)(a0);
|
||||
*(s16 *)(a0 + 2) = 1;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_124/nonmatchings/ov_SC03_124_jr_80187010", func_80189CF0);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_124/nonmatchings/ov_SC03_124_jr_80187010", func_80189D4C);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_124/nonmatchings/ov_SC03_124_jr_80187010", func_80189F00);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_124/nonmatchings/ov_SC03_124_jr_80187010", func_8018A250);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_124/nonmatchings/ov_SC03_124_jr_80187010", func_8018A3C8);
|
||||
|
||||
|
||||
extern void func_8012E8E0(s32 a0, s32 a1);
|
||||
|
||||
void func_8018A470(s32 arg0)
|
||||
{
|
||||
|
||||
extern s32 D_801DE4EC;
|
||||
s32 v1;
|
||||
|
||||
*(short *)(arg0 + 0x2) = 3;
|
||||
*(short *)(arg0 + 0x34) = 0;
|
||||
func_8012E8E0(arg0, (s32)&D_801DE4EC);
|
||||
v1 = *(s32 *)(arg0 + 0x68);
|
||||
*(short *)(v1 + 0xC) = 0x7FFF;
|
||||
}
|
||||
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_124/nonmatchings/ov_SC03_124_jr_80187010", func_8018A4B8);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_124/nonmatchings/ov_SC03_124_jr_80187010", func_8018A594);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_124/nonmatchings/ov_SC03_124_jr_80187010", func_8018A5B8);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_124/nonmatchings/ov_SC03_124_jr_80187010", func_8018A61C);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
extern void func_80131E00(struct S80131E00 *a0, s32 a1);
|
||||
void func_8018A698(void)
|
||||
{
|
||||
int new_var;
|
||||
((void (*)(s32, s32)) func_80131E00)(new_var, 3);
|
||||
new_var = 0x80C70000;
|
||||
}
|
||||
|
||||
void func_8018A6B8(void) {
|
||||
}
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_124/nonmatchings/ov_SC03_124_jr_80187010", func_8018A6C0);
|
||||
|
||||
INCLUDE_ASM("asm/ov_SC03_124/nonmatchings/ov_SC03_124_jr_80187010", func_8018A788);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user