phase-36: S104 checkpoint — d1–d19 all at 0, generators R27–R34, census 4,732 / 0 unmarked (exit 0), R22 218/218; d20–d24 in flight; METHOD step 14 | 🛑 T7 RUNNING

This commit is contained in:
Drew T
2026-09-10 22:51:40 -06:00
parent 13069c142d
commit eadfa5977d
44 changed files with 3569 additions and 91 deletions
+17
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@@ -147,3 +147,20 @@
(`c-typeck.c:2418-2450` short_shift re-extends; cse folds that pair instead, `cse.c:5577-5667`); never the declaration.
- Copies of your class under OTHER names in other TUs close with the same text almost always — find them by grepping a
distinctive line and `--try` each (d7, d9, d11, d12, d13, d15 all did).
14. **S104's third wave (d14, d16–d19), all at 0 with ZERO levers — and a pattern across the session:**
- **FOUR of nineteen closes were a goto chain rewritten as STRUCTURED C** (d3 if/else, d9 `||`, d11 ternary condition,
d17 `switch` + a `for` with `continue`). The tree's bodies are decompiler goto text; no generator reaches a structured
shape. If your body has `goto`/labels, try the structured spelling EARLY.
- (d17) a do-while's return path `bnez …,<epilogue>; move v0,<ret>` vs the target's `beqz …; <increment in slot>` →
write the loop as `for (…; …; count++, p += K)` with `continue`: a rotated for/while emits `NOTE_INSN_LOOP_VTOP`
(`jump.c:2306`), which flips reorg's `mostly_true_jump` (`reorg.c:1364-1372`). A hoisted copy of a parameter living past
the parameter's last use makes cse re-route reads through it (`cse.c:846-862`) — delete the copy.
- (d14) a register residual in a LATE block where the target keeps late values in the same registers as unrelated
EARLY variables → the original REUSED those variables: rename each late local to an earlier-dead one (enumerate;
`combine_regs` refuses a pseudo that dies in several places, `local-alloc.c:1845`). (d19) a walked pointer vs counter
`$s0/$s1` swap → make other loops' index the losing counter (raises its `allocno_compare` priority, `global.c:595-599`).
- (d16, d18) a walked destination/secondary pointer (`dst`, `s1 = p + K` stepped alongside `p`) → index the array by the
loop counter / write the accesses as `p + K + off`: all addresses become givs of one biv and combine into one register
(`record_giv` `loop.c:4341`, `combine_givs` `:5494`). A `$0` pin on `y = x + zr` → declare `y` at the proven width.
- Enumerating cheap spellings (d14: 365 bodies in ~3 min through `--try`) beats reasoning when the residual is a
register permutation; `alloc_table.py` explains afterwards.
+5 -4
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@@ -1,5 +1,6 @@
rank fn alias copies best needed kinds regs tu
2 func_80189030 ov_SC03_001 3 13 1 keepalive src/ov_SC03_001/ov_SC03_001_jr_80189030.c
125 func_80181DAC ov_SC04_004 3 16 2 keepalive,pin $0 src/ov_SC04_004/ov_SC04_004_jr_8017AE2C.c
25 func_8017BF50 ov_SC03_124 3 21 1 pin $17 src/ov_SC03_124/ov_SC03_124_jr_8017AE2C.c
81 func_8017F368 ov_SC03_001 4 40 2 pin $0,$4 src/ov_SC03_001/ov_SC03_001_jr_8017AE2C.c
61 func_801861FC ov_SC03_091 4 9 1 pin $2 src/ov_SC03_091/ov_SC03_091_jr_8018326C.c
36 func_8018003C ov_SC02_016 4 9 4 pin $0,$17,$5,$6 src/ov_SC02_016/ov_SC02_016_jr_8017DC70.c
57 func_80181864 ov_SC03_113 4 21 3 barrier,launder src/ov_SC03_113/ov_SC03_113_jr_8017C294.c
68 func_80180324 ov_SC04_007 7 43 8 cast,keepalive,pin $0 src/ov_SC04_007/ov_SC04_007_jr_8017BEBC.c
85 func_8018179C ov_SC06_010 4 63 2 pin $16,$4 src/ov_SC06_010/ov_SC06_010_jr_8017A4AC.c
1 rank fn alias copies best needed kinds regs tu
2 2 61 func_80189030 func_801861FC ov_SC03_001 ov_SC03_091 3 4 13 9 1 keepalive pin $2 src/ov_SC03_001/ov_SC03_001_jr_80189030.c src/ov_SC03_091/ov_SC03_091_jr_8018326C.c
3 125 36 func_80181DAC func_8018003C ov_SC04_004 ov_SC02_016 3 4 16 9 2 4 keepalive,pin pin $0 $0,$17,$5,$6 src/ov_SC04_004/ov_SC04_004_jr_8017AE2C.c src/ov_SC02_016/ov_SC02_016_jr_8017DC70.c
4 25 57 func_8017BF50 func_80181864 ov_SC03_124 ov_SC03_113 3 4 21 1 3 pin barrier,launder $17 src/ov_SC03_124/ov_SC03_124_jr_8017AE2C.c src/ov_SC03_113/ov_SC03_113_jr_8017C294.c
5 81 68 func_8017F368 func_80180324 ov_SC03_001 ov_SC04_007 4 7 40 43 2 8 pin cast,keepalive,pin $0,$4 $0 src/ov_SC03_001/ov_SC03_001_jr_8017AE2C.c src/ov_SC04_007/ov_SC04_007_jr_8017BEBC.c
6 85 func_8018179C ov_SC06_010 4 63 2 pin $16,$4 src/ov_SC06_010/ov_SC06_010_jr_8017A4AC.c
@@ -0,0 +1,26 @@
void func_8018003C(s32 arg0)
{
s32 obj;
s32 v;
obj = *(s32 *)(arg0 + 0x20);
*(s32 *)(arg0 + 0x10) += *(s32 *)(arg0 + 0x2C);
*(s32 *)(arg0 + 0x14) += *(s32 *)(arg0 + 0x30);
*(s32 *)(arg0 + 0x18) += *(s32 *)(arg0 + 0x34);
func_8012931C((struct vec *)arg0);
v = *(u16 *)(obj + 0x1A) - 0x100;
*(u16 *)(obj + 0x1A) = v;
*(u16 *)(obj + 0x18) = v;
if (func_80128ED8(obj, (s32 *)(arg0 + 0x24)) != 0) {
func_801292C8((u8 *)arg0);
} else {
v = *(s32 *)(arg0 + 0x1C);
if (v != 0) {
v--;
*(s32 *)(arg0 + 0x1C) = v;
if (v == 0) {
func_801292C8((u8 *)arg0);
}
}
}
}
@@ -0,0 +1,57 @@
void func_8018003C(s32 arg0)
{
s32 s1 = arg0;
s32 s0;
s32 v0;
s32 v1;
s32 a0;
s32 a1;
s32 a2;
v0 = *(s32 *)(s1 + 0x10);
v1 = *(s32 *)(s1 + 0x2C);
a1 = *(s32 *)(s1 + 0x30);
a2 = *(s32 *)(s1 + 0x34);
s0 = *(s32 *)(s1 + 0x20);
v0 = v0 + v1;
*(s32 *)(s1 + 0x10) = v0;
v0 = *(s32 *)(s1 + 0x14);
v1 = *(s32 *)(s1 + 0x18);
v0 = v0 + a1;
v1 = v1 + a2;
*(s32 *)(s1 + 0x14) = v0;
*(s32 *)(s1 + 0x18) = v1;
((void (*)(void))func_8012931C)();
a0 = s0 + 0;
v0 = *(u16 *)(s0 + 0x1A);
v0 = v0 - 0x100;
*(u16 *)(a0 + 0x1A) = (u16)v0;
*(u16 *)(a0 + 0x18) = (u16)v0;
if (func_80128ED8(a0, (s32 *)(s1 + 0x24)) != 0) {
func_801292C8((u8 *)s1);
} else {
v0 = *(s32 *)(s1 + 0x1C);
if (v0 != 0) {
v0--;
*(s32 *)(s1 + 0x1C) = v0;
if (v0 == 0) {
func_801292C8((u8 *)s1);
}
}
}
}
@@ -0,0 +1,58 @@
void func_8018003C(s32 arg0)
{
register s32 s1 __asm__("$17") = arg0; // !FAKE: pin $17 — NEEDED DIFFERS (P36 rung B tus8)
s32 s0;
s32 v0;
s32 v1;
s32 a0;
register s32 a1 __asm__("$5"); // !FAKE: pin $5 — NEEDED DIFFERS (P36 rung B tus8)
register s32 a2 __asm__("$6"); // !FAKE: pin $6 — NEEDED DIFFERS (P36 rung B tus8)
register s32 zr __asm__("$0"); // !FAKE: pin $0 — NEEDED DIFFERS (P36 rung B tus8)
v0 = *(s32 *)(s1 + 0x10);
v1 = *(s32 *)(s1 + 0x2C);
a1 = *(s32 *)(s1 + 0x30);
a2 = *(s32 *)(s1 + 0x34);
s0 = *(s32 *)(s1 + 0x20);
v0 = v0 + v1;
*(s32 *)(s1 + 0x10) = v0;
v0 = *(s32 *)(s1 + 0x14);
v1 = *(s32 *)(s1 + 0x18);
v0 = v0 + a1;
v1 = v1 + a2;
*(s32 *)(s1 + 0x14) = v0;
*(s32 *)(s1 + 0x18) = v1;
((void (*)(void))func_8012931C)();
a0 = s0 + zr;
v0 = *(u16 *)(s0 + 0x1A);
v0 = v0 - 0x100;
*(u16 *)(a0 + 0x1A) = (u16)v0;
*(u16 *)(a0 + 0x18) = (u16)v0;
if (func_80128ED8(a0, (s32 *)(s1 + 0x24)) != 0) {
func_801292C8((u8 *)s1);
} else {
v0 = *(s32 *)(s1 + 0x1C);
if (v0 != 0) {
v0--;
*(s32 *)(s1 + 0x1C) = v0;
if (v0 == 0) {
func_801292C8((u8 *)s1);
}
}
}
}
@@ -0,0 +1,14 @@
g6: verdict NO-MATCH start 36 best 9 compiles 333 path R7 do-while @3956 + R6 inline v0 @3966 + R6 inline v0 @3962
best-scoring single candidates of the last trace (move -> score [residual class]):
R6 inline v0 @3962 -> 9 [COUNT] (from 21)
R6 inline v0 @3966 -> 9 [COUNT] (from 22)
R14 param-width arg0 s32->s16 @3942 -> 11 [COUNT] (from 21)
R6 inline v0 @3953 -> 11 [COUNT] (from 21)
R7 do-while @3982 -> 15 [COUNT] (from 21)
R6 inline v0 @3981 -> 18 [COUNT] (from 21)
R9 swap-stmts @3981 -> 18 [COUNT] (from 21)
R6 inline v1 @3967 -> 19 [COUNT] (from 22)
R6 inline v1 @3955 -> 20 [COUNT] (from 21)
R9 swap-stmts @3967 -> 20 [COUNT] (from 22)
R6 inline v0 @3966 -> 21 [COUNT] (from 23)
R8 cse tmp0 @3982 -> 21 [COUNT] (from 23)
@@ -0,0 +1,7 @@
--- every @class/@stuck/@crack note in this translation unit ---
// @class: schedule
// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// @class: regalloc-order
// @stuck: none — MATCH
// @class: struct
// @stuck: none — MATCH (fn-ptr table %lo-fold via extern array of code ptrs)
@@ -0,0 +1,62 @@
=== lever-free bodies in ov_SC02_016 sharing a callee or global with func_8018003C (12 found; top 6 by shared symbols) — read them for the SHAPE ===
--- func_801433F0 (src/shared/ov/func_801433F0.h:7) shares 3: func_80128ED8 func_801292C8 func_8012931C ---
void func_801433F0(s32 a0) {
if (*(u16 *)(a0 + 2) == 0) {
func_80143458();
} else {
func_8012931C((struct vec *)a0);
if (func_80128ED8(*(void **)(a0 + 0x20), (u8 *)a0 + 0x24) != 0) {
func_801292C8((u8 *)a0);
}
}
}
--- func_8014350C (src/shared/ov/func_8014350C.h:7) shares 3: func_80128ED8 func_801292C8 func_8012931C ---
void func_8014350C(s32 *a0) {
if (*(u16 *)((u8 *)a0 + 2) == 0) {
func_8014358C();
return;
}
func_8012931C((struct vec *)a0);
if (func_80128ED8((void *)a0[0x20 / 4], (void *)((u8 *)a0 + 0x24)) != 0) {
func_801292C8((u8 *)a0);
return;
}
*(u8 *)(a0[0x20 / 4] + 0x27) = *(u8 *)((u8 *)a0 + 0x28) - 0x70;
}
--- func_80169FE0 (src/shared/ov/func_80169FE0.h:5) shares 1: func_80128ED8 ---
void func_80169FE0(s32 a0) {
if (func_80128ED8((void *)*(s32 *)(a0 + 0x20), (void *)(a0 + 0x24)) != 0) {
((void (*)(s32))func_80146C3C)(a0);
}
}
--- func_8016DEE0 (src/shared/ov/func_8016DEE0.h:5) shares 1: func_80128ED8 ---
void func_8016DEE0(s32 a0) {
if (func_80128ED8((void *)*(s32 *)(a0 + 0x20), (void *)(a0 + 0x24)) != 0) {
((void (*)(s32))func_80146C3C)(a0);
}
}
--- func_8012927C (src/shared/ov/func_8012927C.h:5) shares 1: func_801292C8 ---
void func_8012927C(void) {
s32 i;
u8 *p = (u8 *)&D_8011DB30;
for (i = 0; i < 0x80; i++) {
func_801292C8(p);
p += 0x38;
}
}
--- func_801665B4 (src/shared/ov/func_801665B4.h:6) shares 1: func_80128ED8 ---
void func_801665B4(s32 *a0)
{
if (func_80128ED8((void *)a0[8], (void *)(a0 + 9))) {
func_80146C3C((s32)a0);
} else {
func_800D22E4((s32)a0);
a0[5] -= a0[5] >> 3;
}
}
@@ -0,0 +1,44 @@
src/ov_SC02_016/ov_SC02_016_jr_8017DC70.c:func_8018003C: score 36 (COUNT; mine 44 ins, target 42) — not yet
register pairs (mine -> target, count): a1->v0 x8, a0->v1 x6, v0->a1 x2, v1->a2 x2
replace mine[5:9] target[5:9]
5 lw a1,16(s1) | lw v0,16(s1)
6 lw a0,44(s1) | lw v1,44(s1)
7 lw v0,48(s1) | lw a1,48(s1)
8 lw v1,52(s1) | lw a2,52(s1)
replace mine[10:17] target[10:17]
10 addu a1,a1,a0 | addu v0,v0,v1
11 sw a1,16(s1) | sw v0,16(s1)
12 lw a1,20(s1) | lw v0,20(s1)
13 lw a0,24(s1) | lw v1,24(s1)
14 addu a1,a1,v0 | addu v0,v0,a1
15 addu a0,a0,v1 | addu v1,v1,a2
16 sw a1,20(s1) | sw v0,20(s1)
replace mine[18:19] target[18:19]
18 sw a0,24(s1) | sw v1,24(s1)
replace mine[20:25] target[20:24]
20 lhu a1,26(s0) | lhu v0,26(s0)
21 move s0,s1 | addiu a1,s1,36
22 addiu a1,a1,-256 | addiu v0,v0,-256
23 sh a1,26(a0) | sh v0,26(a0)
24 sh a1,24(a0) | --
replace mine[26:28] target[25:35]
26 addiu a1,s1,36 | sh v0,24(a0)
27 bnez v0,245c <func_8018003C+0x90> | bnez v0,2454 <func_8018003C+0x88>
28 -- | nop
29 -- | lw v0,28(s1)
30 -- | nop
31 -- | beqz v0,245c <func_8018003C+0x90>
32 -- | addiu v0,v0,-1
33 -- | bnez v0,245c <func_8018003C+0x90>
34 -- | sw v0,28(s1)
35 -- | jal 0 <func_8017DC70>
delete mine[29:38] target[36:36]
29 lw a1,28(s0) | --
30 nop | --
31 beqz a1,2464 <func_8018003C+0x98> | --
32 addiu a1,a1,-1 | --
33 bnez a1,2464 <func_8018003C+0x98> | --
34 sw a1,28(s0) | --
35 move a0,s0 | --
36 jal 0 <func_8017DC70> | --
37 nop | --
@@ -0,0 +1,8 @@
NEEDED pin $17 line 4070
REMOVED pin $16 line 4071
REMOVED pin $2 line 4072
REMOVED pin $3 line 4073
REMOVED pin $4 line 4074
NEEDED pin $5 line 4075
NEEDED pin $6 line 4076
NEEDED pin $0 line 4077
@@ -0,0 +1,2 @@
src/ov_SC02_016/ov_SC02_016_jr_8017DC70.c
func_8018003C
@@ -0,0 +1,47 @@
void func_801861FC(s32 a0) {
s32 ent = a0;
s32 state = *(u16 *)(ent + 0x34);
s32 sub;
s32 cnt;
switch (state) {
case 0: {
s32 t = func_8004787C(*(s32 *)(ent + 0x1C) << 6);
*(s16 *)(*(s32 *)(ent + 0x20) + 0x18) = t * 7;
sub = *(s32 *)(ent + 0x20);
*(s16 *)(sub + 0x1A) = t << 1;
cnt = *(s32 *)(ent + 0x1C) + 1;
*(s32 *)(ent + 0x1C) = cnt;
if (cnt < 0x10) {
break;
}
sub = *(s32 *)(ent + 0x20);
*(s16 *)(sub + 0x1A) = 0x7000;
sub = *(s32 *)(ent + 0x20);
*(s16 *)(sub + 0x1A) = 0x2000;
*(s32 *)(ent + 0x1C) = 0x40;
*(u16 *)(ent + 0x34) = *(u16 *)(ent + 0x34) + 1;
break;
}
case 1:
if (func_8012BEE8(ent) != 0) {
*(s32 *)(ent + 0x1C) = 0x10;
*(u16 *)(ent + 0x34) = *(u16 *)(ent + 0x34) + 1;
}
break;
case 2: {
s32 t = func_8004787C(*(s32 *)(ent + 0x1C) << 6);
sub = *(s32 *)(ent + 0x20);
*(s16 *)(sub + 0x1A) = t << 1;
cnt = *(s32 *)(ent + 0x1C) - 1;
*(s32 *)(ent + 0x1C) = cnt;
if (cnt == 0) {
func_8012C218((void *)ent);
return;
}
break;
}
}
func_8018632C(ent);
}
@@ -0,0 +1,46 @@
void func_801861FC(s32 a0) {
s32 ent = a0;
s32 state = *(u16 *)(ent + 0x34);
s32 sub;
s32 t;
s32 cnt;
switch (state) {
case 0:
t = func_8004787C(*(s32 *)(ent + 0x1C) << 6);
*(s16 *)(*(s32 *)(ent + 0x20) + 0x18) = t * 7;
sub = *(s32 *)(ent + 0x20);
*(s16 *)(sub + 0x1A) = t << 1;
cnt = *(s32 *)(ent + 0x1C) + 1;
*(s32 *)(ent + 0x1C) = cnt;
if (cnt < 0x10) {
break;
}
sub = *(s32 *)(ent + 0x20);
*(s16 *)(sub + 0x1A) = 0x7000;
sub = *(s32 *)(ent + 0x20);
*(s16 *)(sub + 0x1A) = 0x2000;
*(s32 *)(ent + 0x1C) = 0x40;
*(u16 *)(ent + 0x34) = *(u16 *)(ent + 0x34) + 1;
break;
case 1:
if (func_8012BEE8(ent) != 0) {
*(s32 *)(ent + 0x1C) = 0x10;
*(u16 *)(ent + 0x34) = *(u16 *)(ent + 0x34) + 1;
}
break;
case 2:
t = func_8004787C(*(s32 *)(ent + 0x1C) << 6);
sub = *(s32 *)(ent + 0x20);
*(s16 *)(sub + 0x1A) = t << 1;
cnt = *(s32 *)(ent + 0x1C) - 1;
*(s32 *)(ent + 0x1C) = cnt;
if (cnt == 0) {
func_8012C218((void *)ent);
return;
}
break;
}
func_8018632C(ent);
}
@@ -0,0 +1,46 @@
void func_801861FC(s32 a0) {
s32 ent = a0;
s32 state = *(u16 *)(ent + 0x34);
s32 sub;
register s32 t __asm__("$2"); // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B tus9)
s32 cnt;
switch (state) {
case 0:
t = func_8004787C(*(s32 *)(ent + 0x1C) << 6);
*(s16 *)(*(s32 *)(ent + 0x20) + 0x18) = t * 7;
sub = *(s32 *)(ent + 0x20);
*(s16 *)(sub + 0x1A) = t << 1;
cnt = *(s32 *)(ent + 0x1C) + 1;
*(s32 *)(ent + 0x1C) = cnt;
if (cnt < 0x10) {
break;
}
sub = *(s32 *)(ent + 0x20);
*(s16 *)(sub + 0x1A) = 0x7000;
sub = *(s32 *)(ent + 0x20);
*(s16 *)(sub + 0x1A) = 0x2000;
*(s32 *)(ent + 0x1C) = 0x40;
*(u16 *)(ent + 0x34) = *(u16 *)(ent + 0x34) + 1;
break;
case 1:
if (func_8012BEE8(ent) != 0) {
*(s32 *)(ent + 0x1C) = 0x10;
*(u16 *)(ent + 0x34) = *(u16 *)(ent + 0x34) + 1;
}
break;
case 2:
t = func_8004787C(*(s32 *)(ent + 0x1C) << 6);
sub = *(s32 *)(ent + 0x20);
*(s16 *)(sub + 0x1A) = t << 1;
cnt = *(s32 *)(ent + 0x1C) - 1;
*(s32 *)(ent + 0x1C) = cnt;
if (cnt == 0) {
func_8012C218((void *)ent);
return;
}
break;
}
func_8018632C(ent);
}
@@ -0,0 +1,14 @@
g6: verdict NO-MATCH start 15 best 9 compiles 324 path R9 swap-stmts @4725 + R6 inline sub @4748 + R6 inline sub @4735
best-scoring single candidates of the last trace (move -> score [residual class]):
R6 inline sub @4735 -> 9 [COUNT] (from 11)
R6 inline sub @4733 -> 9 [COUNT] (from 11)
R6 inline sub @4733 -> 9 [COUNT] (from 11)
R6 inline sub @4748 -> 11 [COUNT] (from 13)
R6 inline sub @4735 -> 11 [COUNT] (from 13)
R6 inline sub @4733 -> 11 [COUNT] (from 13)
R8 temp tmp0 @4728 -> 11 [COUNT] (from 11)
R7 block @4737 -> 11 [COUNT] (from 11)
R9 swap-stmts @4737 -> 11 [COUNT] (from 11)
R4 decl-move t 3->0 -> 11 [COUNT] (from 11)
R8 base tmp0 @4728 -> 11 [COUNT] (from 11)
R4 decl-move t 3->1 -> 11 [COUNT] (from 11)
@@ -0,0 +1 @@
@@ -0,0 +1,232 @@
=== lever-free bodies in ov_SC03_091 sharing a callee or global with func_801861FC (65 found; top 6 by shared symbols) — read them for the SHAPE ===
--- func_801867DC (src/ov_SC03_091/ov_SC03_091_jr_8018326C.c:4989) shares 2: func_8012BEE8 func_8012C218 ---
void func_801867DC(s32 param_1) {
*(u16 *)(*(s32 *)(param_1 + 0x20) + 0x10) =
*(u16 *)(*(s32 *)(param_1 + 0x20) + 0x10) + 0x40;
if (((s32 (*)(s32))func_8012CBCC)(param_1) != 0 || func_8012BEE8(param_1) != 0) {
func_8012C218((void *)param_1);
} else {
func_80017274(param_1 + 0xDC, *(s32 *)(param_1 + 0x20) + 0x34);
}
}
--- func_80144458 (src/ov_SC03_091/ov_SC03_091_jr_80140608.c:2236) shares 2: func_8004787C func_8012C218 ---
void func_80144458(void *arg0) {
s32 temp_s0;
void *temp_s2;
void *temp_v0;
temp_s2 = M2C_FIELD(arg0, void **, 0xCC);
if (M2C_FIELD(arg0, s16 *, 0x70) == 0) {
temp_v0 = M2C_FIELD(M2C_FIELD(arg0, void **, 0x64), void **, 0x20);
if (temp_v0 != NULL) {
temp_s0 = (M2C_FIELD(temp_v0, s16 *, 0x12) - 0x400) & 0xFFF;
M2C_FIELD(arg0, s32 *, 0x10) = (s32) (func_80047948(temp_s0) * D_8018E25C * 0x10);
M2C_FIELD(arg0, s32 *, 0x18) = (s32) (func_8004787C(temp_s0) * -D_8018E25C * 0x10);
func_8012AD80(arg0);
}
}
M2C_FIELD(temp_s2, u16 *, 8) = (u16) M2C_FIELD(arg0, u16 *, 6);
M2C_FIELD(temp_s2, u16 *, 0xA) = (u16) M2C_FIELD(arg0, u16 *, 0xA);
M2C_FIELD(temp_s2, u16 *, 0xC) = (u16) M2C_FIELD(arg0, u16 *, 0xE);
if (func_80128ED8(temp_s2, arg0 + 0xD0) != 0) {
func_80016714(temp_s2, 0x38);
func_8012C218(arg0);
}
}
--- func_80143D28 (src/ov_SC03_091/ov_SC03_091_jr_80140608.c:2096) shares 2: func_8012BEE8 func_8012C218 ---
void func_80143D28(s32 param_1) {
extern MatEntry D_8018E28C[];
s32 iVar2 = *(s32 *)(param_1 + 0x64); /* $s1 */
MatEntry *p = &D_8018E28C[*(s16 *)(param_1 + 0x70)];
u16 uVar5 = p->f8;
s32 iVar3 = *(s32 *)(param_1 + 0x20);
s32 sVar4;
s32 iVar1;
*(s16 *)(iVar3 + 0x14) = uVar5;
*(u16 *)(iVar3 + 0x12) = *(u16 *)(iVar3 + 0x12) + p->fa;
sVar4 = 0x1000;
((void (*)(void *, void *, void *))ApplyMatrixSV)((void *)(*(s32 *)(param_1 + 0x20) + 0x34), p, (void *)(param_1 + 0x50));
if (*(s16 *)(param_1 + 0xfe) == 0 &&
(iVar2 == 0 || *(s16 *)(iVar2 + 0x36) != *(s16 *)(param_1 + 0xfc) ||
*(u8 *)(iVar2 + 0xc1) != 6)) {
if (0x10 < *(s32 *)(param_1 + 0x1c)) {
*(s32 *)(param_1 + 0x1c) = 0x10;
}
*(s16 *)(param_1 + 0xfe) = 1;
}
iVar1 = *(s32 *)(param_1 + 0x1c);
if (iVar1 < 0x11) {
sVar4 = iVar1 << 8;
}
if (0x73 < iVar1) {
sVar4 = (0x78 - iVar1) << 10;
}
*(s16 *)(iVar3 + 0x18) = *(s16 *)(iVar3 + 0x1a) = *(s16 *)(iVar3 + 0x1c) = sVar4;
if (func_8012BEE8(param_1)) {
func_8012C218((void *)param_1);
}
}
--- func_80143EBC (src/shared/ov/func_80143EBC.h:11) shares 2: func_8004787C func_8012C218 ---
void func_80143EBC(s32 a0) {
s32 s1 = *(s32 *)(a0 + 0x64);
s32 s0 = *(s32 *)(a0 + 0xCC);
s16 sp[3];
s32 v0;
if (*(s16 *)(s1 + 0x36) != *(s16 *)(a0 + 0xFC)) {
if (a0 == 0) {
return;
}
func_80016714((void *)s0, 0x38);
func_8012C218((void *)a0);
return;
}
sp[0] = *(u16 *)(s1 + 6);
sp[1] = *(u16 *)(s1 + 0xA) - 0x10;
sp[2] = *(u16 *)(s1 + 0xE);
if (func_80134510((s32)&sp[0]) == 0) {
*(s32 *)(s0 + 4) = *(s32 *)(s0 + 4) | 0x80000000;
return;
}
*(s16 *)(s0 + 8) = sp[0];
*(s16 *)(s0 + 0xA) = sp[1];
*(s16 *)(s0 + 0xC) = sp[2];
*(s32 *)(s0 + 4) = *(s32 *)(s0 + 4) & 0x7FFFFFFF;
if (*(s16 *)(a0 + 0x70) == 1) {
*(s16 *)(s0 + 0x10) = 0x400;
*(s16 *)(s0 + 0x12) = 0;
} else {
*(s16 *)(s0 + 0x10) = ratan2(D_801152AC, D_801152AA) + 0x400;
*(s16 *)(s0 + 0x12) = ratan2(*(s16 *)D_801152A8, D_801152AA);
}
v0 = *(s32 *)(s1 + 0x20);
*(s16 *)(s0 + 0x14) = -(*(u16 *)(v0 + 0x12));
v0 = *(s32 *)(s1 + 0x20);
*(s16 *)(s0 + 0x18) = func_8004787C((*(u16 *)(v0 + 0x14) & 0x3FF) << 1) + 0x4000;
v0 = *(s32 *)(s1 + 0x20);
*(s16 *)(s0 + 0x1A) = func_8004787C((*(u16 *)(v0 + 0x10) & 0x3FF) << 1) + 0x4000;
}
--- func_80186A8C (src/ov_SC03_091/ov_SC03_091_jr_8018326C.c:5178) shares 2: func_8004787C func_8012BEE8 ---
void func_80186A8C(s32 a0) {
extern u8 D_800AF630[];
extern s32 D_801A8C0C[];
s32 pad[4]; /* idiom 6: 16 bytes of dead locals at sp+0x10 => frame 0x30 */
u8 *m = D_800AF630;
s32 ang;
s32 off;
s32 base;
ang = func_8004787C(*(s32 *)(a0 + 0xE4));
if (*(s16 *)(a0 + 0xAA) == 0) {
*(s16 *)(*(s32 *)(a0 + 0x20) + 0x18) = (ang >> 2) + 0x1000;
*(s16 *)(*(s32 *)(a0 + 0x20) + 0x1A) = 0x1000 - (ang >> 1);
*(s16 *)(*(s32 *)(a0 + 0x20) + 0x1C) = (ang >> 1) + 0x1000;
} else {
*(s16 *)(*(s32 *)(a0 + 0x20) + 0x18) = (ang >> 3) + 0x700;
*(s16 *)(*(s32 *)(a0 + 0x20) + 0x1A) = 0x700 - (ang >> 2);
*(s16 *)(*(s32 *)(a0 + 0x20) + 0x1C) = (ang >> 2) + 0x700;
}
if (*(u16 *)(m + 0xA3AA) % *(s16 *)(a0 + 0xFE) == 0) {
*(u16 *)(*(s32 *)(a0 + 0x20) + 0x12) =
*(u16 *)(*(s32 *)(a0 + 0x20) + 0x12) + func_8012B8E4(a0, 0x20);
}
switch (*(u16 *)(a0 + 0x34)) {
case 0: {
s32 t;
s32 r;
if (ang >= 0) {
t = -(ang << 4) - 0x4000;
} else {
t = (ang << 4) - 0x4000;
}
func_8012B178(a0, t);
r = ((s32 (*)(s32))func_8012CBA4)(a0);
if (r & 0x8000) {
*(u16 *)(a0 + 0x34) = 2;
*(s32 *)(a0 + 0xE0) = *(s16 *)(*(s32 *)(a0 + 0x20) + 0x12) + 0x800;
*(s32 *)(a0 + 0x1C) = rand() % 10 + 0x14;
} else if ((r & 0x2000) == 0) {
func_8012ADE4((u8 *)a0);
*(u16 *)(a0 + 0x34) = 2;
*(s32 *)(a0 + 0xE0) = *(s16 *)(*(s32 *)(a0 + 0x20) + 0x12) + 0x800;
*(s32 *)(a0 + 0x1C) = rand() % 10 + 0x14;
} else if (--*(s32 *)(a0 + 0xE8) == 0) {
if (rand() & 1) {
s32 v;
*(u16 *)(a0 + 0x34) = 1;
*(s32 *)(a0 + 0x1C) = 0x20;
off = rand() % 1024;
base = *(s16 *)(*(s32 *)(a0 + 0x20) + 0x12);
if ((rand() & 1) == 0) {
v = base - off;
} else {
v = base + off;
}
*(s32 *)(a0 + 0xE0) = v;
} else {
*(s32 *)(a0 + 0xE8) = 0x40;
}
}
break;
}
case 1: {
s32 t;
s32 d = func_8012B608(*(s16 *)(*(s32 *)(a0 + 0x20) + 0x12),
*(s32 *)(a0 + 0xE0), 0x14);
*(u16 *)(*(s32 *)(a0 + 0x20) + 0x12) =
*(u16 *)(*(s32 *)(a0 + 0x20) + 0x12) + d;
if (ang >= 0) {
t = -(ang << 4) - 0x4000;
} else {
t = (ang << 4) - 0x4000;
}
func_8012B178(a0, t);
if ((((s32 (*)(s32))func_8012CBA4)(a0) & 0x2000) == 0) {
func_8012ADE4((u8 *)a0);
*(u16 *)(a0 + 0x34) = 2;
*(s32 *)(a0 + 0xE0) = *(s16 *)(*(s32 *)(a0 + 0x20) + 0x12) + 0x800;
*(s32 *)(a0 + 0x1C) = rand() % 10 + 0x14;
} else if (func_8012BEE8(a0) != 0) {
*(u16 *)(a0 + 0x34) = 0;
*(s32 *)(a0 + 0xE8) = 0x40;
}
break;
}
case 2: {
s32 d = func_8012B608(*(s16 *)(*(s32 *)(a0 + 0x20) + 0x12),
*(s32 *)(a0 + 0xE0), 0x14);
*(u16 *)(*(s32 *)(a0 + 0x20) + 0x12) =
*(u16 *)(*(s32 *)(a0 + 0x20) + 0x12) + d;
if (func_8012BEE8(a0) != 0) {
*(u16 *)(a0 + 0x34) = 0;
func_8012B030((u8 *)a0);
}
break;
}
}
func_801877EC(a0);
func_8018771C(a0, D_801A8C0C[*(u16 *)(a0 + 0x70) & 0xF]);
*(s32 *)(a0 + 0xE4) = (*(s32 *)(a0 + 0xE4) + 0x40) & 0x7FF;
if (*(s32 *)(a0 + 0x14) > 0x100000) {
*(s32 *)(a0 + 0x14) = 0x100000;
}
}
--- func_8017CC60 (src/shared/ov/func_8017CC60.h:4) shares 1: func_8012C218 ---
void func_8017CC60(void) {
((void (*)(void))func_8012C218)();
}
@@ -0,0 +1,25 @@
src/ov_SC03_091/ov_SC03_091_jr_8018326C.c:func_801861FC: score 15 (COUNT; mine 77 ins, target 76) — not yet
replace mine[6:7] target[6:7]
6 beq v1,v0,3048 <func_801861FC+0xb8> | beq v1,v0,3044 <func_801861FC+0xb4>
replace mine[12:13] target[12:13]
12 j 30a8 <func_801861FC+0x118> | j 30a4 <func_801861FC+0x114>
replace mine[15:16] target[15:16]
15 beq v1,v0,306c <func_801861FC+0xdc> | beq v1,v0,3068 <func_801861FC+0xd8>
replace mine[17:18] target[17:18]
17 j 30a8 <func_801861FC+0x118> | j 30a4 <func_801861FC+0x114>
replace mine[22:24] target[22:26]
22 move a0,v0 | sll v1,v0,0x3
23 sll v0,a0,0x3 | lw a0,32(s0)
24 -- | subu v1,v1,v0
25 -- | sh v1,24(a0)
replace mine[25:29] target[27:28]
25 subu v0,v0,a0 | sll v0,v0,0x1
26 sh v0,24(v1) | --
27 lw v1,32(s0) | --
28 sll v0,a0,0x1 | --
replace mine[44:45] target[43:44]
44 j 305c <func_801861FC+0xcc> | j 3058 <func_801861FC+0xc8>
replace mine[53:54] target[52:53]
53 j 30a8 <func_801861FC+0x118> | j 30a4 <func_801861FC+0x114>
replace mine[68:69] target[67:68]
68 j 30b0 <func_801861FC+0x120> | j 30ac <func_801861FC+0x11c>
@@ -0,0 +1,2 @@
REMOVED pin $3 line 4825
NEEDED pin $2 line 4826
@@ -0,0 +1,2 @@
src/ov_SC03_091/ov_SC03_091_jr_8018326C.c
func_801861FC
@@ -0,0 +1,182 @@
void func_80181864(s32 arg0) {
extern void func_8012C218(void *a0);
extern s32 func_8012CC64(s32 a0, void *a1);
extern s32 func_80133784(s32 a0, void *a1, s32 a2);
extern void func_8012E688(s32 arg0, s32 arg1, s32 arg2);
extern void func_8012B23C(s32 a0);
extern void func_8012B1B4(s32 a0, s32 a1);
extern s32 rand(void);
extern s32 D_8019F2A8;
extern s32 D_8019F28C;
s32 e;
s32 n;
s32 dir;
e = arg0;
if (--*(s16 *)(e + 0xFC) == 0) {
n = 0;
do {
arg0 = *(s32 *)(arg0 + 0x6C);
n++;
} while (arg0 != 0);
if (n < 7) {
if (e != 0) {
arg0 = e;
for (;;) {
s32 next = *(s32 *)(arg0 + 0x6C);
func_8012C218((void *)arg0);
arg0 = next;
if (arg0 == 0) {
return;
}
}
}
return;
}
}
{
s32 f;
*(s16 *)(*(s32 *)(e + 0x20) + 0x14) += 0x40;
*(s16 *)(*(s32 *)(e + 0x20) + 0x14) &= 0xFFF;
f = func_8012CC64(e, &D_8019F2A8);
if (f & 0x1000) {
*(s16 *)(e + 0x2) = 0x12;
return;
}
n = 0;
if (f & 0xC000) {
s16 p1[3];
s16 p2[3];
{
s16 *q = p2;
s32 x;
s32 y;
s32 z;
*(s16 *)(e + 0x16) = -(rand() & 3) - 8;
x = *(u16 *)(e + 6);
p1[0] = x - 0x20;
y = *(u16 *)(e + 0xA) + 0x10;
p1[1] = y;
z = *(u16 *)(e + 0xE) + 0x20;
p1[2] = z;
q[0] = x + 0x20;
q[1] = y;
q[2] = z;
if (func_80133784(1, p1, (s32)q) != 0) {
n = 1;
*(s16 *)(e + 0x12) = -(rand() & 3) - 4;
} else {
q[0] = p1[0] + 0x40;
q[1] = p1[1];
q[2] = p1[2];
if (func_80133784(1, q, (s32)p1) != 0) {
n = 2;
*(s16 *)(e + 0x12) = (rand() & 3) + 4;
}
}
}
{
s16 *q = p2;
s32 x;
s32 y;
s32 z;
x = *(u16 *)(e + 6);
p1[0] = x;
y = *(u16 *)(e + 0xA) + 0x10;
p1[1] = y;
z = *(u16 *)(e + 0xE);
p1[2] = z;
q[0] = x;
q[1] = y;
q[2] = z + 0x40;
if (func_80133784(1, p1, (s32)q) != 0) {
n += 4;
*(s16 *)(e + 0x1A) = -(rand() & 3) - 4;
} else {
q[0] = p1[0];
q[1] = p1[1];
q[2] = p1[2] + 0x40;
if (func_80133784(1, q, (s32)p1) != 0) {
n += 8;
*(s16 *)(e + 0x1A) = (rand() & 3) + 4;
}
}
}
switch (n - 1) {
case 0:
dir = 0x800;
break;
case 1:
dir = 0;
break;
case 3:
dir = 0x400;
break;
case 4:
dir = 0x600;
break;
case 5:
dir = 0x200;
break;
case 7:
dir = 0xC00;
break;
case 8:
dir = 0xA00;
break;
case 9:
dir = 0xE00;
break;
}
*(s16 *)(*(s32 *)(e + 0x20) + 0x12) = dir;
} else if (f & 0x2000) {
func_8012E688(e, 0x833, 0);
if ((rand() & 0xF) == 0) {
s32 t1;
s32 t2;
s32 t3;
s32 p;
*(s16 *)(*(s32 *)(e + 0x20) + 0x14) = 0;
t1 = *(u16 *)(e + 6);
t2 = *(u16 *)(e + 0xA);
t3 = *(u16 *)(e + 0xE);
*(s16 *)(e + 0x2) = 1;
*(s16 *)(e + 0x34) = 1;
*(s16 *)(e + 0x70) = 0;
*(s16 *)(e + 0x88) = t1;
*(s16 *)(e + 0x8A) = t2;
*(s16 *)(e + 0x8C) = t3;
func_8012B23C(e);
func_8012B1B4(e, (s32)&D_8019F28C);
p = *(s32 *)(e + 0x6C);
if (p != 0) {
do {
*(s16 *)(p + 0x2) = 2;
*(s16 *)(p + 0x70) -= 0x10;
*(s16 *)(*(s32 *)(p + 0x20) + 0x14) = 0;
p = *(s32 *)(p + 0x6C);
} while (p != 0);
}
*(s16 *)(e + 0xFC) = 0;
} else {
*(s16 *)(e + 0x16) = -(rand() & 3) - 8;
}
}
}
if (*(s16 *)(e + 0xA) >= 0x65) {
func_8012C218((void *)e);
}
}
@@ -0,0 +1,182 @@
void func_80181864(s32 arg0) {
extern void func_8012C218(void *a0);
extern s32 func_8012CC64(s32 a0, void *a1);
extern s32 func_80133784(s32 a0, void *a1, s32 a2);
extern void func_8012E688(s32 arg0, s32 arg1, s32 arg2);
extern void func_8012B23C(s32 a0);
extern void func_8012B1B4(s32 a0, s32 a1);
extern s32 rand(void);
extern s32 D_8019F2A8;
extern s32 D_8019F28C;
s32 e;
s32 n;
s32 dir;
e = arg0;
if (--*(s16 *)(e + 0xFC) == 0) {
n = 0;
do {
arg0 = *(s32 *)(arg0 + 0x6C);
n++;
} while (arg0 != 0);
if (n < 7) {
if (e != 0) {
arg0 = e;
for (;;) {
e = *(s32 *)(arg0 + 0x6C);
func_8012C218((void *)arg0);
arg0 = e;
if (arg0 == 0) {
return;
}
}
}
return;
}
}
{
s32 f;
*(s16 *)(*(s32 *)(e + 0x20) + 0x14) += 0x40;
*(s16 *)(*(s32 *)(e + 0x20) + 0x14) &= 0xFFF;
f = func_8012CC64(e, &D_8019F2A8);
if (f & 0x1000) {
*(s16 *)(e + 0x2) = 0x12;
return;
}
n = 0;
if (f & 0xC000) {
s16 p1[3];
s16 p2[3];
{
s16 *q = p2;
s32 x;
s32 y;
s32 z;
*(s16 *)(e + 0x16) = -(rand() & 3) - 8;
x = *(u16 *)(e + 6);
p1[0] = x - 0x20;
y = *(u16 *)(e + 0xA) + 0x10;
p1[1] = y;
z = *(u16 *)(e + 0xE) + 0x20;
p1[2] = z;
q[0] = x + 0x20;
q[1] = y;
q[2] = z;
if (func_80133784(1, p1, (s32)q) != 0) {
n = 1;
*(s16 *)(e + 0x12) = -(rand() & 3) - 4;
} else {
q[0] = p1[0] + 0x40;
q[1] = p1[1];
q[2] = p1[2];
if (func_80133784(1, q, (s32)p1) != 0) {
n = 2;
*(s16 *)(e + 0x12) = (rand() & 3) + 4;
}
}
}
{
s16 *q = p2;
s32 x;
s32 y;
s32 z;
x = *(u16 *)(e + 6);
p1[0] = x;
y = *(u16 *)(e + 0xA) + 0x10;
p1[1] = y;
z = *(u16 *)(e + 0xE);
p1[2] = z;
q[0] = x;
q[1] = y;
q[2] = z + 0x40;
if (func_80133784(1, p1, (s32)q) != 0) {
n += 4;
*(s16 *)(e + 0x1A) = -(rand() & 3) - 4;
} else {
q[0] = p1[0];
q[1] = p1[1];
q[2] = p1[2] + 0x40;
if (func_80133784(1, q, (s32)p1) != 0) {
n += 8;
*(s16 *)(e + 0x1A) = (rand() & 3) + 4;
}
}
}
switch (n - 1) {
case 0:
dir = 0x800;
break;
case 1:
dir = 0;
break;
case 3:
dir = 0x400;
break;
case 4:
dir = 0x600;
break;
case 5:
dir = 0x200;
break;
case 7:
dir = 0xC00;
break;
case 8:
dir = 0xA00;
break;
case 9:
dir = 0xE00;
break;
}
*(s16 *)(*(s32 *)(e + 0x20) + 0x12) = dir;
} else if (f & 0x2000) {
func_8012E688(e, 0x833, 0);
if ((rand() & 0xF) == 0) {
s32 t1;
s32 t2;
s32 t3;
s32 p;
*(s16 *)(*(s32 *)(e + 0x20) + 0x14) = 0;
t1 = *(u16 *)(e + 6);
t2 = *(u16 *)(e + 0xA);
t3 = *(u16 *)(e + 0xE);
*(s16 *)(e + 0x2) = 1;
*(s16 *)(e + 0x34) = 1;
*(s16 *)(e + 0x70) = 0;
*(s16 *)(e + 0x88) = t1;
*(s16 *)(e + 0x8A) = t2;
*(s16 *)(e + 0x8C) = t3;
func_8012B23C(e);
func_8012B1B4(e, (s32)&D_8019F28C);
p = *(s32 *)(e + 0x6C);
if (p != 0) {
do {
*(s16 *)(p + 0x2) = 2;
*(s16 *)(p + 0x70) -= 0x10;
*(s16 *)(*(s32 *)(p + 0x20) + 0x14) = 0;
p = *(s32 *)(p + 0x6C);
} while (p != 0);
}
*(s16 *)(e + 0xFC) = 0;
} else {
*(s16 *)(e + 0x16) = -(rand() & 3) - 8;
}
}
}
if (*(s16 *)(e + 0xA) >= 0x65) {
func_8012C218((void *)e);
}
}
@@ -0,0 +1,185 @@
void func_80181864(s32 arg0) {
extern void func_8012C218(void *a0);
extern s32 func_8012CC64(s32 a0, void *a1);
extern s32 func_80133784(s32 a0, void *a1, s32 a2);
extern void func_8012E688(s32 arg0, s32 arg1, s32 arg2);
extern void func_8012B23C(s32 a0);
extern void func_8012B1B4(s32 a0, s32 a1);
extern s32 rand(void);
extern s32 D_8019F2A8;
extern s32 D_8019F28C;
s32 e;
s32 n;
s32 dir;
e = arg0;
if (--*(s16 *)(e + 0xFC) == 0) {
n = 0;
do {
arg0 = *(s32 *)(arg0 + 0x6C);
n++;
} while (arg0 != 0);
if (n < 7) {
if (e != 0) {
arg0 = e;
for (;;) {
e = *(s32 *)(arg0 + 0x6C);
func_8012C218((void *)arg0);
arg0 = e;
__asm__ __volatile__("" : "=r"(arg0) : "0"(arg0)); // !FAKE: launder — NEEDED DIFFERS (P36 rung B tus9)
if (arg0 == 0) {
return;
}
}
}
return;
}
}
{
s32 f;
*(s16 *)(*(s32 *)(e + 0x20) + 0x14) += 0x40;
*(s16 *)(*(s32 *)(e + 0x20) + 0x14) &= 0xFFF;
f = func_8012CC64(e, &D_8019F2A8);
if (f & 0x1000) {
*(s16 *)(e + 0x2) = 0x12;
return;
}
n = 0;
if (f & 0xC000) {
s16 p1[3];
s16 p2[3];
{
s16 *q = p2;
s32 x;
s32 y;
s32 z;
*(s16 *)(e + 0x16) = -(rand() & 3) - 8;
x = *(u16 *)(e + 6);
p1[0] = x - 0x20;
y = *(u16 *)(e + 0xA) + 0x10;
p1[1] = y;
z = *(u16 *)(e + 0xE) + 0x20;
p1[2] = z;
q[0] = x + 0x20;
q[1] = y;
q[2] = z;
if (func_80133784(1, p1, (s32)q) != 0) {
n = 1;
*(s16 *)(e + 0x12) = -(rand() & 3) - 4;
} else {
q[0] = p1[0] + 0x40;
q[1] = p1[1];
q[2] = p1[2];
if (func_80133784(1, q, (s32)p1) != 0) {
n = 2;
*(s16 *)(e + 0x12) = (rand() & 3) + 4;
__asm__ __volatile__(""); /* cookbook 5a cross-jump barrier vs the n==1 arm */ // !FAKE: barrier — NEEDED DIFFERS (P36 rung B tus9)
}
}
}
{
s16 *q = p2;
s32 x;
s32 y;
s32 z;
x = *(u16 *)(e + 6);
p1[0] = x;
y = *(u16 *)(e + 0xA) + 0x10;
p1[1] = y;
z = *(u16 *)(e + 0xE);
p1[2] = z;
q[0] = x;
q[1] = y;
q[2] = z + 0x40;
if (func_80133784(1, p1, (s32)q) != 0) {
n += 4;
*(s16 *)(e + 0x1A) = -(rand() & 3) - 4;
} else {
q[0] = p1[0];
q[1] = p1[1];
q[2] = p1[2] + 0x40;
if (func_80133784(1, q, (s32)p1) != 0) {
n += 8;
*(s16 *)(e + 0x1A) = (rand() & 3) + 4;
__asm__ __volatile__(""); /* cookbook 5a cross-jump barrier vs the n+=4 arm */ // !FAKE: barrier — NEEDED DIFFERS (P36 rung B tus9)
}
}
}
switch (n - 1) {
case 0:
dir = 0x800;
break;
case 1:
dir = 0;
break;
case 3:
dir = 0x400;
break;
case 4:
dir = 0x600;
break;
case 5:
dir = 0x200;
break;
case 7:
dir = 0xC00;
break;
case 8:
dir = 0xA00;
break;
case 9:
dir = 0xE00;
break;
}
*(s16 *)(*(s32 *)(e + 0x20) + 0x12) = dir;
} else if (f & 0x2000) {
func_8012E688(e, 0x833, 0);
if ((rand() & 0xF) == 0) {
s32 t1;
s32 t2;
s32 t3;
s32 p;
*(s16 *)(*(s32 *)(e + 0x20) + 0x14) = 0;
t1 = *(u16 *)(e + 6);
t2 = *(u16 *)(e + 0xA);
t3 = *(u16 *)(e + 0xE);
*(s16 *)(e + 0x2) = 1;
*(s16 *)(e + 0x34) = 1;
*(s16 *)(e + 0x70) = 0;
*(s16 *)(e + 0x88) = t1;
*(s16 *)(e + 0x8A) = t2;
*(s16 *)(e + 0x8C) = t3;
func_8012B23C(e);
func_8012B1B4(e, (s32)&D_8019F28C);
p = *(s32 *)(e + 0x6C);
if (p != 0) {
do {
*(s16 *)(p + 0x2) = 2;
*(s16 *)(p + 0x70) -= 0x10;
*(s16 *)(*(s32 *)(p + 0x20) + 0x14) = 0;
p = *(s32 *)(p + 0x6C);
} while (p != 0);
}
*(s16 *)(e + 0xFC) = 0;
} else {
*(s16 *)(e + 0x16) = -(rand() & 3) - 8;
}
}
}
if (*(s16 *)(e + 0xA) >= 0x65) {
func_8012C218((void *)e);
}
}
@@ -0,0 +1,15 @@
g6: verdict NO-MATCH start 25 best 25 compiles 323 path
s7: verdict NO-MATCH start 25 best 21 compiles 558 path R12 width dir s32->u16 @5454 + R8 base tmp0 @5536 + R12 width tmp0 s32->s16 @5455
best-scoring single candidates of the last trace (move -> score [residual class]):
R12 width tmp0 s32->s16 @5455 -> 21 [COUNT] (from 25)
R12 width dir s32->u16 @5454 -> 25 [COUNT] (from 25)
R8 temp tmp0 @5536 -> 25 [COUNT] (from 25)
R7 block @5567 -> 25 [COUNT] (from 25)
R10 param-copy arg0 @5455 -> 25 [COUNT] (from 25)
R12 width dir s32->s16 @5454 -> 25 [COUNT] (from 25)
R8 base tmp0 @5536 -> 25 [COUNT] (from 25)
R7 do-while @5567 -> 25 [COUNT] (from 25)
R9 swap-stmts @5537 -> 25 [COUNT] (from 25)
R8 temp tmp0 @5505 -> 25 [COUNT] (from 25)
R7 block @5564 -> 25 [COUNT] (from 25)
R8 base tmp0 @5505 -> 25 [COUNT] (from 25)
@@ -0,0 +1,3 @@
--- every @class/@stuck/@crack note in this translation unit ---
// @class: schedule
// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
@@ -0,0 +1,669 @@
=== lever-free bodies in ov_SC03_113 sharing a callee or global with func_80181864 (48 found; top 6 by shared symbols) — read them for the SHAPE ===
--- func_801822BC (src/ov_SC03_113/ov_SC03_113_jr_8017C294.c:5884) shares 3: D_8019F28C D_8019F2A8 func_8012B1B4 ---
void func_801822BC(s32 a0)
{
extern void func_8012BE98(s32 a0, u16 *a1);
extern s32 func_8012B744(void *a0, void *a1);
extern s32 func_8012B608(s32 a0, s32 a1, s32 a2);
extern void func_8012B1B4(s32 a0, s32 a1);
extern s32 func_8012BD3C(s32 a0, s32 a1, s32 a2);
extern void func_8012CC40(s32 arg0, s32 arg1);
extern s32 func_8012C0EC(s32 a0);
extern u8 D_8019F28C[];
extern s32 D_8019F2A8;
s32 anim = a0 + 0x88;
if (((s32 (*)(s32, u16 *))func_8012BE98)(a0, (u16 *)anim) >= 0x4000) {
s32 d = func_8012B608(*(s16 *)(*(s32 *)(a0 + 0x20) + 0x12),
func_8012B744((void *)(a0 + 4), (void *)anim), 0x10);
*(u16 *)(*(s32 *)(a0 + 0x20) + 0x12) =
*(u16 *)(*(s32 *)(a0 + 0x20) + 0x12) + d;
*(u16 *)(*(s32 *)(a0 + 0x20) + 0x12) =
*(u16 *)(*(s32 *)(a0 + 0x20) + 0x12) & 0xFFF;
func_8012B1B4(a0, (s32)D_8019F28C);
} else {
if (func_8012BD3C(a0, 0x200, 0x40000) == 1) {
*(s16 *)(a0 + 0x2) = 3;
}
}
if ((((s32 (*)(s32, s32))func_8012CC40)(a0, (s32)&D_8019F2A8) & 0x1000) != 0) {
*(s16 *)(a0 + 0x2) = 0x12;
} else {
func_8012C0EC(a0);
}
}
--- func_80181730 (src/ov_SC03_113/ov_SC03_113_jr_8017C294.c:5377) shares 3: D_8019F28C D_8019F2A8 func_8012B1B4 ---
void func_80181730(s32 a0)
{
extern u8 D_8019F28C[];
extern s32 D_8019F2A8;
s16 pos1[4];
s16 pos2[4];
s32 s1;
*(u16 *)(*(s32 *)(a0 + 0x20) + 0x12) += func_8012B8E4(a0, 0x10);
*(u16 *)(*(s32 *)(a0 + 0x20) + 0x12) &= 0xFFF;
func_8012B1B4(a0, (s32)D_8019F28C);
{
s16 *p1 = pos1;
s16 *p2 = pos2;
s32 x, y, z;
x = *(u16 *)(a0 + 0x6);
p2[0] = x;
p1[0] = x;
y = *(u16 *)(a0 + 0xA);
p2[1] = y;
p1[1] = y;
z = *(u16 *)(a0 + 0xE);
p2[1] = y + 0x40;
p2[2] = z;
p1[2] = z;
s1 = func_8012CEB0((s32)p1, (s32)p2, 1);
}
if (s1 & 0x6000) {
if (!(s1 & 0x1000)) {
s1 = func_8012BCCC(a0);
if (s1 < 0x4001) {
if (func_8012BDBC(a0, 0x200) == 1) {
*(s16 *)(a0 + 0x2) = 4;
*(s16 *)(a0 + 0xFC) = 0;
*(s16 *)(a0 + 0x100) = *(u16 *)(a0 + 0xA);
}
}
}
}
if (s1 > 0x40000) {
*(s16 *)(a0 + 0x2) = 1;
}
if ((((s32 (*)(s32, s32))func_8012CC40)(a0, (s32)&D_8019F2A8) & 0x1000) != 0) {
*(s16 *)(a0 + 0x2) = 0x12;
}
}
--- func_80182130 (src/ov_SC03_113/ov_SC03_113_jr_8017C294.c:5809) shares 3: D_8019F28C func_8012B1B4 func_8012B23C ---
void func_80182130(s32 a0)
{
extern u8 D_8019F28C[];
u16 out[4];
u16 pos[4];
u16 t0, t1, t2;
*(u16 *)(a0 + 0x5C) = 0xA810;
*(u16 *)(a0 + 0x2) = *(u16 *)(a0 + 0x34);
t0 = *(u16 *)(a0 + 0x6);
pos[0] = t0;
out[0] = t0;
t1 = *(u16 *)(a0 + 0xA);
pos[1] = t1;
out[1] = t1 - 0x18;
t2 = *(u16 *)(a0 + 0xE);
pos[2] = t2;
out[2] = t2;
func_8012CEB0((s32)out, (s32)pos, 1);
*(u16 *)(a0 + 0xA) = pos[1] - 0x10;
if (*(s16 *)(a0 + 0x70) == 0xF) {
s32 c;
c = *(s32 *)(a0 + 0x20);
*(u16 *)(c + 0x14) = 0;
*(u16 *)(a0 + 0x2) = 1;
*(u16 *)(a0 + 0x34) = 1;
*(u16 *)(a0 + 0x70) = 0;
*(u16 *)(a0 + 0x88) = *(u16 *)(a0 + 0x6);
*(u16 *)(a0 + 0x8A) = *(u16 *)(a0 + 0xA);
*(u16 *)(a0 + 0x8C) = *(u16 *)(a0 + 0xE);
func_8012B23C(a0);
func_8012B1B4(a0, (s32)D_8019F28C);
{
s32 n = *(s32 *)(a0 + 0x6C);
while (n != 0) {
*(u16 *)(n + 0x2) = 2;
*(u16 *)(n + 0x70) = *(u16 *)(n + 0x70) - 0x10;
*(u16 *)(*(s32 *)(n + 0x20) + 0x14) = 0;
n = *(s32 *)(n + 0x6C);
}
}
*(u16 *)(a0 + 0xFC) = 0;
} else {
func_8012B23C(a0);
func_8012B1B4(a0, (s32)D_8019F28C);
}
}
--- func_8018097C (src/ov_SC03_113/ov_SC03_113_jr_8017C294.c:4918) shares 3: D_8019F28C func_8012B1B4 func_8012B23C ---
void func_8018097C(void *a0v)
{
extern u8 D_8019F1EC[];
extern u8 D_801A061C[];
extern u8 D_8019F2C0[];
extern u8 D_8019F28C[];
extern u8 D_801A5A00[];
extern u8 D_8019F220[];
extern u8 D_8019F22C[];
extern u8 D_8019F234[];
extern u8 D_8019F244[];
extern u16 D_8019F248;
extern u8 D_8019F24C[];
extern u8 D_8019F258[];
extern u8 D_8019F260[];
extern u8 D_8019F284[];
extern u16 D_8019F288;
extern u8 D_8019F270[];
extern u8 D_8019F27C[];
extern u8 D_801A5A41;
extern u8 D_801A5A42;
extern u8 D_801A5A44;
s32 e;
s32 r;
s32 o;
s32 cc;
s32 sv;
u8 *p;
u8 *q;
e = (s32)a0v;
switch (*(s16 *)(e + 0x70)) {
case 0:
if (((s32 (*)(s32, s32))func_8012C354)(e, (s32)D_8019F1EC) == 0) {
return;
}
*(u8 *)(e + 0xC0) = 1;
*(s32 *)(e + 0xB4) = -1;
*(s32 *)(e + 0xBC) = (s32)D_8019F2C0;
((void (*)(s32, void *))func_8012A828)(e, D_801A061C);
*(s16 *)(e + 0x2) = 1;
*(s16 *)(e + 0x34) = 1;
func_8012B23C(e);
func_8012B1B4(e, (s32)D_8019F28C);
*(s32 *)(e + 0xCC) = (s32)(D_801A5A00 + *(s16 *)(e + 0xFC) * 8);
o = func_8012C658(0x1EA, 1, e);
if (o != 0) {
*(u16 *)(o + 0xFE) = *(u16 *)(e + 0x36);
}
return;
case 1:
r = func_8012C1B8();
*(s32 *)(e + 0x20) = r;
if (r == 0) {
func_8012CAE4((void *)e);
return;
}
func_8001CA1C(r, (s32)D_8019F220);
((void (*)(s32, void *))func_8012A828)(e, D_8019F22C);
*(s16 *)(e + 0x2) = 2;
*(s16 *)(e + 0x5C) = 0x810;
*(s32 *)(e + 0x58) = (s32)D_8019F234 | 0x40000000 | 0x20000000;
*(s32 *)(e + 0xD0) = (s32)D_8019F244;
*(u16 *)(e + 0xE) = *(u16 *)(e + 0xE) + D_8019F248;
cc = *(s32 *)(*(s32 *)(e + 0x64) + 0xCC);
*(u16 *)(*(s32 *)(e + 0x20) + 0x2C) = *(u16 *)(*(s32 *)(e + 0x20) + 0x2C) | 0x80;
*(s32 *)(*(s32 *)(e + 0x20) + 0x80) = cc;
*(s32 *)(e + 0xCC) = cc;
o = func_8012C658(0x1EA, 2, e);
if (o != 0) {
*(u16 *)(o + 0xFE) = *(u16 *)(e + 0x36);
}
return;
case 2:
case 3:
case 4:
case 5:
case 6:
r = func_8012C1B8();
*(s32 *)(e + 0x20) = r;
if (r == 0) {
func_8012CAE4((void *)e);
return;
}
func_8001CA1C(r, (s32)D_8019F24C);
((void (*)(s32, void *))func_8012A828)(e, D_8019F258);
*(s16 *)(e + 0x2) = 0xF;
*(s16 *)(e + 0x5C) = 0x810;
*(s32 *)(e + 0x58) = (s32)D_8019F260 | 0x40000000 | 0x20000000;
*(s32 *)(e + 0xD0) = (s32)D_8019F284;
*(u16 *)(e + 0xE) = *(u16 *)(e + 0xE) + D_8019F288;
return;
case 7:
if (((s32 (*)(s32, s32))func_8012C354)(e, (s32)D_8019F1EC) == 0) {
return;
}
p = &D_801A5A41;
q = p - 1;
D_801A5A42 = 0xFF;
*q = 0xFF;
*p = 0;
D_801A5A42 = 0;
D_801A5A44 = 0;
func_800233CC(q, 0x20);
*(u8 *)(e + 0xC0) = 1;
*(s32 *)(e + 0xB4) = -1;
*(s32 *)(e + 0xBC) = (s32)D_8019F2C0;
((void (*)(s32, void *))func_8012A828)(e, D_801A061C);
*(s16 *)(e + 0x2) = 8;
*(s16 *)(e + 0x34) = 0xB;
func_8012B23C(e);
sv = *(s16 *)(e + 0xFC);
*(s16 *)(e + 0xFC) = 0;
*(s32 *)(e + 0xCC) = (s32)(D_801A5A00 + sv * 8);
o = func_8012C658(0x1EA, 8, e);
if (o != 0) {
*(u16 *)(o + 0xFE) = *(u16 *)(e + 0x36);
}
return;
case 8:
r = func_8012C1B8();
*(s32 *)(e + 0x20) = r;
if (r == 0) {
func_8012CAE4((void *)e);
return;
}
func_8001CA1C(r, (s32)D_8019F220);
((void (*)(s32, void *))func_8012A828)(e, D_8019F22C);
*(s16 *)(e + 0x2) = 2;
*(s16 *)(e + 0x5C) = 0x810;
*(s32 *)(e + 0x58) = (s32)D_8019F234 | 0x40000000 | 0x20000000;
*(s32 *)(e + 0xD0) = (s32)D_8019F244;
*(u16 *)(e + 0xE) = *(u16 *)(e + 0xE) + D_8019F248;
cc = *(s32 *)(*(s32 *)(e + 0x64) + 0xCC);
*(u16 *)(*(s32 *)(e + 0x20) + 0x2C) = *(u16 *)(*(s32 *)(e + 0x20) + 0x2C) | 0x80;
*(s32 *)(*(s32 *)(e + 0x20) + 0x80) = cc;
*(s32 *)(e + 0xCC) = cc;
o = func_8012C658(0x1EA, 9, e);
if (o != 0) {
*(u16 *)(o + 0xFE) = *(u16 *)(e + 0x36);
}
*(u16 *)(e + 0x106) = (rand() & 0x1F) + 0x20;
*(u16 *)(e + 0x100) = (rand() & 0x1F) + 0x20;
*(u16 *)(e + 0x102) = rand() & 0xFFF;
*(u16 *)(e + 0x104) = rand() & 0xFFF;
return;
case 9:
case 10:
case 11:
case 12:
case 13:
r = func_8012C1B8();
*(s32 *)(e + 0x20) = r;
if (r == 0) {
func_8012CAE4((void *)e);
return;
}
func_8001CA1C(r, (s32)D_8019F24C);
((void (*)(s32, void *))func_8012A828)(e, D_8019F258);
*(s16 *)(e + 0x2) = 0xF;
*(s16 *)(e + 0x5C) = 0x810;
*(s32 *)(e + 0x58) = (s32)D_8019F260 | 0x40000000 | 0x20000000;
*(s32 *)(e + 0xD0) = (s32)D_8019F284;
*(u16 *)(e + 0xE) = *(u16 *)(e + 0xE) + D_8019F288;
*(u16 *)(e + 0x106) = (rand() & 0x1F) + 0x20;
*(u16 *)(e + 0x100) = (rand() & 0x1F) + 0x20;
*(u16 *)(e + 0x102) = rand() & 0xFFF;
*(u16 *)(e + 0x104) = rand() & 0xFFF;
return;
case 14:
r = func_8012C1B8();
*(s32 *)(e + 0x20) = r;
if (r == 0) {
func_8012CAE4((void *)e);
return;
}
func_8001CA1C(r, (s32)D_8019F270);
((void (*)(s32, void *))func_8012A828)(e, D_8019F27C);
*(s16 *)(e + 0x2) = 0xC;
*(u16 *)(*(s32 *)(e + 0x20) + 0x10) =
*(u16 *)(*(s32 *)(*(s32 *)(e + 0x64) + 0x20) + 0x10);
*(u16 *)(*(s32 *)(e + 0x20) + 0x12) =
*(u16 *)(*(s32 *)(*(s32 *)(e + 0x64) + 0x20) + 0x12);
*(s32 *)(e + 0x14) = func_8004787C(*(s16 *)(*(s32 *)(e + 0x20) + 0x10)) << 9;
{
s32 t1 = func_8004787C(*(s16 *)(*(s32 *)(e + 0x20) + 0x12));
*(s32 *)(e + 0x10) = -((t1 * func_80047948(*(s16 *)(*(s32 *)(e + 0x20) + 0x10))) >> 3);
}
{
s32 t2 = func_80047948(*(s16 *)(*(s32 *)(e + 0x20) + 0x12));
*(s32 *)(e + 0x18) = -((t2 * func_80047948(*(s16 *)(*(s32 *)(e + 0x20) + 0x10))) >> 3);
}
*(s32 *)(e + 0x10) = (*(s32 *)(e + 0x10) * 2) / 3;
*(s32 *)(e + 0x1C) = 0x12C;
*(s32 *)(e + 0x14) = (*(s32 *)(e + 0x14) * 2) / 3;
*(s32 *)(e + 0x18) = (*(s32 *)(e + 0x18) * 2) / 3;
return;
case 15:
if (((s32 (*)(s32, s32))func_8012C354)(e, (s32)D_8019F1EC) == 0) {
return;
}
*(u8 *)(e + 0xC0) = 1;
*(s32 *)(e + 0xB4) = -1;
*(s32 *)(e + 0xBC) = (s32)D_8019F2C0;
((void (*)(s32, void *))func_8012A828)(e, D_801A061C);
*(s16 *)(e + 0x2) = 0xD;
*(s16 *)(e + 0x34) = 0xD;
func_8012B23C(e);
*(s32 *)(e + 0xCC) = (s32)(D_801A5A00 + *(s16 *)(e + 0xFC) * 8);
o = func_8012C658(0x1EA, 0x11, e);
if (o != 0) {
*(u16 *)(o + 0xFE) = *(u16 *)(e + 0x36);
*(s32 *)(e + 0x6C) = o;
}
*(s16 *)(e + 0xFC) = 0xA;
return;
case 16:
case 24:
*(s16 *)(e + 0x2) = 0xE;
*(s32 *)(e + 0x1C) = 6;
return;
case 17:
r = func_8012C1B8();
*(s32 *)(e + 0x20) = r;
if (r == 0) {
func_8012CAE4((void *)e);
return;
}
func_8001CA1C(r, (s32)D_8019F220);
((void (*)(s32, void *))func_8012A828)(e, D_8019F22C);
*(s16 *)(e + 0x2) = 0x11;
*(s16 *)(e + 0x5C) = 0x810;
*(s32 *)(e + 0x58) = (s32)D_8019F234 | 0x40000000 | 0x20000000;
*(s32 *)(e + 0xD0) = (s32)D_8019F244;
*(u16 *)(e + 0xE) = *(u16 *)(e + 0xE) + D_8019F248;
cc = *(s32 *)(*(s32 *)(e + 0x64) + 0xCC);
*(u16 *)(*(s32 *)(e + 0x20) + 0x2C) = *(u16 *)(*(s32 *)(e + 0x20) + 0x2C) | 0x80;
*(s32 *)(*(s32 *)(e + 0x20) + 0x80) = cc;
*(s32 *)(e + 0xCC) = cc;
o = func_8012C658(0x1EA, 0x12, e);
if (o != 0) {
*(u16 *)(o + 0xFE) = *(u16 *)(e + 0x36);
*(s32 *)(e + 0x6C) = o;
}
*(u16 *)(e + 0x106) = (rand() & 0x1F) + 0x20;
*(u16 *)(e + 0x100) = (rand() & 0x1F) + 0x20;
*(u16 *)(e + 0x102) = rand() & 0xFFF;
*(u16 *)(e + 0x104) = rand() & 0xFFF;
return;
case 18:
case 19:
case 20:
case 21:
case 22:
r = func_8012C1B8();
*(s32 *)(e + 0x20) = r;
if (r == 0) {
func_8012CAE4((void *)e);
return;
}
func_8001CA1C(r, (s32)D_8019F24C);
((void (*)(s32, void *))func_8012A828)(e, D_8019F258);
*(s16 *)(e + 0x2) = 0x10;
*(s16 *)(e + 0x5C) = 0x810;
*(s32 *)(e + 0x58) = (s32)D_8019F260 | 0x40000000 | 0x20000000;
*(s32 *)(e + 0xD0) = (s32)D_8019F284;
*(u16 *)(e + 0xE) = *(u16 *)(e + 0xE) + D_8019F288;
*(u16 *)(e + 0x106) = (rand() & 0x1F) + 0x20;
*(u16 *)(e + 0x100) = (rand() & 0x1F) + 0x20;
*(u16 *)(e + 0x102) = rand() & 0xFFF;
*(u16 *)(e + 0x104) = rand() & 0xFFF;
return;
case 25:
*(s16 *)(e + 0x2) = 0x13;
return;
}
}
--- func_80131340 (src/ov_SC03_113/ov_SC03_113_jr_8012ACE0.c:1432) shares 2: func_8012B23C func_8012CC64 ---
void func_80131340(s32 a0)
{
/* 8-byte, align-2 vector: align < 4 is what makes the assignments unaligned
* (lwl/lwr + swl/swr) block moves. Block-scope so the body stays self-contained
* for the dedup_propagate lift (§28-#1) and cannot collide with the TU's `M8`. */
struct V8 {
u16 vx, vy, vz, pad;
};
extern struct V8 D_80183290;
/* BLOCK-scope, mirroring the already-matched func_801312D0's decl at TU L1619: the
* later DEFINE_func_80131AC8() (TU L1964, AFTER this slot) redeclares func_80131CF4
* with the stale 1-arg engine_core canonical. A file-scope `extern int
* func_80131CF4(int,int);` here is a HARD `conflicting types` against it (cc1 rc=33,
* measured); block-scope goes out of scope before that macro and compiles clean. */
extern int func_80131CF4(int, int);
struct V8 sp10;
struct V8 sp18;
struct V8 sp20;
struct V8 sp28;
s32 temp;
s32 var_a1;
if (*(s16 *)(a0 + 0xA) >= 0x10) {
func_801319E0(a0);
return;
}
temp = func_80131CF4(*(s32 *)(a0 + 0xBC), 0x2E);
if (temp != 0) {
sp10.vz = 0;
sp10.vx = 0;
sp10.vy = temp;
} else {
sp10 = D_80183290;
}
if (*(s32 *)(a0 + 0x10) != 0 || *(s32 *)(a0 + 0x18) != 0) {
var_a1 = func_80131CF4(*(s32 *)(a0 + 0xBC), 0x19);
if (var_a1 == 0) {
var_a1 = 0x50;
}
func_8012DBD0(a0, var_a1,
*(s16 *)(*(s32 *)(a0 + 0x20) + 0x12) + 0x800, 0x1D);
}
switch (*(u8 *)(a0 + 0xC2)) {
case 0:
case 1:
if (*(s32 *)(a0 + 0xC4) & 4) {
*(u16 *)(*(s32 *)(a0 + 0x20) + 0x10) -= 0x100;
}
*(s32 *)(a0 + 0x1C) += 1;
if (*(s32 *)(a0 + 0x1C) >= 0x3D) {
func_80131E00(a0, 0xD);
return;
}
if (*(u8 *)(a0 + 0xC2) == 0) {
*(u8 *)(a0 + 0xC2) = 1;
sp18.vx = *(u16 *)(a0 + 0x3A);
sp18.vy = *(u16 *)(a0 + 0x3E);
sp18.vz = *(u16 *)(a0 + 0x42);
sp20 = sp18;
sp20.vx += sp10.vx;
sp20.vy += sp10.vy;
sp20.vz += sp10.vz;
sp28 = sp20; /* load-bearing dead aggregate copy — gcc-2.7.2 has no aggregate DSE */
func_8012CEB0((s32)&sp18, (s32)&sp20, 1);
sp20.vx -= sp10.vx;
sp20.vy -= sp10.vy;
sp20.vz -= sp10.vz;
*(u16 *)(a0 + 0x3A) = sp20.vx;
*(u16 *)(a0 + 0x3E) = sp20.vy;
*(u16 *)(a0 + 0x42) = sp20.vz;
*(u16 *)(a0 + 0x6) = sp20.vx;
*(u16 *)(a0 + 0xA) = sp20.vy;
*(u16 *)(a0 + 0xE) = sp20.vz;
}
D_801A46C8 = ((s32 (*)(s32, s32))func_8012CC64)(a0, (s32)&sp10);
if (D_801A46C8 & 0x8000) {
*(s32 *)(a0 + 0x18) = 0;
*(s32 *)(a0 + 0x10) = 0;
}
if (D_801A46C8 & 0x4000) {
func_8012B23C(a0);
*(u8 *)(a0 + 0xC2) = 4;
} else if (D_801A46C8 & 0x2000) {
if (func_80131D68(a0, D_801A46C8) == 1) {
return;
}
*(u8 *)(a0 + 0xC2) = 2;
func_80143B6C(a0, 1);
*(s32 *)(a0 + 0x14) = 0xFFF30000;
*(s32 *)(a0 + 0x1C) = 0;
} else if (D_801A46C8 & 0x8000) {
*(u8 *)(a0 + 0xC2) = 2;
*(s32 *)(a0 + 0x1C) = 0;
*(s32 *)(a0 + 0x18) = 0;
*(s32 *)(a0 + 0x10) = 0;
}
break;
case 2:
if (*(s32 *)(a0 + 0xC4) & 4) {
*(u16 *)(*(s32 *)(a0 + 0x20) + 0x10) -= 0x100;
}
*(s32 *)(a0 + 0x1C) += 1;
if (*(s32 *)(a0 + 0x1C) >= 0x3D) {
func_80131E00(a0, 0xD);
return;
}
D_801A46CC = *(s32 *)(a0 + 0x14);
D_801A46C8 = ((s32 (*)(s32, s32))func_8012CC64)(a0, (s32)&sp10);
if (D_801A46C8 & 0x8000) {
*(s32 *)(a0 + 0x18) = 0;
*(s32 *)(a0 + 0x10) = 0;
}
if (D_801A46C8 & 0x4000) {
func_8012B23C(a0);
*(u8 *)(a0 + 0xC2) = 4;
} else if (D_801A46C8 & 0x2000) {
if (func_80131D68(a0, D_801A46C8) == 1) {
return;
}
func_80143B6C(a0, 1);
/* MUST precede the 0x1C/0xC2 stores — see the header note on the /3 block. */
*(s32 *)(a0 + 0x14) = (-D_801A46CC) / 3;
*(s32 *)(a0 + 0x1C) = 0;
*(u8 *)(a0 + 0xC2) = 3;
*(u16 *)(*(s32 *)(a0 + 0x20) + 0x10) = 0;
} else if (D_801A46C8 & 0x8000) {
*(u8 *)(a0 + 0xC2) = 3;
*(s32 *)(a0 + 0x1C) = 0;
*(u16 *)(*(s32 *)(a0 + 0x20) + 0x10) = 0;
*(s32 *)(a0 + 0x18) = 0;
*(s32 *)(a0 + 0x10) = 0;
}
break;
case 3:
*(s32 *)(a0 + 0x10) = *(s32 *)(a0 + 0x10) * 15 / 16;
*(s32 *)(a0 + 0x18) = *(s32 *)(a0 + 0x18) * 15 / 16;
if (*(u8 *)(a0 + 0xC3) & 1) {
D_801A46C8 = ((s32 (*)(s32))func_8012CBA4)(a0);
if (D_801A46C8 & 0x8000) {
*(s32 *)(a0 + 0x18) = 0;
*(s32 *)(a0 + 0x10) = 0;
}
if (func_80131D68(a0, D_801A46C8) == 1) {
return;
}
if (!(D_801A46C8 & 0x6000)) {
func_80131E00(a0, 0xD);
return;
}
} else {
D_801A46C8 = ((s32 (*)(s32))func_8012CBF4)(a0);
if (D_801A46C8 & 0x8000) {
*(s32 *)(a0 + 0x18) = 0;
*(s32 *)(a0 + 0x10) = 0;
}
if (D_801A46C8 & 0x4000) {
func_8012B23C(a0);
*(u8 *)(a0 + 0xC2) = 4;
break;
} else if (D_801A46C8 & 0x2000) {
if (func_80131D68(a0, D_801A46C8) == 1) {
return;
}
*(u8 *)(a0 + 0xC3) |= 1;
} else if (D_801A46C8 & 0x8000) {
*(s32 *)(a0 + 0x18) = 0;
*(s32 *)(a0 + 0x10) = 0;
}
}
if ((*(s32 *)(a0 + 0x1C) & 3) == 3) {
func_80143B6C(a0, 1);
}
*(s32 *)(a0 + 0x1C) += 1;
if (*(s32 *)(a0 + 0x1C) < 0x11) {
break;
}
if (!(D_801A46C8 & 0x6000)) {
func_80131E00(a0, 0xD);
return;
}
/* polarity MUST match case 4's — see the cross-jump note in the header. */
if (*(s16 *)(a0 + 0x76) <= 0) {
func_80131E00(a0, 6);
} else {
func_80131C78(a0);
}
break;
case 4:
D_801A46C8 = ((s32 (*)(s32))func_8012CBA4)(a0);
if (D_801A46C8 & 0x8000) {
*(s32 *)(a0 + 0x18) = 0;
*(s32 *)(a0 + 0x10) = 0;
}
if (D_801A46C8 & 0x2000) {
if (func_80131D68(a0, D_801A46C8) == 1) {
return;
}
if (*(s16 *)(a0 + 0x76) <= 0) {
func_80131E00(a0, 6);
} else {
func_80131C78(a0);
}
} else {
if ((*(s32 *)(a0 + 0x1C) & 3) == 3) {
func_80143B6C(a0, 1);
}
*(s32 *)(a0 + 0x1C) += 1;
if (*(s32 *)(a0 + 0x1C) >= 0x3D) {
func_80131E00(a0, 0xD);
return;
}
}
break;
}
func_80131CA8(a0, 0x2F);
}
--- func_80182288 (src/ov_SC03_113/ov_SC03_113_jr_8017C294.c:5874) shares 1: func_8012E688 ---
void func_80182288(void *arg0) {
func_8012E688((s32)arg0, 0x8C7, 0);
func_8002AC00(0x10);
}
@@ -0,0 +1,48 @@
src/ov_SC03_113/ov_SC03_113_jr_8017C294.c:func_80181864: score 25 (COUNT; mine 237 ins, target 240) — not yet
replace mine[12:13] target[12:13]
12 bnez v0,5648 <func_80181864+0x78> | bnez v0,564c <func_80181864+0x7c>
replace mine[19:20] target[19:20]
19 beqz v0,5648 <func_80181864+0x78> | beqz v0,564c <func_80181864+0x7c>
replace mine[21:22] target[21:22]
21 beqz s0,5964 <func_80181864+0x394> | beqz s0,5970 <func_80181864+0x3a0>
delete mine[26:27] target[26:26]
26 beqz s0,5964 <func_80181864+0x394> | --
insert mine[28:28] target[27:29]
28 -- | beqz a0,5970 <func_80181864+0x3a0>
29 -- | nop
replace mine[48:49] target[49:50]
48 j 5964 <func_80181864+0x394> | j 5970 <func_80181864+0x3a0>
replace mine[51:52] target[52:53]
51 beqz v0,587c <func_80181864+0x2ac> | beqz v0,5888 <func_80181864+0x2b8>
replace mine[77:78] target[78:79]
77 beqz v0,5724 <func_80181864+0x154> | beqz v0,572c <func_80181864+0x15c>
delete mine[83:84] target[84:84]
83 j 5764 <func_80181864+0x194> | --
insert mine[85:85] target[85:87]
85 -- | j 5770 <func_80181864+0x1a0>
86 -- | sh v0,18(s0)
replace mine[118:119] target[120:121]
118 beqz v0,57c8 <func_80181864+0x1f8> | beqz v0,57d4 <func_80181864+0x204>
delete mine[124:125] target[126:126]
124 j 5808 <func_80181864+0x238> | --
insert mine[126:126] target[127:129]
126 -- | j 5818 <func_80181864+0x248>
127 -- | sh v0,26(s0)
replace mine[153:154] target[156:157]
153 j 5870 <func_80181864+0x2a0> | j 587c <func_80181864+0x2ac>
replace mine[155:156] target[158:159]
155 j 5870 <func_80181864+0x2a0> | j 587c <func_80181864+0x2ac>
replace mine[157:158] target[160:161]
157 j 5870 <func_80181864+0x2a0> | j 587c <func_80181864+0x2ac>
replace mine[159:160] target[162:163]
159 j 5870 <func_80181864+0x2a0> | j 587c <func_80181864+0x2ac>
replace mine[161:162] target[164:165]
161 j 5870 <func_80181864+0x2a0> | j 587c <func_80181864+0x2ac>
replace mine[163:164] target[166:167]
163 j 5870 <func_80181864+0x2a0> | j 587c <func_80181864+0x2ac>
replace mine[165:166] target[168:169]
165 j 5870 <func_80181864+0x2a0> | j 587c <func_80181864+0x2ac>
replace mine[169:170] target[172:173]
169 j 5948 <func_80181864+0x378> | j 5954 <func_80181864+0x384>
replace mine[214:215] target[217:218]
214 j 5948 <func_80181864+0x378> | j 5954 <func_80181864+0x384>
@@ -0,0 +1,3 @@
NEEDED launder line 5741
NEEDED barrier line 5795
NEEDED barrier line 5825
@@ -0,0 +1,2 @@
src/ov_SC03_113/ov_SC03_113_jr_8017C294.c
func_80181864
@@ -1,5 +1,5 @@
=== lever-free bodies in ov_SC04_007 sharing a callee or global with func_80180324 (3 found; top 6 by shared symbols) — read them for the SHAPE ===
--- func_80137D08 (src/ov_SC04_007/ov_SC04_007_jr_80135D20.c:1453) shares 1: D_800A5E60 ---
=== lever-free bodies in ov_SC04_007 sharing a callee or global with func_80180324 (4 found; top 6 by shared symbols) — read them for the SHAPE ===
--- func_80137D08 (src/ov_SC04_007/ov_SC04_007_jr_80135D20.c:1448) shares 1: D_800A5E60 ---
int func_80137D08(int arg0, int arg1, short arg2)
{
unsigned char buf[3];
@@ -20,7 +20,7 @@ int func_80137D08(int arg0, int arg1, short arg2)
return D_800A5E60;
}
--- func_80183438 (src/ov_SC04_007/ov_SC04_007_jr_8017BEBC.c:7294) shares 1: D_800A5E60 ---
--- func_80183438 (src/ov_SC04_007/ov_SC04_007_jr_8017BEBC.c:7292) shares 1: D_800A5E60 ---
void func_80183438(void *a0)
{
@@ -76,7 +76,7 @@ void func_80183438(void *a0)
}
}
--- func_8013DD68 (src/ov_SC04_007/ov_SC04_007_jr_8013C98C.c:1683) shares 1: D_800A5E60 ---
--- func_8013DD68 (src/ov_SC04_007/ov_SC04_007_jr_8013C98C.c:1641) shares 1: D_800A5E60 ---
void func_8013DD68() {
extern void SetDrawEnv(void *p, void *env);
extern u16 D_800AF7B8;
@@ -145,3 +145,362 @@ void func_8013DD68() {
return;
}
--- func_8017BEBC (src/ov_SC04_007/ov_SC04_007_jr_8017BEBC.c:2690) shares 1: D_800A5E60 ---
void func_8017BEBC(s32 arg0)
{
typedef struct { u32 w0, w1, w2; } Prim;
extern s32 func_800491EC(void);
extern void func_800547D8(s32, MATRIX2 *);
extern void func_80052E38(MATRIX2 *);
extern u8 *D_800A5E60;
extern u8 D_800A6610[];
extern short D_800B9A02; /* TU-visible spelling (engine_core.h + ov_SC01_000.c col-0); unsigned access forced at use — §8d sub-class (b) */
DVECTOR2 tmpxy[4];
SVECTOR2 box[8];
SVECTOR2 sxy[8];
MATRIX2 mtx;
struct { long otz, flag, opz, sz0, sz1, sz2, sz3; } g;
s32 lim;
s32 nparts;
s32 j;
u32 nprim;
u32 i;
Part *part;
Prim *prim;
u8 *pkt;
u32 ot;
u8 *vtx;
u8 *va, *vb, *vc, *vd;
u32 w, code;
u32 wx, wy, wz;
s32 xa32, xb32, t32;
s32 xmn1, xmx1, xmn2, xmx2;
s32 mnc, mxc;
s16 my, mny, mx, mn;
lim = func_800491EC() + *(s32 *)(arg0 + 0x64);
func_800547D8(arg0 + 0x10, &mtx);
func_80052E38(&mtx);
pkt = D_800A5E60;
part = *(Part **)(arg0 + 0xC);
nparts = *(s32 *)(*(s32 *)(arg0 + 8) + 8);
vtx = *(u8 **)(*(s32 *)(arg0 + 8) + 0x10);
ot = (u32)&D_800A6610[(*(u16 *)&D_800B9A02) << 14];
for (j = 0; j < nparts; j++, part++) {
wx = part->xx;
mn = wx;
mx = wx >> 16;
wy = part->yy;
mny = wy;
my = wy >> 16;
wz = part->zz;
box[0].vx = mn; box[0].vy = mny;
box[1].vx = mx; box[1].vy = mny;
box[2].vx = mn; box[2].vy = mny;
box[3].vx = mx; box[3].vy = mny;
box[4].vx = mn; box[4].vy = my;
box[5].vx = mx; box[5].vy = my;
box[6].vx = mn; box[6].vy = my;
box[7].vx = mx; box[7].vy = my;
wy = wz >> 16;
box[0].vz = wz;
box[1].vz = wz;
box[4].vz = wz;
box[5].vz = wz;
box[2].vz = wy;
box[3].vz = wy;
box[6].vz = wy;
box[7].vz = wy;
gte_ldv3c(&box[0]);
gte_rtpt();
gte_stsxy3(&sxy[0], &sxy[1], &sxy[2]);
gte_ldv0(&box[3]);
gte_rtps();
gte_stsxy(&sxy[3]);
gte_ldv3c(&box[4]);
gte_rtpt();
gte_stsxy3(&sxy[4], &sxy[5], &sxy[6]);
gte_ldv0(&box[7]);
gte_rtps();
gte_stsxy(&sxy[7]);
gte_stszotz(&g.otz);
if (lim >= g.otz) {
xa32 = sxy[0].vx;
xb32 = sxy[1].vx;
if (xb32 < xa32) { xmx1 = xa32; xmn1 = xb32; } else { xmn1 = xa32; xmx1 = xb32; }
t32 = sxy[2].vx;
if (xmx1 < t32) xmx1 = t32; else if (t32 < xmn1) xmn1 = t32;
t32 = sxy[3].vx;
if (xmx1 < t32) xmx1 = t32; else if (t32 < xmn1) xmn1 = t32;
xa32 = sxy[4].vx;
xb32 = sxy[5].vx;
if (xb32 < xa32) { xmx2 = xa32; xmn2 = xb32; } else { xmn2 = xa32; xmx2 = xb32; }
t32 = sxy[6].vx;
if (xmx2 < t32) xmx2 = t32; else if (t32 < xmn2) xmn2 = t32;
t32 = sxy[7].vx;
if (xmx2 < t32) xmx2 = t32; else if (t32 < xmn2) xmn2 = t32;
mnc = xmn1;
if (xmn2 < xmn1) mnc = xmn2;
mxc = xmx1;
if (mxc < xmx2) mxc = xmx2;
if ((s16)mxc >= -0xA0 && (s16)mnc < 0xA1) {
xa32 = sxy[0].vy;
xb32 = sxy[1].vy;
if (xb32 < xa32) { xmx1 = xa32; xmn1 = xb32; } else { xmn1 = xa32; xmx1 = xb32; }
t32 = sxy[2].vy;
if (xmx1 < t32) xmx1 = t32; else if (t32 < xmn1) xmn1 = t32;
t32 = sxy[3].vy;
if (xmx1 < t32) xmx1 = t32; else if (t32 < xmn1) xmn1 = t32;
xa32 = sxy[4].vy;
xb32 = sxy[5].vy;
if (xb32 < xa32) { xmx2 = xa32; xmn2 = xb32; } else { xmn2 = xa32; xmx2 = xb32; }
t32 = sxy[6].vy;
if (xmx2 < t32) xmx2 = t32; else if (t32 < xmn2) xmn2 = t32;
t32 = sxy[7].vy;
if (xmx2 < t32) xmx2 = t32; else if (t32 < xmn2) xmn2 = t32;
mnc = xmn1;
if (xmn2 < xmn1) mnc = xmn2;
mxc = xmx1;
if (mxc < xmx2) mxc = xmx2;
if ((s16)mxc >= -0x78 && (s16)mnc < 0x79) {
prim = (Prim *)part->prim;
nprim = part->nprim;
for (i = 0; i < nprim; i++, prim++) {
w = prim->w1;
va = vtx + (w & 0xFFFF);
vb = vtx + (w >> 16);
w = prim->w2;
vc = vtx + (w & 0xFFFF);
w = w >> 16;
gte_ldv3(va, vb, vc);
gte_rtpt();
gte_stflg(&g.flag);
if (!(g.flag & 0x7F85E000)) {
gte_nclip();
code = w & 7;
vd = vtx + (w & 0xFFF8);
gte_stopz(&g.opz);
if (g.opz > 0) {
switch (code) {
case 4:
case 5:
gte_stsxy3_f3(pkt);
gte_stsz3(&g.sz0, &g.sz1, &g.sz2);
if (((PolyF3 *)pkt)->x0 > ((PolyF3 *)pkt)->x1) {
mx = ((PolyF3 *)pkt)->x0;
mn = ((PolyF3 *)pkt)->x1;
} else {
mn = ((PolyF3 *)pkt)->x0;
mx = ((PolyF3 *)pkt)->x1;
}
if (((PolyF3 *)pkt)->x2 > mx) mx = ((PolyF3 *)pkt)->x2;
else if (((PolyF3 *)pkt)->x2 < mn) mn = ((PolyF3 *)pkt)->x2;
if (mx >= -0xA0 && mn < 0xA1) {
if (((PolyF3 *)pkt)->y0 > ((PolyF3 *)pkt)->y1) {
my = ((PolyF3 *)pkt)->y0;
mny = ((PolyF3 *)pkt)->y1;
} else {
mny = ((PolyF3 *)pkt)->y0;
my = ((PolyF3 *)pkt)->y1;
}
if (((PolyF3 *)pkt)->y2 > my) my = ((PolyF3 *)pkt)->y2;
else if (((PolyF3 *)pkt)->y2 < mny) mny = ((PolyF3 *)pkt)->y2;
if (my >= -0x78 && mny < 0x79) {
s32 za, zb;
u32 *otp;
if (g.sz0 > g.sz1) {
za = g.sz0;
if (za < g.sz2) za = g.sz2;
} else {
za = g.sz1;
if (za < g.sz2) za = g.sz2;
}
g.opz = za;
if (code != 4) g.opz = za + 0x200;
((PolyF3 *)pkt)->rgbc = prim->w0;
otp = (u32 *)(((g.opz >> 2) << 2) + ot);
*(u32 *)pkt = (*otp & 0xFFFFFF) | 0x4000000;
*otp = (*otp & 0xFF000000) | ((u32)pkt & 0xFFFFFF);
pkt += 0x14;
}
}
break;
case 6:
case 7:
gte_stsxy3_ft3(pkt);
gte_stsz3(&g.sz0, &g.sz1, &g.sz2);
if (((PolyFT3 *)pkt)->x0 > ((PolyFT3 *)pkt)->x1) {
mx = ((PolyFT3 *)pkt)->x0;
mn = ((PolyFT3 *)pkt)->x1;
} else {
mn = ((PolyFT3 *)pkt)->x0;
mx = ((PolyFT3 *)pkt)->x1;
}
if (((PolyFT3 *)pkt)->x2 > mx) mx = ((PolyFT3 *)pkt)->x2;
else if (((PolyFT3 *)pkt)->x2 < mn) mn = ((PolyFT3 *)pkt)->x2;
if (mx >= -0xA0 && mn < 0xA1) {
if (((PolyFT3 *)pkt)->y0 > ((PolyFT3 *)pkt)->y1) {
my = ((PolyFT3 *)pkt)->y0;
mny = ((PolyFT3 *)pkt)->y1;
} else {
mny = ((PolyFT3 *)pkt)->y0;
my = ((PolyFT3 *)pkt)->y1;
}
if (((PolyFT3 *)pkt)->y2 > my) my = ((PolyFT3 *)pkt)->y2;
else if (((PolyFT3 *)pkt)->y2 < mny) mny = ((PolyFT3 *)pkt)->y2;
if (my >= -0x78 && mny < 0x79) {
s32 za, zb;
u32 *otp;
u32 *tp;
if (g.sz0 > g.sz1) {
za = g.sz0;
if (za < g.sz2) za = g.sz2;
} else {
za = g.sz1;
if (za < g.sz2) za = g.sz2;
}
g.opz = za;
if (code == 7) g.opz = za + 0x200;
tp = (u32 *)prim->w0;
((PolyFT3 *)pkt)->rgbc = tp[0];
((PolyFT3 *)pkt)->uvc0 = tp[1];
((PolyFT3 *)pkt)->uvp1 = tp[2];
((PolyFT3 *)pkt)->uv2 = tp[3];
otp = (u32 *)(((g.opz >> 2) << 2) + ot);
*(u32 *)pkt = (*otp & 0xFFFFFF) | 0x7000000;
*otp = (*otp & 0xFF000000) | ((u32)pkt & 0xFFFFFF);
pkt += 0x20;
}
}
break;
case 0:
case 1:
gte_stsxy3_f3(pkt);
gte_ldv0(vd);
gte_rtps();
if (((PolyF4 *)pkt)->x0 > ((PolyF4 *)pkt)->x1) {
mx = ((PolyF4 *)pkt)->x0;
mn = ((PolyF4 *)pkt)->x1;
} else {
mn = ((PolyF4 *)pkt)->x0;
mx = ((PolyF4 *)pkt)->x1;
}
if (((PolyF4 *)pkt)->x2 > mx) mx = ((PolyF4 *)pkt)->x2;
else if (((PolyF4 *)pkt)->x2 < mn) mn = ((PolyF4 *)pkt)->x2;
if (((PolyF4 *)pkt)->y0 > ((PolyF4 *)pkt)->y1) {
my = ((PolyF4 *)pkt)->y0;
mny = ((PolyF4 *)pkt)->y1;
} else {
mny = ((PolyF4 *)pkt)->y0;
my = ((PolyF4 *)pkt)->y1;
}
if (((PolyF4 *)pkt)->y2 > my) my = ((PolyF4 *)pkt)->y2;
else if (((PolyF4 *)pkt)->y2 < mny) mny = ((PolyF4 *)pkt)->y2;
gte_stflg(&g.flag);
if (!(g.flag & 0x7F85E000)) {
gte_stsz4(&g.sz0, &g.sz1, &g.sz2, &g.sz3);
gte_stsxy((long *)&((PolyF4 *)pkt)->x3);
if (((PolyF4 *)pkt)->x3 < mn) mn = ((PolyF4 *)pkt)->x3;
else if (mx < ((PolyF4 *)pkt)->x3) mx = ((PolyF4 *)pkt)->x3;
if (mx >= -0xA0 && mn < 0xA1) {
if (((PolyF4 *)pkt)->y3 < mny) mny = ((PolyF4 *)pkt)->y3;
else if (my < ((PolyF4 *)pkt)->y3) my = ((PolyF4 *)pkt)->y3;
if (my >= -0x78 && mny < 0x79) {
s32 za, zb, zc;
u32 *otp;
zb = g.sz2;
if (zb < g.sz3) zb = g.sz3;
za = g.sz0;
if (za < g.sz1) za = g.sz1;
zc = za;
if (zc < zb) zc = zb;
g.opz = zc;
((PolyF4 *)pkt)->rgbc = prim->w0;
otp = (u32 *)(((zc >> 2) << 2) + ot);
*(u32 *)pkt = (*otp & 0xFFFFFF) | 0x5000000;
*otp = (*otp & 0xFF000000) | ((u32)pkt & 0xFFFFFF);
pkt += 0x18;
}
}
}
break;
case 2:
case 3:
gte_stsxy3c(&tmpxy[0]);
gte_ldv0(vd);
gte_rtps();
if (tmpxy[0].vx > tmpxy[1].vx) {
mx = tmpxy[0].vx;
mn = tmpxy[1].vx;
} else {
mn = tmpxy[0].vx;
mx = tmpxy[1].vx;
}
if (tmpxy[2].vx > mx) mx = tmpxy[2].vx;
else if (tmpxy[2].vx < mn) mn = tmpxy[2].vx;
if (tmpxy[0].vy > tmpxy[1].vy) {
my = tmpxy[0].vy;
mny = tmpxy[1].vy;
} else {
mny = tmpxy[0].vy;
my = tmpxy[1].vy;
}
if (tmpxy[2].vy > my) my = tmpxy[2].vy;
else if (tmpxy[2].vy < mny) mny = tmpxy[2].vy;
gte_stflg(&g.flag);
if (!(g.flag & 0x7F85E000)) {
gte_stsz4(&g.sz0, &g.sz1, &g.sz2, &g.sz3);
gte_stsxy((long *)&((PolyFT4 *)pkt)->x3);
if (((PolyFT4 *)pkt)->x3 < mn) mn = ((PolyFT4 *)pkt)->x3;
else if (mx < ((PolyFT4 *)pkt)->x3) mx = ((PolyFT4 *)pkt)->x3;
if (mx >= -0xA0 && mn < 0xA1) {
if (((PolyFT4 *)pkt)->y3 < mny) mny = ((PolyFT4 *)pkt)->y3;
else if (my < ((PolyFT4 *)pkt)->y3) my = ((PolyFT4 *)pkt)->y3;
if (my >= -0x78 && mny < 0x79) {
s32 za, zb;
u32 *otp;
u32 *tp;
u32 uvw;
zb = g.sz2;
if (zb < g.sz3) zb = g.sz3;
za = g.sz0;
if (za < g.sz1) za = g.sz1;
if (za < zb) za = zb;
g.opz = za;
if (code == 3) g.opz = za + 0x200;
*(u32 *)&((PolyFT4 *)pkt)->x0 = *(u32 *)&tmpxy[0];
*(u32 *)&((PolyFT4 *)pkt)->x1 = *(u32 *)&tmpxy[1];
*(u32 *)&((PolyFT4 *)pkt)->x2 = *(u32 *)&tmpxy[2];
tp = (u32 *)prim->w0;
((PolyFT4 *)pkt)->rgbc = tp[0];
((PolyFT4 *)pkt)->uvc0 = tp[1];
((PolyFT4 *)pkt)->uvp1 = tp[2];
uvw = tp[3];
((PolyFT4 *)pkt)->uv2 = uvw;
((PolyFT4 *)pkt)->uv3 = uvw >> 16;
otp = (u32 *)(((g.opz >> 2) << 2) + ot);
*(u32 *)pkt = (*otp & 0xFFFFFF) | 0x9000000;
*otp = (*otp & 0xFF000000) | ((u32)pkt & 0xFFFFFF);
pkt += 0x28;
}
}
}
break;
}
}
}
}
}
}
}
}
D_800A5E60 = pkt;
}
@@ -0,0 +1,153 @@
void func_8018179C(s32 a0)
{
s16 hi;
s16 pos;
s32 sp10[3];
u16 state;
hi = *(s16 *)(a0 + 0x8A);
pos = *(s16 *)(a0 + 0xA);
if (pos >= hi - 8) {
if (*(s32 *)(a0 + 0x48) >= 0) {
*(s32 *)(a0 + 0x48) = -0x8000;
*(s32 *)(a0 + 0x14) = *(s32 *)(a0 + 0x14) >> 1;
}
} else {
if (hi + 8 >= pos) {
if (*(s32 *)(a0 + 0x48) <= 0) {
*(s32 *)(a0 + 0x48) = 0x8000;
*(s32 *)(a0 + 0x14) = *(s32 *)(a0 + 0x14) >> 1;
}
}
}
if (*(s32 *)(a0 + 0xDC) < -0x40000) {
*(s32 *)(a0 + 0xDC) = -0x40000;
}
sp10[0] = 0;
sp10[1] = 0;
sp10[2] = *(s32 *)(a0 + 0xDC);
func_8012B1B4(a0, (s32)sp10);
func_8012CBCC(a0);
state = *(u16 *)(a0 + 0x34);
switch (state) {
case 0: {
s32 s0v;
s32 ret;
s32 p744;
s32 v1p;
s16 snd;
s32 b608;
s32 p20;
s0v = a0 + 0x88;
ret = ((s32 (*)(s32, u16 *))func_8012BE98)(a0, (u16 *)s0v);
if (ret <= 0x3FFFF) {
if (func_801810FC(a0, 0x51) == 0) {
goto set_state1;
}
}
p744 = func_8012B744((void *)(a0 + 4), (void *)s0v);
v1p = *(s32 *)(a0 + 0x20);
snd = *(s16 *)(v1p + 0x12);
b608 = func_8012B608(snd, p744, 8);
p20 = *(s32 *)(a0 + 0x20);
*(u16 *)(p20 + 0x12) = *(u16 *)(p20 + 0x12) + b608;
v1p = *(s32 *)(a0 + 0x20);
*(u16 *)(v1p + 0x12) = *(u16 *)(v1p + 0x12) & 0xFFF;
func_8012B1B4(a0, (s32)sp10);
break;
}
case 1: {
s32 ret;
*(s32 *)(a0 + 0xDC) = *(s32 *)(a0 + 0xDC) << 1;
ret = ((s32 (*)(s32, u16 *))func_8012BE98)(a0, (u16 *)(a0 + 0x88));
if (ret > 0x3FFFF) {
goto rand_tail;
}
if (func_801810FC(a0, 0x51) == 0) {
goto end_switch;
}
goto rand_tail;
}
case 2: {
s32 p744;
s32 v1p;
s16 snd;
s32 b608;
s32 p20;
p744 = func_8012B744((void *)(a0 + 4), (void *)(a0 + 0x88));
v1p = *(s32 *)(a0 + 0x20);
snd = *(s16 *)(v1p + 0x12);
b608 = func_8012B608(snd, p744, 0x10);
p20 = *(s32 *)(a0 + 0x20);
*(u16 *)(p20 + 0x12) = *(u16 *)(p20 + 0x12) + b608;
v1p = *(s32 *)(a0 + 0x20);
*(u16 *)(v1p + 0x12) = *(u16 *)(v1p + 0x12) & 0xFFF;
*(s32 *)(a0 + 0xDC) = *(s32 *)(a0 + 0xDC) >> 1;
func_801810FC(a0, 0x51);
if (*(s16 *)(a0 + 0x102) == 0) {
*(u16 *)(a0 + 0x34) = 3;
} else {
*(s16 *)(a0 + 0x102) = *(s16 *)(a0 + 0x102) - 1;
}
break;
}
case 3: {
s32 s2v;
s32 ret;
s32 p744;
s32 v1p;
s16 snd;
s32 b608;
s2v = a0 + 0x88;
ret = ((s32 (*)(s32, u16 *))func_8012BE98)(a0, (u16 *)s2v);
*(s32 *)(a0 + 0xDC) = *(s32 *)(a0 + 0xDC) << 1;
if (func_801810FC(a0, 0x51) != 0) {
goto rand_tail;
}
if (ret <= 0x40000) {
goto set_state1;
}
p744 = func_8012B744((void *)(a0 + 4), (void *)s2v);
v1p = *(s32 *)(a0 + 0x20);
snd = *(s16 *)(v1p + 0x12);
b608 = func_8012B608(snd, p744, 1);
if ((u32)(b608 + 0xFF) < 0x1FF) {
goto end_switch;
}
goto rand_tail;
}
}
goto end_switch;
rand_tail:
*(u16 *)(a0 + 0x34) = 2;
{
s32 r = rand();
*(s16 *)(a0 + 0x102) = (r & 7) + 8;
}
goto end_switch;
set_state1:
*(u16 *)(a0 + 0x34) = 1;
end_switch:
if (*(s16 *)(a0 + 0x100) != 0) {
*(s16 *)(a0 + 0x100) = *(s16 *)(a0 + 0x100) - 1;
} else {
s32 ret3;
ret3 = ((s32 (*)(s32))func_8012BE54)(a0);
if (ret3 <= 0x24000) {
*(s16 *)(a0 + 0x2) = 2;
*(s16 *)(a0 + 0x100) = 0x3C;
}
}
}
@@ -0,0 +1,153 @@
void func_8018179C(s32 a0)
{
s16 hi;
s16 pos;
s32 sp10[3];
u16 state;
hi = *(s16 *)(a0 + 0x8A);
pos = *(s16 *)(a0 + 0xA);
if (pos >= hi - 8) {
if (*(s32 *)(a0 + 0x48) >= 0) {
*(s32 *)(a0 + 0x48) = -0x8000;
*(s32 *)(a0 + 0x14) = *(s32 *)(a0 + 0x14) >> 1;
}
} else {
if (hi + 8 >= pos) {
if (*(s32 *)(a0 + 0x48) <= 0) {
*(s32 *)(a0 + 0x48) = 0x8000;
*(s32 *)(a0 + 0x14) = *(s32 *)(a0 + 0x14) >> 1;
}
}
}
if (*(s32 *)(a0 + 0xDC) < -0x40000) {
*(s32 *)(a0 + 0xDC) = -0x40000;
}
sp10[0] = 0;
sp10[1] = 0;
sp10[2] = *(s32 *)(a0 + 0xDC);
func_8012B1B4(a0, (s32)sp10);
func_8012CBCC(a0);
state = *(u16 *)(a0 + 0x34);
switch (state) {
case 0: {
s32 s0v;
s32 ret;
s32 p744;
s32 v1p;
s16 snd;
s32 b608;
s32 p20;
s0v = a0 + 0x88;
ret = ((s32 (*)(s32, u16 *))func_8012BE98)(a0, (u16 *)s0v);
if (ret <= 0x3FFFF) {
if (func_801810FC(a0, 0x51) == 0) {
goto set_state1;
}
}
p744 = func_8012B744((void *)(a0 + 4), (void *)s0v);
v1p = *(s32 *)(a0 + 0x20);
snd = *(s16 *)(v1p + 0x12);
b608 = func_8012B608(snd, p744, 8);
p20 = *(s32 *)(a0 + 0x20);
*(u16 *)(p20 + 0x12) = *(u16 *)(p20 + 0x12) + b608;
v1p = *(s32 *)(a0 + 0x20);
*(u16 *)(v1p + 0x12) = *(u16 *)(v1p + 0x12) & 0xFFF;
func_8012B1B4(a0, (s32)sp10);
break;
}
case 1: {
s32 ret;
*(s32 *)(a0 + 0xDC) = *(s32 *)(a0 + 0xDC) << 1;
ret = ((s32 (*)(s32, u16 *))func_8012BE98)(a0, (u16 *)(a0 + 0x88));
if (ret > 0x3FFFF) {
goto rand_tail;
}
if (func_801810FC(a0, 0x51) == 0) {
goto end_switch;
}
goto rand_tail;
}
case 2: {
s32 p744;
s32 v1p;
s16 snd;
s32 b608;
s32 p20;
p744 = func_8012B744((void *)(a0 + 4), (void *)(a0 + 0x88));
v1p = *(s32 *)(a0 + 0x20);
snd = *(s16 *)(v1p + 0x12);
b608 = func_8012B608(snd, p744, 0x10);
p20 = *(s32 *)(a0 + 0x20);
*(u16 *)(p20 + 0x12) = *(u16 *)(p20 + 0x12) + b608;
v1p = *(s32 *)(a0 + 0x20);
*(u16 *)(v1p + 0x12) = *(u16 *)(v1p + 0x12) & 0xFFF;
*(s32 *)(a0 + 0xDC) = *(s32 *)(a0 + 0xDC) >> 1;
func_801810FC(a0, 0x51);
if (*(s16 *)(a0 + 0x102) == 0) {
*(u16 *)(a0 + 0x34) = 3;
} else {
*(s16 *)(a0 + 0x102) = *(s16 *)(a0 + 0x102) - 1;
}
break;
}
case 3: {
s32 s2v;
s32 ret;
s32 p744;
s32 v1p;
s16 snd;
s32 b608;
s2v = a0 + 0x88;
ret = ((s32 (*)(s32, u16 *))func_8012BE98)(a0, (u16 *)s2v);
*(s32 *)(a0 + 0xDC) = *(s32 *)(a0 + 0xDC) << 1;
if (func_801810FC(a0, 0x51) != 0) {
goto rand_tail;
}
if (ret <= 0x40000) {
goto set_state1;
}
p744 = func_8012B744((void *)(a0 + 4), (void *)s2v);
v1p = *(s32 *)(a0 + 0x20);
snd = *(s16 *)(v1p + 0x12);
b608 = func_8012B608(snd, p744, 1);
if ((u32)(b608 + 0xFF) < 0x1FF) {
goto end_switch;
}
goto rand_tail;
}
}
goto end_switch;
rand_tail:
*(u16 *)(a0 + 0x34) = 2;
{
s32 r = rand();
*(s16 *)(a0 + 0x102) = (r & 7) + 8;
}
goto end_switch;
set_state1:
*(u16 *)(a0 + 0x34) = 1;
end_switch:
if (*(s16 *)(a0 + 0x100) != 0) {
*(s16 *)(a0 + 0x100) = *(s16 *)(a0 + 0x100) - 1;
} else {
s32 ret3;
ret3 = ((s32 (*)(s32))func_8012BE54)(a0);
if (ret3 <= 0x24000) {
*(s16 *)(a0 + 0x2) = 2;
*(s16 *)(a0 + 0x100) = 0x3C;
}
}
}
@@ -0,0 +1,153 @@
void func_8018179C(s32 a0)
{
s16 hi;
s16 pos;
s32 sp10[3];
u16 state;
hi = *(s16 *)(a0 + 0x8A);
pos = *(s16 *)(a0 + 0xA);
if (pos >= hi - 8) {
if (*(s32 *)(a0 + 0x48) >= 0) {
*(s32 *)(a0 + 0x48) = -0x8000;
*(s32 *)(a0 + 0x14) = *(s32 *)(a0 + 0x14) >> 1;
}
} else {
if (hi + 8 >= pos) {
if (*(s32 *)(a0 + 0x48) <= 0) {
*(s32 *)(a0 + 0x48) = 0x8000;
*(s32 *)(a0 + 0x14) = *(s32 *)(a0 + 0x14) >> 1;
}
}
}
if (*(s32 *)(a0 + 0xDC) < -0x40000) {
*(s32 *)(a0 + 0xDC) = -0x40000;
}
sp10[0] = 0;
sp10[1] = 0;
sp10[2] = *(s32 *)(a0 + 0xDC);
func_8012B1B4(a0, (s32)sp10);
func_8012CBCC(a0);
state = *(u16 *)(a0 + 0x34);
switch (state) {
case 0: {
register s32 s0v __asm__("$16"); // !FAKE: pin $16 — NEEDED DIFFERS (P36 rung B tus7)
s32 ret;
s32 p744;
s32 v1p;
s16 snd;
s32 b608;
register s32 p20 __asm__("$4"); // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus7)
s0v = a0 + 0x88;
ret = ((s32 (*)(s32, u16 *))func_8012BE98)(a0, (u16 *)s0v);
if (ret <= 0x3FFFF) {
if (func_801810FC(a0, 0x51) == 0) {
goto set_state1;
}
}
p744 = func_8012B744((void *)(a0 + 4), (void *)s0v);
v1p = *(s32 *)(a0 + 0x20);
snd = *(s16 *)(v1p + 0x12);
b608 = func_8012B608(snd, p744, 8);
p20 = *(s32 *)(a0 + 0x20);
*(u16 *)(p20 + 0x12) = *(u16 *)(p20 + 0x12) + b608;
v1p = *(s32 *)(a0 + 0x20);
*(u16 *)(v1p + 0x12) = *(u16 *)(v1p + 0x12) & 0xFFF;
func_8012B1B4(a0, (s32)sp10);
break;
}
case 1: {
s32 ret;
*(s32 *)(a0 + 0xDC) = *(s32 *)(a0 + 0xDC) << 1;
ret = ((s32 (*)(s32, u16 *))func_8012BE98)(a0, (u16 *)(a0 + 0x88));
if (ret > 0x3FFFF) {
goto rand_tail;
}
if (func_801810FC(a0, 0x51) == 0) {
goto end_switch;
}
goto rand_tail;
}
case 2: {
s32 p744;
s32 v1p;
s16 snd;
s32 b608;
s32 p20;
p744 = func_8012B744((void *)(a0 + 4), (void *)(a0 + 0x88));
v1p = *(s32 *)(a0 + 0x20);
snd = *(s16 *)(v1p + 0x12);
b608 = func_8012B608(snd, p744, 0x10);
p20 = *(s32 *)(a0 + 0x20);
*(u16 *)(p20 + 0x12) = *(u16 *)(p20 + 0x12) + b608;
v1p = *(s32 *)(a0 + 0x20);
*(u16 *)(v1p + 0x12) = *(u16 *)(v1p + 0x12) & 0xFFF;
*(s32 *)(a0 + 0xDC) = *(s32 *)(a0 + 0xDC) >> 1;
func_801810FC(a0, 0x51);
if (*(s16 *)(a0 + 0x102) == 0) {
*(u16 *)(a0 + 0x34) = 3;
} else {
*(s16 *)(a0 + 0x102) = *(s16 *)(a0 + 0x102) - 1;
}
break;
}
case 3: {
s32 s2v;
s32 ret;
s32 p744;
s32 v1p;
s16 snd;
s32 b608;
s2v = a0 + 0x88;
ret = ((s32 (*)(s32, u16 *))func_8012BE98)(a0, (u16 *)s2v);
*(s32 *)(a0 + 0xDC) = *(s32 *)(a0 + 0xDC) << 1;
if (func_801810FC(a0, 0x51) != 0) {
goto rand_tail;
}
if (ret <= 0x40000) {
goto set_state1;
}
p744 = func_8012B744((void *)(a0 + 4), (void *)s2v);
v1p = *(s32 *)(a0 + 0x20);
snd = *(s16 *)(v1p + 0x12);
b608 = func_8012B608(snd, p744, 1);
if ((u32)(b608 + 0xFF) < 0x1FF) {
goto end_switch;
}
goto rand_tail;
}
}
goto end_switch;
rand_tail:
*(u16 *)(a0 + 0x34) = 2;
{
s32 r = rand();
*(s16 *)(a0 + 0x102) = (r & 7) + 8;
}
goto end_switch;
set_state1:
*(u16 *)(a0 + 0x34) = 1;
end_switch:
if (*(s16 *)(a0 + 0x100) != 0) {
*(s16 *)(a0 + 0x100) = *(s16 *)(a0 + 0x100) - 1;
} else {
s32 ret3;
ret3 = ((s32 (*)(s32))func_8012BE54)(a0);
if (ret3 <= 0x24000) {
*(s16 *)(a0 + 0x2) = 2;
*(s16 *)(a0 + 0x100) = 0x3C;
}
}
}
@@ -0,0 +1,14 @@
g6b: verdict NO-MATCH start 63 best 63 compiles 305 path
best-scoring single candidates of the last trace (move -> score [residual class]):
R2 decl-order 1,0 -> 63 [MIXED] (from 63)
R5 swap + @6944 -> 63 [MIXED] (from 63)
R6 inline state @6921 -> 63 [MIXED] (from 63)
R7 block @6906 -> 63 [MIXED] (from 63)
R8 temp tmp0 @6906 -> 63 [MIXED] (from 63)
R9 swap-stmts @6899 -> 63 [MIXED] (from 63)
R10 param-copy a0 @6893 -> 63 [MIXED] (from 63)
R12 width state u16->s32 @6892 -> 63 [MIXED] (from 63)
R5 swap + @6975 -> 63 [MIXED] (from 63)
R6 inline r @7019 -> 63 [MIXED] (from 63)
R8 base tmp0 @6906 -> 63 [MIXED] (from 63)
R12 width state u16->s16 @6892 -> 63 [MIXED] (from 63)
@@ -0,0 +1,51 @@
--- every @class/@stuck/@crack note in this translation unit ---
// @class: plumbing
// @stuck: none — MATCH
// @class: regalloc-order — simplified sibling of matched func_8017B614.
// @stuck: none. Block-moves are align-1 struct-assigns (u8[8]) -> emit_block_move
// @class: struct
// @stuck: none — MATCH (74 ins)
// @class: regalloc-order + T1 memcpy-builtin→call re-crack
// @stuck: 0 (iso). Register lever = $16 pin + in-place re-tie on the memcpy-branch src (keeps
// @class: plumbing
// @stuck: none — MATCH
// @class: schedule
// @stuck: none — MATCH
// @class: struct
// @stuck: none — MATCH
// @class: struct
// @stuck: none — MATCH (63 ins)
// @class: struct
// @stuck: none — MATCH (62 ins)
// @class: struct
// @stuck: none — MATCH (65 ins)
// @class: regalloc-order
// @stuck: pending self-check — register order param=$s2 counter=$s1 ptr=$s0
// @class: plumbing
// @stuck: none — MATCH (expected); short-typed global increment + signed compare, store-2 on overflow
// @class: plumbing
// @stuck: none — MATCH expected (simple short-increment + guarded call)
// @class: regalloc-order
// @stuck: none — MATCH (branch-polarity invert: fn-ptr non-zero call is the fall-through arm)
// @class: regalloc-order
// @stuck: none — MATCH (83 ins). $s3 is a dual-copy of iVar3 used only in the ==0 tail block; natural C coalesces to one $s0, so pin iVar3=$s0 and iVar3b=$s3 (different hard regs prevent gcc coalescing the copy). Also: outer+inner branch polarity inverted (if!=0 / if!=0 puts both short blocks at the tail as beqz targets); base = (int)D_801B203C + idx*0x40 (materialize form, arg to callees).
// @class: regalloc-order
// @stuck: none — MATCH (223 ins). Giant GTE coord transform. Two levers: (1) vy = {int t=vy-0x10; t+(r&0x1f);}
// @class: schedule
// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// @class: regalloc-order
// @stuck: none — MATCH (145/145 ins, match_one confirmed)
// @class: regalloc-order
// @stuck: none — MATCH (168 ins). Keys: (1) pin param->$s1 via `register int self __asm__("$17")=param_1`
// @class: schedule
// @stuck: none — MATCH (132 ins, match_one). Levers: (1) block2 statement order — compute sv1.vz (with the *(p+0xe) load) right after the 2nd call so gcc hoists that load into $v1, forcing the sv2.vx=sv1.vx copy through $a3, which globally pushes every `func*param>>12` product from $a3 to $t0; (2) sv2 store order vx-before-vy; (3) SHARED return-0 join via gotos placed BEFORE the copy block (ret0: before docopy:) — this blocks gcc's conditional-jump-over-jump inversion + return-threading, so the copy block falls through to the epilogue with v0=1 preset in the beqz delay slot (drops the extra `li v0,1`).
// @class: plumbing
// @stuck: none — MATCH (126 ins). Keys: (1) cVar1 as `int` (not unsigned char) so the
// @class: schedule
// @stuck: none — MATCH; success-block placed last via `goto big` (bnez forward into epilogue), single cae4 merge kept
// @class: plumbing
// @stuck: none — MATCH (126 ins). Keys: (1) cVar1 as `int` (not unsigned char) so the
// @class: struct
// @stuck: none — MATCH
// @class: schedule
// @stuck: none — MATCH. Two levers: (1) split rand()-result into its own var (shared iVar1 forced an extra move a0,v0); (2) reorder decrement before sp[0] to group the two lhu loads as target's scheduler does; (3) materialize &D_80126B96 via a local u16* to CSE the address (lui+addiu once) instead of %hi/%lo split-per-access.
@@ -0,0 +1,371 @@
=== lever-free bodies in ov_SC06_010 sharing a callee or global with func_8018179C (10 found; top 6 by shared symbols) — read them for the SHAPE ===
--- func_8017FE3C (src/ov_SC06_010/ov_SC06_010_jr_8017A4AC.c:5844) shares 6: func_8012B1B4 func_8012B608 func_8012B744 func_8012BE54 func_8012BE98 func_8012CBCC ---
void func_8017FE3C(s32 a0)
{
s16 hi;
s16 pos;
s32 sp10[3];
s32 r;
u16 state;
s32 tmp0;
hi = *(s16 *)(a0 + 0x8A);
pos = *(s16 *)(a0 + 0xA);
if (pos >= hi - 8) {
if (*(s32 *)(a0 + 0x48) >= 0) {
*(s32 *)(a0 + 0x48) = -0x8000;
*(s32 *)(a0 + 0x14) = *(s32 *)(a0 + 0x14) >> 1;
}
} else {
if (hi + 8 >= pos) {
if (*(s32 *)(a0 + 0x48) <= 0) {
*(s32 *)(a0 + 0x48) = 0x8000;
*(s32 *)(a0 + 0x14) = *(s32 *)(a0 + 0x14) >> 1;
}
}
}
if (*(s32 *)(a0 + 0xDC) < -0x40000) {
*(s32 *)(a0 + 0xDC) = -0x40000;
}
sp10[0] = 0;
sp10[1] = 0;
sp10[2] = *(s32 *)(a0 + 0xDC);
func_8012B1B4(a0, (s32)sp10);
func_8012CBCC(a0);
if (0x1323F < *(s16 *)(a0 + 6) * *(s16 *)(a0 + 6) +
(*(s16 *)(a0 + 0xA) + 0x482) * (*(s16 *)(a0 + 0xA) + 0x482)) {
func_8012ADE4(a0);
*(s32 *)(a0 + 0x14) = 0;
}
state = *(u16 *)(a0 + 0x34);
switch (state) {
case 0: {
s32 p20;
s32 ret;
s32 p744;
s32 v1p;
s16 snd;
s32 b608;
ret = ((s32 (*)(s32, u16 *))func_8012BE98)(a0, (u16 *)(a0 + 0x88));
if (ret <= 0x3FFFF) {
goto set_state1;
}
p744 = func_8012B744((void *)(a0 + 4), (void *)(a0 + 0x88));
v1p = *(s32 *)(a0 + 0x20);
snd = *(s16 *)(v1p + 0x12);
b608 = func_8012B608(snd, p744, 8);
p20 = *(s32 *)(a0 + 0x20);
*(u16 *)(p20 + 0x12) = *(u16 *)(p20 + 0x12) + b608;
tmp0 = *(s32 *)(a0 + 0x20);
v1p = tmp0;
*(u16 *)(v1p + 0x12) = *(u16 *)(v1p + 0x12) & 0xFFF;
func_8012B1B4(a0, (s32)sp10);
break;
}
case 1: {
s32 ret;
s32 t;
*(s32 *)(a0 + 0xDC) = *(s32 *)(a0 + 0xDC) << 1;
ret = ((s32 (*)(s32, u16 *))func_8012BE98)(a0, (u16 *)(a0 + 0x88));
t = ret > 0x3FFFF;
if (t == 0) {
break;
}
goto rand_tail;
}
case 2: {
s32 p744;
s32 v1p;
s16 snd;
s32 b608;
s32 p20;
p744 = func_8012B744((void *)(a0 + 4), (void *)(a0 + 0x88));
v1p = *(s32 *)(a0 + 0x20);
snd = *(s16 *)(v1p + 0x12);
b608 = func_8012B608(snd, p744, 0x10);
p20 = *(s32 *)(a0 + 0x20);
*(u16 *)(p20 + 0x12) = *(u16 *)(p20 + 0x12) + b608;
v1p = *(s32 *)(a0 + 0x20);
*(u16 *)(v1p + 0x12) = *(u16 *)(v1p + 0x12) & 0xFFF;
*(s32 *)(a0 + 0xDC) = *(s32 *)(a0 + 0xDC) >> 1;
if (*(s16 *)(a0 + 0x102) == 0) {
state = 3;
goto store_state;
}
*(s16 *)(a0 + 0x102) = *(s16 *)(a0 + 0x102) - 1;
goto end_switch;
}
case 3: {
s32 ret;
s32 p744;
s32 v1p;
s16 snd;
s32 b608;
ret = ((s32 (*)(s32, u16 *))func_8012BE98)(a0, (u16 *)(a0 + 0x88));
*(s32 *)(a0 + 0xDC) = *(s32 *)(a0 + 0xDC) << 1;
if (ret > 0x40000) {
p744 = func_8012B744((void *)(a0 + 4), (void *)(a0 + 0x88));
v1p = *(s32 *)(a0 + 0x20);
snd = *(s16 *)(v1p + 0x12);
b608 = func_8012B608(snd, p744, 1);
if ((u32)(b608 + 0xFF) < 0x1FF) {
goto end_switch;
}
goto rand_tail;
}
goto set_state1;
}
}
goto end_switch;
rand_tail:
*(u16 *)(a0 + 0x34) = 2;
r = rand();
*(s16 *)(a0 + 0x102) = (r & 7) + 8;
goto end_switch;
set_state1:
state = 1;
store_state:
*(u16 *)(a0 + 0x34) = state;
end_switch:
if (*(s16 *)(a0 + 0x100) != 0) {
*(s16 *)(a0 + 0x100) = *(s16 *)(a0 + 0x100) - 1;
} else {
s32 ret3;
ret3 = ((s32 (*)(s32))func_8012BE54)(a0);
if (ret3 <= 0x24000) {
*(s16 *)(a0 + 0x2) = 2;
*(s16 *)(a0 + 0x100) = 0x3C;
}
}
}
--- func_801825DC (src/ov_SC06_010/ov_SC06_010_jr_8017A4AC.c:7549) shares 3: func_8012B1B4 func_8012CBCC func_801810FC ---
void func_801825DC(s32 a0)
{
extern s32 D_80126B60;
s32 sp10[3];
if (*(s32 *)(a0 + 8) >= D_80126B60 - 0x200000) {
if (*(s32 *)(a0 + 0x48) >= 0) {
*(s32 *)(a0 + 0x48) = -0x8000;
*(s32 *)(a0 + 0x14) = *(s32 *)(a0 + 0x14) >> 1;
}
} else {
if (D_80126B60 - 0x180000 >= *(s32 *)(a0 + 8)) {
if (*(s32 *)(a0 + 0x48) <= 0) {
*(s32 *)(a0 + 0x48) = 0x8000;
*(s32 *)(a0 + 0x14) = *(s32 *)(a0 + 0x14) >> 1;
}
}
}
*(s32 *)(a0 + 0xDC) = *(s32 *)(a0 + 0xDC) >> 1;
sp10[0] = 0;
sp10[1] = 0;
sp10[2] = *(s32 *)(a0 + 0xDC);
func_8012B1B4(a0, (s32)sp10);
func_8012CBCC(a0);
func_801810FC(a0, 0x51);
*(s16 *)(*(s32 *)(a0 + 0x20) + 0x12) += func_8012B8E4(a0, 0x10);
*(u16 *)(*(s32 *)(a0 + 0x20) + 0x12) &= 0xFFF;
*(u16 *)(a0 + 0x100) -= 1;
if (*(s16 *)(a0 + 0x100) == 0) {
*(s16 *)(a0 + 2) = 3;
*(u16 *)(a0 + 0x100) = 5;
*(s32 *)(a0 + 0x1C) = 0;
}
}
--- func_8017AE2C (src/ov_SC06_010/ov_SC06_010_jr_8017A4AC.c:2787) shares 3: func_8012B608 func_8012B744 func_8012BE98 ---
void func_8017AE2C(s32 param_1) {
extern s16 D_801B2BD8;
extern s16 D_801B2BDA;
extern s16 D_801B2BE4;
s32 pv = param_1;
s16 *g = &D_801B2BD8;
switch (g[0]) {
case 0:
default:
return;
case 1:
g[1] = (u16)g[1] - 1;
if (g[1] <= 0) {
*(u16 *)(*(s32 *)(pv + 0x20) + 0x12) = (u16)g[2];
goto reset_both;
}
{
s32 r = func_8012B608(*(s16 *)(*(s32 *)(pv + 0x20) + 0x12), g[2], 6);
*(u16 *)(*(s32 *)(pv + 0x20) + 0x12) =
*(u16 *)(*(s32 *)(pv + 0x20) + 0x12) + r;
}
return;
case 2:
func_8012B178(pv, (s32)g[4] << 8);
func_8012AD80(pv);
*(u16 *)(pv + 0xA) -= 8;
((s32 (*)(u8 *))func_8012B030)((u8 *)pv);
break;
case 3:
if (g[1] != 0) {
if (g[5] != 0) {
void *p = (void *)(pv + 4);
if ((s16)func_80012A60(*(s16 *)(*(s32 *)(pv + 0x20) + 0x12),
(s16)func_8012B744(p, &g[6])) < 0x100) {
g[1] = 0;
}
*(s16 *)(*(s32 *)(pv + 0x20) + 0x12) =
func_8012B744(p, &D_801B2BE4);
func_8012B178(pv, 0xFFFA0000);
func_8012AD80(pv);
*(u16 *)(pv + 0xA) -= 8;
((s32 (*)(u8 *))func_8012B030)((u8 *)pv);
/* &D_801B2BD8+0xC == &D_801B2BE4; distinct rtx defeats gcc's address-CSE
so BE98's arg rematerializes instead of sharing the store's reg (byte-gate). */
if (func_8012BE98(pv, (u16 *)((s32)&D_801B2BD8 + 0xC)) < 0x101) {
D_801B2BD8 = 0;
D_801B2BDA = 0;
}
}
{
s32 t = func_8012B744((void *)(pv + 4), &g[6]);
s32 r = func_8012B608(*(s16 *)(*(s32 *)(pv + 0x20) + 0x12), t, g[3]);
*(u16 *)(*(s32 *)(pv + 0x20) + 0x12) =
*(u16 *)(*(s32 *)(pv + 0x20) + 0x12) + r;
}
g[1] = (u16)g[1] - 1;
if (g[1] > 0) {
return;
}
g[1] = 0;
return;
}
*(s16 *)(*(s32 *)(pv + 0x20) + 0x12) =
func_8012B744((void *)(pv + 4), &D_801B2BE4);
func_8012B178(pv, 0xFFFA0000);
func_8012AD80(pv);
*(u16 *)(pv + 0xA) -= 8;
((s32 (*)(u8 *))func_8012B030)((u8 *)pv);
/* see note above: distinct rtx for the same address defeats address-CSE. */
if (func_8012BE98(pv, (u16 *)((s32)&D_801B2BD8 + 0xC)) < 0x101) {
D_801B2BD8 = 0;
D_801B2BDA = 0;
}
return;
case 4:
func_8012AD80(pv);
}
g[1] = (u16)g[1] - 1;
if (g[1] > 0) {
return;
}
reset_both:
g[0] = 0;
g[1] = 0;
return;
}
--- func_801857F4 (src/ov_SC06_010/ov_SC06_010_jr_8017A4AC.c:9471) shares 2: func_8012B1B4 func_8012CBCC ---
void func_801857F4(s32 a0) {
extern u8 D_801A71A4[];
extern u8 D_801AE960[];
extern u8 D_801AEA50[];
extern u8 D_801AEB40[];
s32 pad[4];
func_8012B1B4(a0, (s32)D_801A71A4);
func_8012CBCC(a0);
func_80182F4C(a0, 0x48);
*(s16 *)(*(s32 *)(a0 + 0x20) + 0x12) += func_8012B8E4(a0, 0x10);
*(u16 *)(*(s32 *)(a0 + 0x20) + 0x12) &= 0xFFF;
*(u16 *)(a0 + 0x100) -= 1;
if (*(s16 *)(a0 + 0x100) == 0) {
*(s16 *)(a0 + 2) = 6;
*(u16 *)(a0 + 0x100) = 0x2D;
*(s32 *)(a0 + 0x1C) = 0;
*(s16 *)(a0 + 0x104) = 0;
func_8012A828(a0, D_801AE960);
if (*(s32 *)(a0 + 0xCC) != 0) {
func_8012A828(*(s32 *)(a0 + 0xCC), D_801AEA50);
}
if (*(s32 *)(a0 + 0xD0) != 0) {
func_8012A828(*(s32 *)(a0 + 0xD0), D_801AEB40);
}
}
}
--- func_80180170 (src/ov_SC06_010/ov_SC06_010_jr_8017A4AC.c:6004) shares 2: func_8012B1B4 func_8012CBCC ---
void func_80180170(s32 a0)
{
extern s32 D_80126B60;
s32 sp10[3];
if (*(s32 *)(a0 + 8) >= D_80126B60 - 0x200000) {
if (*(s32 *)(a0 + 0x48) >= 0) {
*(s32 *)(a0 + 0x48) = -0x8000;
*(s32 *)(a0 + 0x14) = *(s32 *)(a0 + 0x14) >> 1;
}
} else {
if (D_80126B60 - 0x180000 >= *(s32 *)(a0 + 8)) {
if (*(s32 *)(a0 + 0x48) <= 0) {
*(s32 *)(a0 + 0x48) = 0x8000;
*(s32 *)(a0 + 0x14) = *(s32 *)(a0 + 0x14) >> 1;
}
}
}
*(s32 *)(a0 + 0xDC) = *(s32 *)(a0 + 0xDC) >> 1;
sp10[0] = 0;
sp10[1] = 0;
sp10[2] = *(s32 *)(a0 + 0xDC);
func_8012B1B4(a0, (s32)sp10);
func_8012CBCC(a0);
if (0x1323F < *(s16 *)(a0 + 6) * *(s16 *)(a0 + 6) +
(*(s16 *)(a0 + 0xA) + 0x482) * (*(s16 *)(a0 + 0xA) + 0x482)) {
func_8012ADE4(a0);
*(s32 *)(a0 + 0x14) = 0;
}
*(s16 *)(*(s32 *)(a0 + 0x20) + 0x12) += func_8012B8E4(a0, 0x10);
*(u16 *)(*(s32 *)(a0 + 0x20) + 0x12) &= 0xFFF;
*(u16 *)(a0 + 0x100) -= 1;
if (*(s16 *)(a0 + 0x100) == 0) {
*(s16 *)(a0 + 2) = 3;
*(u16 *)(a0 + 0x100) = 5;
*(s32 *)(a0 + 0x1C) = 0;
}
}
--- func_8012BE54 (src/shared/ov/func_8012BE54.h:7) shares 1: func_8012BE98 ---
void func_8012BE54(s32 a0) {
u16 sp[3];
sp[0] = D_80126B5E;
sp[1] = D_80126B62;
sp[2] = D_80126B66;
func_8012BE98(a0, sp);
}
@@ -0,0 +1,109 @@
src/ov_SC06_010/ov_SC06_010_jr_8017A4AC.c:func_8018179C: score 63 (MIXED; mine 207 ins, target 207) — not yet
register pairs (mine -> target, count): s0->s1 x54, s1->s0 x5, a0->v1 x4, v1->a0 x3
replace mine[1:3] target[1:3]
1 sw s0,48(sp) | sw s1,52(sp)
2 move s0,a0 | move s1,a0
replace mine[5:8] target[5:8]
5 sw s1,52(sp) | sw s0,48(sp)
6 lh a0,138(s0) | lh a0,138(s1)
7 lh v1,10(s0) | lh v1,10(s1)
replace mine[12:13] target[12:13]
12 lw v0,72(s0) | lw v0,72(s1)
replace mine[16:17] target[16:17]
16 lw v0,20(s0) | lw v0,20(s1)
replace mine[18:19] target[18:19]
18 sw v1,72(s0) | sw v1,72(s1)
replace mine[22:23] target[22:23]
22 lw v0,72(s0) | lw v0,72(s1)
replace mine[26:28] target[26:28]
26 lw v0,20(s0) | lw v0,20(s1)
27 sw v1,72(s0) | sw v1,72(s1)
replace mine[29:31] target[29:31]
29 sw v0,20(s0) | sw v0,20(s1)
30 lw v0,220(s0) | lw v0,220(s1)
replace mine[35:37] target[35:37]
35 sw v1,220(s0) | sw v1,220(s1)
36 move a0,s0 | move a0,s1
replace mine[39:40] target[39:40]
39 lw v0,220(s0) | lw v0,220(s1)
replace mine[44:46] target[44:46]
44 move a0,s0 | move a0,s1
45 lhu v1,52(s0) | lhu v1,52(s1)
replace mine[52:53] target[52:53]
52 move a0,s0 | move a0,s1
replace mine[59:60] target[59:60]
59 move a0,s0 | move a0,s1
replace mine[62:63] target[62:63]
62 addiu s1,s0,136 | addiu s0,s1,136
replace mine[64:65] target[64:65]
64 move a1,s1 | move a1,s0
replace mine[69:71] target[69:71]
69 addiu a0,s0,4 | addiu a0,s1,4
70 move a0,s0 | move a0,s1
replace mine[74:75] target[74:75]
74 addiu a0,s0,4 | addiu a0,s1,4
replace mine[76:78] target[76:78]
76 move a1,s1 | move a1,s0
77 lw v1,32(s0) | lw v1,32(s1)
replace mine[82:83] target[82:83]
82 lw v1,32(s0) | lw a0,32(s1)
replace mine[84:85] target[84:85]
84 lhu a0,18(v1) | lhu v1,18(a0)
replace mine[86:89] target[86:89]
86 addu a0,a0,v0 | addu v1,v1,v0
87 sh a0,18(v1) | sh v1,18(a0)
88 lw v1,32(s0) | lw v1,32(s1)
replace mine[91:92] target[91:92]
91 move a0,s0 | move a0,s1
replace mine[97:100] target[97:100]
97 move a0,s0 | move a0,s1
98 lw v0,220(s0) | lw v0,220(s1)
99 addiu a1,s0,136 | addiu a1,s1,136
replace mine[102:103] target[102:103]
102 sw v0,220(s0) | sw v0,220(s1)
replace mine[108:109] target[108:109]
108 move a0,s0 | move a0,s1
replace mine[115:116] target[115:116]
115 addiu a0,s0,4 | addiu a0,s1,4
replace mine[117:119] target[117:119]
117 addiu a1,s0,136 | addiu a1,s1,136
118 lw v1,32(s0) | lw v1,32(s1)
replace mine[123:124] target[123:124]
123 lw a0,32(s0) | lw a0,32(s1)
replace mine[129:130] target[129:130]
129 lw v1,32(s0) | lw v1,32(s1)
replace mine[135:137] target[135:137]
135 lw v0,220(s0) | lw v0,220(s1)
136 move a0,s0 | move a0,s1
replace mine[139:141] target[139:141]
139 sw v0,220(s0) | sw v0,220(s1)
140 lh v0,258(s0) | lh v0,258(s1)
replace mine[148:150] target[148:150]
148 sh v0,258(s0) | sh v0,258(s1)
149 addiu s2,s0,136 | addiu s2,s1,136
replace mine[152:153] target[152:153]
152 move a0,s0 | move a0,s1
replace mine[154:156] target[154:156]
154 lw v1,220(s0) | lw v1,220(s1)
155 move s1,v0 | move s0,v0
replace mine[158:159] target[158:159]
158 sw v1,220(s0) | sw v1,220(s1)
replace mine[162:163] target[162:163]
162 slt v0,v0,s1 | slt v0,v0,s0
replace mine[164:165] target[164:165]
164 addiu a0,s0,4 | addiu a0,s1,4
replace mine[167:168] target[167:168]
167 lw v1,32(s0) | lw v1,32(s1)
replace mine[177:178] target[177:178]
177 sh v0,52(s0) | sh v0,52(s1)
replace mine[181:182] target[181:182]
181 sh v0,258(s0) | sh v0,258(s1)
replace mine[183:185] target[183:185]
183 sh v0,52(s0) | sh v0,52(s1)
184 lh v0,256(s0) | lh v0,256(s1)
replace mine[191:192] target[191:192]
191 move a0,s0 | move a0,s1
replace mine[197:198] target[197:198]
197 sh v0,2(s0) | sh v0,2(s1)
replace mine[199:200] target[199:200]
199 sh v0,256(s0) | sh v0,256(s1)
@@ -0,0 +1,3 @@
NEEDED pin $16 line 7097
NEEDED pin $4 line 7103
REMOVED pin $18 line 7161
@@ -0,0 +1,2 @@
src/ov_SC06_010/ov_SC06_010_jr_8017A4AC.c
func_8018179C
+67 -67
View File
@@ -5,6 +5,7 @@
"gte_mnemonics": {
"gte_SetRotMatrix": 249,
"gte_SetTransMatrix": 229,
"gte_avsz3": 25,
"gte_avsz4": 56,
"gte_dpcl": 134,
"gte_ldclmv": 72,
@@ -12,7 +13,6 @@
"gte_ldv0": 757,
"gte_ldv3": 177,
"gte_ldv3c": 184,
"gte_nccs": 25,
"gte_nclip": 108,
"gte_rtir": 75,
"gte_rtps": 437,
@@ -53,7 +53,7 @@
},
"kinds": {
"asm-body/direct": 13,
"barrier/direct": 360,
"barrier/direct": 359,
"barrier/via-macro": 2,
"gte-lever/direct": 362,
"gte-lever/via-macro": 94,
@@ -62,8 +62,8 @@
"gte/via-macro": 6128,
"instruction/direct": 210,
"instruction/via-macro": 22,
"keepalive/direct": 354,
"launder/direct": 716,
"keepalive/direct": 349,
"launder/direct": 714,
"launder/via-macro": 42,
"verbatim-body/direct": 2682
}
@@ -72,54 +72,54 @@
"cfake_markers": {
"count": 13,
"sample": [
"src/ov_SC04_002/ov_SC04_002_jr_8017BEBC.c:10089",
"src/ov_SC04_005/ov_SC04_005_jr_8017BEBC.c:9325",
"src/md_SC07_003/md_SC07_003.c:3577",
"src/md_SC07_004/md_SC07_004.c:280",
"src/ov_SC01_009/ov_SC01_009_jr_8017E590.c:4271",
"src/ov_SC01_080/ov_SC01_080_jr_8017AE2C.c:5178",
"src/ov_SC02_028/ov_SC02_028_jr_8017D898.c:5475",
"src/ov_SC02_041/ov_SC02_041_jr_8017BEBC.c:7554",
"src/ov_SC04_007/ov_SC04_007_jr_8017BEBC.c:6638",
"src/ov_SC05_001/ov_SC05_001_jr_8017BEBC.c:5814",
"src/ov_SC05_003/ov_SC05_003_jr_8017BEBC.c:4815",
"src/ov_SC05_005/ov_SC05_005_jr_8017D898.c:4026",
"src/ov_SC05_007/ov_SC05_007_jr_8017BEBC.c:3335",
"src/ov_SC02_041/ov_SC02_041_jr_8017BEBC.c:7554",
"src/ov_SC04_002/ov_SC04_002_jr_8017BEBC.c:10112",
"src/ov_SC04_005/ov_SC04_005_jr_8017BEBC.c:9325",
"src/ov_SC04_007/ov_SC04_007_jr_8017BEBC.c:6638"
"src/ov_SC05_007/ov_SC05_007_jr_8017BEBC.c:3335"
]
},
"classes": {
"A": {
"bodies": 1632,
"distinct_bodies": 753,
"bodies": 1622,
"distinct_bodies": 745,
"file_scope": 0,
"in_bodies": 2578,
"in_bodies": 2565,
"kinds": {
"pin": 2578
"pin": 2565
},
"marked": 2578,
"sites": 2578,
"tus": 1109,
"marked": 2565,
"sites": 2565,
"tus": 1106,
"unmarked": 0
},
"B": {
"bodies": 4775,
"distinct_bodies": 817,
"bodies": 4769,
"distinct_bodies": 813,
"file_scope": 13,
"in_bodies": 11443,
"in_bodies": 11435,
"kinds": {
"asm-body": 13,
"barrier": 362,
"barrier": 361,
"gte": 6328,
"gte-lever": 456,
"gte-unsigned": 271,
"instruction": 232,
"keepalive": 354,
"launder": 758,
"keepalive": 349,
"launder": 756,
"verbatim-body": 2682
},
"marked": 2665,
"sites": 11456,
"tus": 1434,
"marked": 2657,
"sites": 11448,
"tus": 1432,
"unmarked": 8791
},
"C": {
@@ -224,9 +224,9 @@
"coverage": {
"asm": {
"comment_dead": 6782,
"live": 15688,
"live": 15667,
"macro_block": 194,
"raw": 22664
"raw": 22643
},
"attribute": {
"comment_dead": 0,
@@ -242,9 +242,9 @@
},
"register": {
"comment_dead": 8570,
"live": 2628,
"live": 2615,
"macro_block": 18,
"raw": 11216
"raw": 11203
},
"volatile": {
"comment_dead": 2607,
@@ -254,7 +254,7 @@
}
},
"coverage_ok": true,
"elapsed_s": 40.5,
"elapsed_s": 32.0,
"generated": "2026-09-10",
"gte_levers": {
"direct": 362,
@@ -265,15 +265,15 @@
"via_macro": 94,
"what": "GTE ops whose clobbers exceed the canonical macro's (a scheduling steer): class-B levers INSIDE the headline number since T5 (2026-09-09), marked, 0 at the close"
},
"head": "91ae94a64",
"head": "13069c142",
"headers": 3181,
"levers_AB": {
"asm": 2175,
"bodies": 2383,
"distinct_bodies": 1019,
"marked": 4753,
"pins": 2578,
"sites": 4753,
"asm": 2167,
"bodies": 2373,
"distinct_bodies": 1011,
"marked": 4732,
"pins": 2565,
"sites": 4732,
"unmarked": 0,
"what": "register pins + asm statements excluding GTE ops: the classes the phase drives to 0"
},
@@ -312,24 +312,14 @@
5,
1
],
[
"DRAW",
3,
1
],
[
"gte_SetRotMatrix_m",
3,
2
],
[
"gte_rtv0tr_m",
2,
1
],
[
"gte_SetTransMatrix_m",
2,
"DRAW",
3,
1
],
[
@@ -342,6 +332,16 @@
2,
1
],
[
"gte_rtv0tr_m",
2,
1
],
[
"gte_SetTransMatrix_m",
2,
1
],
[
"gte_rt",
1,
@@ -407,9 +407,9 @@
},
"pins": {
"bare_name": 15,
"init": 247,
"init": 245,
"registers": {
"$0": 80,
"$0": 76,
"$10": 10,
"$11": 5,
"$12": 9,
@@ -420,18 +420,18 @@
"$17": 53,
"$18": 35,
"$19": 30,
"$2": 881,
"$2": 878,
"$20": 8,
"$21": 6,
"$22": 7,
"$23": 10,
"$25": 1,
"$29": 13,
"$3": 216,
"$4": 529,
"$3": 215,
"$4": 527,
"$5": 391,
"$6": 69,
"$7": 28,
"$6": 67,
"$7": 27,
"$8": 25,
"$9": 22,
"7": 1,
@@ -440,30 +440,30 @@
"v0": 2,
"v1": 3
},
"sites": 2578,
"sites": 2565,
"sp": 13,
"spelling": {
"__asm__": 2547,
"asm": 31
"__asm__": 2535,
"asm": 30
},
"volatile_qualified": 0,
"zero": 80
"zero": 76
},
"src_stamp": "10b8e8e36bdba05f",
"src_stamp": "3c3eb3589516cc0d",
"tus": 4121,
"unclassified": 0,
"union_AD": {
"bodies": 6121,
"bodies": 6111,
"by_kind": {
"main": 163,
"md": 120,
"ov": 5656,
"ov": 5649,
"resident": 10,
"shared": 172
"shared": 169
},
"copies_in_multi": 4939,
"distinct_bodies": 1325,
"multi_copy_classes": 143
"copies_in_multi": 4936,
"distinct_bodies": 1317,
"multi_copy_classes": 142
},
"verbatim_excluded": {
"functions": 13,
+14 -14
View File
@@ -1,32 +1,32 @@
lever_census: 218 binaries · 4,121 TUs + 3,181 headers · coverage OK · unclassified 0 · verbatim excluded 13 fn / 14 sites (manifest 13)
coverage asm raw 22664 = live 15688 + macro-block 194 + comment/dead 6782
coverage register raw 11216 = live 2628 + macro-block 18 + comment/dead 8570
coverage asm raw 22643 = live 15667 + macro-block 194 + comment/dead 6782
coverage register raw 11203 = live 2615 + macro-block 18 + comment/dead 8570
coverage volatile raw 4389 = live 1700 + macro-block 82 + comment/dead 2607
coverage builtin raw 599 = live 445 + macro-block 0 + comment/dead 154
coverage attribute raw 76 = live 76 + macro-block 0 + comment/dead 0
class sites in-bodies file-scope bodies distinct TUs marked unmarked kinds
A pins 2578 2578 0 1632 753 1109 2578 0 {'pin': 2578}
B asm 11456 11443 13 4775 817 1434 2665 8791 {'gte': 6328, 'barrier': 362, 'gte-lever': 456, 'gte-unsigned': 271, 'launder': 758, 'instruction': 232, 'asm-body': 13, 'keepalive': 354, 'verbatim-body': 2682}
C volatile 1590 1438 152 496 95 610 14 1576 {'cast': 1378, 'decl-body': 58, 'decl-file': 152, 'param': 2}
A pins 2565 2565 0 1622 745 1106 2565 0 {'pin': 2565}
B asm 11448 11435 13 4769 813 1432 2657 8791 {'barrier': 361, 'keepalive': 349, 'gte': 6328, 'launder': 756, 'asm-body': 13, 'gte-lever': 456, 'gte-unsigned': 271, 'instruction': 232, 'verbatim-body': 2682}
C volatile 1590 1438 152 496 95 610 14 1576 {'decl-file': 152, 'cast': 1378, 'decl-body': 58, 'param': 2}
D register 50 50 0 47 47 6 0 50 {'register': 50}
E asm-label 7780 1357 6423 1089 153 2090 0 7780 {'asm-label': 7780}
F builtin 445 445 0 428 27 302 0 445 {'builtin': 445}
G attribute 76 1 75 1 1 40 0 76 {'attribute': 76}
UNION A–D: 6,121 bodies · 1,325 distinct (addresses normalized) · 143 multi-copy classes holding 4,939 bodies · by kind {'ov': 5656, 'main': 163, 'md': 120, 'shared': 172, 'resident': 10}
THE PHASE'S NUMBER (pins + asm statements, GTE excluded): 4,753 sites in 2,383 bodies (1,019 distinct) · marked !FAKE 4,753 · UNMARKED 0
UNION A–D: 6,111 bodies · 1,317 distinct (addresses normalized) · 142 multi-copy classes holding 4,936 bodies · by kind {'ov': 5649, 'main': 163, 'shared': 169, 'md': 120, 'resident': 10}
THE PHASE'S NUMBER (pins + asm statements, GTE excluded): 4,732 sites in 2,373 bodies (1,011 distinct) · marked !FAKE 4,732 · UNMARKED 0
orphan !FAKE markers (no pin/asm site on the line nor below): 0
marked ordinary-C fakes kept by Drew's S104 ruling (a) (`do { } while (0)`, dead initialisers; NOT levers): 13
GTE levers (clobbers beyond the canonical macro's): 456 sites (94 via a variant macro, 362 direct) · marked 456 · UNMARKED 0 · unsigned GTE statements 271
per-TU asm macro definitions outside the GTE header: 314 {'launder': 154, 'gte': 150, 'instruction': 9, 'barrier': 1} (GTE variants 64)
pins: 2,578 · $0 80 · $sp 13 · with initializer 247 · volatile-qualified 0 · bare-name 15 · spellings {'__asm__': 2547, 'asm': 31}
per-TU asm macro definitions outside the GTE header: 314 {'gte': 150, 'launder': 154, 'instruction': 9, 'barrier': 1} (GTE variants 64)
pins: 2,565 · $0 76 · $sp 13 · with initializer 245 · volatile-qualified 0 · bare-name 15 · spellings {'__asm__': 2535, 'asm': 30}
whole-body asm routines in C shells, manifest PERMANENT (hand asm, NOT levers): 22 routines · 2,682 sites (2,660 private copies + 22 shared headers); asm-bodies NOT permanent (levers): 13 site(s) ['func_8001E378:DECOMPILE-NOW', 'func_80020F34:DECOMPILE-NOW', 'func_800249F0:DECOMPILE-NOW', 'func_80025CBC:DECOMPILE-NOW', 'func_80026514:UNCERTAIN', 'func_800268D0:UNCERTAIN', 'func_80027058:DECOMPILE-NOW', 'func_80027200:DECOMPILE-NOW', 'func_800CBA44:DECOMPILE-NOW', 'func_8017D810:DECOMPILE-NOW', 'func_8017E26C:UNCERTAIN', 'func_80184440:DECOMPILE-NOW', 'func_801A3BCC:DECOMPILE-NOW']
asm kinds: {'asm-body/direct': 13, 'barrier/direct': 360, 'barrier/via-macro': 2, 'gte/direct': 200, 'gte/via-macro': 6128, 'gte-lever/direct': 362, 'gte-lever/via-macro': 94, 'gte-unsigned/direct': 271, 'instruction/direct': 210, 'instruction/via-macro': 22, 'keepalive/direct': 354, 'launder/direct': 716, 'launder/via-macro': 42, 'verbatim-body/direct': 2682}
instruction mnemonics: {'la': 142, 'addu': 23, 'addiu': 22, 'RTP_SND': 22, '.section': 7, 'lui': 4, 'lh': 3, 'and': 2, 'mult': 1, 'mfhi': 1, 'li': 1, 'sll': 1, 'lw': 1, 'nop': 1, 'srl': 1}
gte mnemonics: {'gte_ldv0': 757, 'gte_stlvnl': 593, 'gte_stsxy': 447, 'gte_rtps': 437, 'gte_stflg': 415, 'gte_rtpt': 352, 'gte_SetRotMatrix': 249, 'gte_stsxy3': 236, 'gte_SetTransMatrix': 229, 'gte_rtv0tr': 228, 'gte_ldv3c': 184, 'gte_ldv3': 177, 'gte_stsv': 161, 'lwc2': 159, 'gte_stsz4': 149, 'gte_stsz3': 147, 'gte_stszotz': 134, 'gte_dpcl': 134, 'gte_stsxy3_f3': 111, 'gte_stclmv': 108, 'gte_nclip': 108, 'gte_stopz': 108, 'gte_stsxy3c': 108, 'gte_stsxy3_ft3': 79, 'gte_rtir': 75, 'gte_ldclmv': 72, 'gte_avsz4': 56, 'gte_stotz': 52, 'gte_ldrgb': 30, 'gte_nccs': 25}
asm-bearing macro definitions: 314 (20 names, 3 with >1 text) kinds {'launder': 154, 'gte': 150, 'instruction': 9, 'barrier': 1}
asm kinds: {'asm-body/direct': 13, 'barrier/direct': 359, 'barrier/via-macro': 2, 'gte/direct': 200, 'gte/via-macro': 6128, 'gte-lever/direct': 362, 'gte-lever/via-macro': 94, 'gte-unsigned/direct': 271, 'instruction/direct': 210, 'instruction/via-macro': 22, 'keepalive/direct': 349, 'launder/direct': 714, 'launder/via-macro': 42, 'verbatim-body/direct': 2682}
instruction mnemonics: {'la': 142, 'addu': 23, 'addiu': 22, 'RTP_SND': 22, '.section': 7, 'lui': 4, 'lh': 3, 'and': 2, 'mult': 1, 'mfhi': 1, 'sll': 1, 'li': 1, 'lw': 1, 'nop': 1, 'srl': 1}
gte mnemonics: {'gte_ldv0': 757, 'gte_stlvnl': 593, 'gte_stsxy': 447, 'gte_rtps': 437, 'gte_stflg': 415, 'gte_rtpt': 352, 'gte_SetRotMatrix': 249, 'gte_stsxy3': 236, 'gte_SetTransMatrix': 229, 'gte_rtv0tr': 228, 'gte_ldv3c': 184, 'gte_ldv3': 177, 'gte_stsv': 161, 'lwc2': 159, 'gte_stsz4': 149, 'gte_stsz3': 147, 'gte_stszotz': 134, 'gte_dpcl': 134, 'gte_stsxy3_f3': 111, 'gte_nclip': 108, 'gte_stopz': 108, 'gte_stsxy3c': 108, 'gte_stclmv': 108, 'gte_stsxy3_ft3': 79, 'gte_rtir': 75, 'gte_ldclmv': 72, 'gte_avsz4': 56, 'gte_stotz': 52, 'gte_ldrgb': 30, 'gte_avsz3': 25}
asm-bearing macro definitions: 314 (20 names, 3 with >1 text) kinds {'gte': 150, 'launder': 154, 'instruction': 9, 'barrier': 1}
controls (R39):
src/800.c func_800226C0 pins got 14 expected 45 N-A
src/shared/ov/func_80178004.h pins got 8 expected 26 N-A
ov_SC03_006 func_80184034 bare-name pins got 0 expected 3 N-A
engine_prelude.h asm sites (a macro definition only) got 0 expected 0 OK
elapsed 40.5 s
elapsed 32.0 s
+1
View File
@@ -56,3 +56,4 @@ date milestone head sites_AB pins asm bodies_AB distinct_AB marked unmarked gte_
2026-09-10 S103 end: c51 func_8012E364 2 levers (134); scrub of 46 orphan markers 94520756e 5097 2798 2299 2569 1097 5097 0 456 314 1590 50 7782 445 76
2026-09-10 S104 T7: free sweep (5 classes) + agents d1–d9 (all 0; 8 with zero levers, d4 one marked do-while) 910875139 4963 2730 2233 2498 1077 4963 0 456 314 1590 50 7782 445 76
2026-09-10 S104 T7: sweeps (all-families, R27) + agents d11–d19 all at 0 with zero levers 91ae94a64 4753 2578 2175 2383 1019 4753 0 456 314 1590 50 7780 445 76
2026-09-10 S104 T7: d17 + R28–R33 pass (4) + R27 remainder 13069c142 4732 2565 2167 2373 1011 4732 0 456 314 1590 50 7780 445 76
1 date milestone head sites_AB pins asm bodies_AB distinct_AB marked unmarked gte_levers per_tu_asm_macros class_C class_D class_E class_F class_G
56 2026-09-10 S103 end: c51 func_8012E364 2 levers (134); scrub of 46 orphan markers 94520756e 5097 2798 2299 2569 1097 5097 0 456 314 1590 50 7782 445 76
57 2026-09-10 S104 T7: free sweep (5 classes) + agents d1–d9 (all 0; 8 with zero levers, d4 one marked do-while) 910875139 4963 2730 2233 2498 1077 4963 0 456 314 1590 50 7782 445 76
58 2026-09-10 S104 T7: sweeps (all-families, R27) + agents d11–d19 all at 0 with zero levers 91ae94a64 4753 2578 2175 2383 1019 4753 0 456 314 1590 50 7780 445 76
59 2026-09-10 S104 T7: d17 + R28–R33 pass (4) + R27 remainder 13069c142 4732 2565 2167 2373 1011 4732 0 456 314 1590 50 7780 445 76
+5 -1
View File
@@ -102,6 +102,7 @@ counted, not marked). E, F and G belong to the canonical type layer and are the
| 2026-09-10 | S103 end: c51 func_8012E364 2 levers (134); scrub of 46 orphan markers | 2798 | 2299 | **5097** | 2569 | 1097 | 456 | 314 | 1590 | 50 | 7782 | 445 | 76 | `94520756e` |
| 2026-09-10 | S104 T7: free sweep (5 classes) + agents d1–d9 (all 0; 8 with zero levers, d4 one marked do-while) | 2730 | 2233 | **4963** | 2498 | 1077 | 456 | 314 | 1590 | 50 | 7782 | 445 | 76 | `910875139` |
| 2026-09-10 | S104 T7: sweeps (all-families, R27) + agents d11–d19 all at 0 with zero levers | 2578 | 2175 | **4753** | 2383 | 1019 | 456 | 314 | 1590 | 50 | 7780 | 445 | 76 | `91ae94a64` |
| 2026-09-10 | S104 T7: d17 + R28–R33 pass (4) + R27 remainder | 2565 | 2167 | **4732** | 2373 | 1011 | 456 | 314 | 1590 | 50 | 7780 | 445 | 76 | `13069c142` |
### The campaign — every batch, from the ledger (derived on every render)
@@ -331,7 +332,10 @@ counted, not marked). E, F and G belong to the canonical type layer and are the
| `s104_d14` | 2026-09-10 | E | 0 | 0 | 0 | 9 | 3 |
| `s104_d19` | 2026-09-10 | E | 0 | 0 | 0 | 3 | 3 |
| `s104_d16` | 2026-09-10 | E | 0 | 0 | 0 | 10 | 5 |
| **total** | | | **17,122** | **20,778** | **283** | **29,677** | **10,364** |
| `s104_d17` | 2026-09-10 | E | 0 | 0 | 0 | 8 | 4 |
| `s104_new5` | 2026-09-10 | E | 0 | 0 | 0 | 5 | 4 |
| `s104_r27` | 2026-09-10 | E | 0 | 0 | 0 | 10 | 3 |
| **total** | | | **17,122** | **20,778** | **283** | **29,700** | **10,375** |
*Generated by `tools/lever_progress.py --render` from `.run/P36/census/lever_census.json` and `.run/P36/delever/ledger.jsonl`; the series lives in `docs/lever-progress.tsv` (R75: published numbers are generated, never typed).*
+106 -1
View File
@@ -1863,7 +1863,112 @@ accumulate here as the phase produces them.**
marked ordinary-C fakes); R7's do-while now carries the marker. **Open for T9:** the tree's `LOAD-BEARING CONSTRUCTS` header
comments (232 files) still describe levers their banked bodies no longer have (e.g. `func_8017EF88`'s) — a stale-comment pass.
## 🛑 SESSION CHECKPOINT — S103 (2026-09-10, refreshed at the session's end): T0–T6 ☑, **T7 RUNNING**. 24,119 → **5,097 sites** this session (−19,022); 56 agent draws; generators **R22–R26**; `delever_regen` + `delever --port-scan`; **the MINIMUM-LEVER pivot** (four 130-copy classes now carry 1-2 marked levers instead of 4-34); R22 `check-all: 218 passed, 0 failed of 218` at every bank | `lever_census --check` OK, exit 0 (5,097 marked, 0 UNMARKED, 0 orphans) · the session's last commit follows
- **S104 — the second and third waves: d11–d19 ALL at 0 with ZERO levers; generators R28–R34; the new-families pass.** d11
`func_801800F0` (sign-split range tests → one ternary condition; cookbook §396(a); 4 bodies), d12 `func_801898E4` (the split
locals merged + `s16 b`; 4), d13 `func_8018F694` (`(s16)t >> 6` at the shift; 5), d14 `func_801860B8` (late locals reuse
earlier-dead variables; 3), d15 `func_8018594C` (a reused temp as direct stores + an `s16` parameter; 4), d16 `func_8017F368`
(arrays indexed by the loop counter, a `u8` copy; 5), d17 `func_80181DAC` (goto chain → `switch`, do-while → `for`:
`NOTE_INSN_LOOP_VTOP` flips `mostly_true_jump`, `reorg.c:1364-1372`; 4), d18 `func_8017BF50` (the invented second stepped
pointer deleted; 9), d19 `func_80189030` (loop indices renamed to the losing counter; 3). **Four of nineteen closes this session
were goto chains rewritten as structured C** (d3/d9/d11/d17) — no generator can reach that shape. **Generators R28
`merge_pinned_twins`, R29 `fold_store_temps`, R31 `shift_operand_casts`, R32 `compound_assignments`, R33
`else_arm_assignments`, R34 `merge_disjoint_locals`**, each run against its agent's own start text (R31/R32/R33 reproduce the
close at 0; R28 63 and R29 4 = the agents' measured single-move scores; R34 is a composition move: 13/5/63 alone). Their first
residue pass: `945 of 945 classes judged in 842 s — MATCH 4` (R32 ×2, R33, R28), banked 4/4. R27 pass: `995 of 995 classes judged
in 919 s — MATCH 25`, all banked. Sweep bank part 2: `39 of 44 MATCH row(s) banked, 35 sibling(s) propagated` (2 sibling
DIFFERS refused, 3 re-score misses). R22 after every batch: `check-all: 218 passed, 0 failed of 218` (r22_a/b/c logs). Census
4,928 → **4,732** (`0 UNMARKED — OK`, exit 0). Agents d20–d24 launched on the triple-judged residue (see the checkpoint).
## 🛑 SESSION CHECKPOINT — S104 (2026-09-10): T0–T6 ☑, **T7 RUNNING**. 5,097 → **4,732 sites** this session; 24 agent draws, **19 landed, ALL at 0** (18 with zero levers, d4 one marked do-while); generators **R27–R34**; the census counts kept ordinary-C fakes apart; R22 `check-all: 218 passed, 0 failed of 218` after every batch | `lever_census --check` exit 0 (4,732 marked, 0 UNMARKED, 0 orphans, 4 marked ordinary-C fakes)
### 0. How to use this block
A fresh session reads CLAUDE.md's load order, replays this block verbatim, confirms the effort (**S104 ran at `/effort high` on
Opus 5 1M; every agent on Opus**) and executes §2. **In flight when last refreshed:** agents d20 `func_80180324` (ov_SC04_007,
7 copies), d21 `func_8018179C` (ov_SC06_010), d22 `func_801861FC` (ov_SC03_091), d23 `func_80181864` (ov_SC03_113), d24
`func_8018003C` (ov_SC02_016) — read-only; each leaves `.run/P36/agents/<alias>__<fn>/body.c` + `mechanism.md` (+ copies under
`scratch/`). And the all-families sweep `s104_all` (detached, `setsid`; `.run/P36/regen/s104_all.jsonl` grows one line per
judged class; ~350 of 1,020 at the refresh; its MATCH rows are banked from the jsonl, see §3). First commands:
```
git log --oneline -1 && git status --short | grep -v '^??' | wc -l
ps -eo pid,etime,args | grep '[d]elever_regen' # is s104_all still running?
.venv/bin/python tools/delever_oracle.py --calibrate ov_SC04_011 ov_SC03_015 ov_SC03_014 main -j 16 # after EVERY commit
```
### 1. THE OPERATING PROCEDURE (Drew's; S104 additions in bold)
- At most FIVE agents at once (Drew, S103). **Free sweep BEFORE any agent touches a class (Drew, S104: "are we running sweeps
with the new tooling on all remaining funcs to see if we can reduce them further for free before an agent touches them?")** —
draw only classes that every current generator pass has judged and not closed (`s104_all` + `s104_r27` + `s104_new5`).
- Every landing: `--try` the body (and `grep -c '__asm__\|register\|FAKE\|volatile'` it) → launch the next agent → bank the
exemplar AND the agent's copies (`.run/P36/s104/bank_list.sh`, one line per body: `TU FN FILE LABEL MSG`; it calibrates,
`--apply-body --rung E`, `--propagate`, commits per bank, skips a no-op) → harvest (a generator with a known-true check on
the agent's own start text) → a regen pass of the new families → R22 → census (READ THE EXIT CODE, R97) → commit.
- **Resolve a copy's TU from `delever.named_definitions()` filtered by `/<alias>/`** — a grep for `^[a-z].*\bfn(` finds call
lines (one bank list stopped on it).
- Agents' brief: `PROMPT.md` + `METHOD_S103.md` (steps 8–14 are S104's; step 12–14 list every close with its `file:line`) +
the pack. Tell each agent what every pass already did and which same-name donors are NOT the same function.
### 2. NEXT
1. Land d20–d24 (§0). Bank each + copies; harvest mechanical moves into generators; re-run the new families.
2. When `s104_all` finishes: bank its remaining MATCH rows (build a TSV from the jsonl, skip rows already banked, mark R7
do-while lines — §3), then R22.
3. The residue at the refresh: **930 classes**; ~300 judged by all three passes and undrawn — keep five agents on them, largest
copies first, one per TU. Below 3 copies the classes are mostly singletons (912 at S104's open).
4. Open generator ideas, not built: **a goto-chain → structured-C rewriter** (d3/d9/d11/d17 — the biggest gap: every generator
mutates goto text); widen R22 `merge_walked_pointers` to STORES through a second stepped pointer (d18 found it did not
fire); `tools/localalloc_sim.py` three-quantity rule (d5's `scratch/lsim3.py`, both sorts); `alloc_table.py` final
registers (d12's `scratch/finalregs.py`) and local-alloc's handed-out call-saved registers (d7).
5. **Drew's rulings of S104 bind (decisions §S104):** do-while stays, marked; GTE is T5; unclosed sites stay marked and go to the
STRUCTS phase (the milestone amended); the signature-change functions go to the structs phase.
### 3. THE EXACT INVOCATIONS (S103's §3 still holds; additions)
```
# a regen pass (read-only; processes; one jsonl line per judged class as it lands)
setsid nohup nice -n 5 .venv/bin/python tools/delever_regen.py --families R28 R29 R31 R32 R33 R34 -j 8 --label <L> \
--exclude <every fn an agent holds> > .run/P36/regen/<L>.log 2>&1 < /dev/null & disown
.venv/bin/python tools/delever_regen.py --bank .run/P36/regen/<L>.tsv # the one writer; then R22
# banking MATCH rows from a still-running pass: build a TSV from <L>.jsonl (the S104 snippet: cols verdict alias fn tu copies
# score cls family desc start path tried err; skip (alias, fn) already banked; for family R7 append the do-while marker to the
# candidate's `while (0);` line — the pass generated before R7 learned the marker)
# R22 (≈90 s):
make clean && make extract-all JOBS=16 && make check-all JOBS=16
.venv/bin/python tools/delever_oracle.py --snapshot-baseline
.venv/bin/python tools/lever_census.py --check -j 16 --quiet; echo "exit=$?" # the EXIT CODE, never the last line
.venv/bin/python tools/lever_progress.py --snapshot "<what>"
```
### 4. WHAT S104 BUILT (SETUP rows under the delever_regen entry; kit corpus regenerated after the regen/census change)
- `delever_regen`: forked worker PROCESSES after warming `sites_by_body` / `real_signatures` / `named_definitions` (threads
made zero compiles in five minutes); `<label>.jsonl` written as each class lands; R27/R28 fed the REAL TU.
- `lever_census`: `walk_file` defaults to the tree's cross-file macro table (`tree_asm_macros()`) — S103's scrub false
positive fixed; a marker on a kept ordinary-C fake (`while (0)` / `!FAKE: do-while|dead-init`) is counted apart, never an
orphan (the census had exited 1 on d4's four markers — commit `830650946`'s "0 unmarked" was read from the last line; R97).
- Generators R27 (named port by relocation pairing), R28, R29, R31, R32, R33, R34 (§ the log); R7's do-while carries the marker.
- `.run/P36/s104/bank_list.sh` (the per-bank loop; scratch, untracked like `s103/`).
### 5. GOTCHAS S104 PAID FOR
- A regen on THREADS is GIL-bound: R18 emits 1,000+ texts per body and R19 builds a 29 s table once per thread.
- **R97, again:** a chain `census && next` stops on the census's exit 1 and the commit message still said OK — read `$?`.
- A per-line `mask_text` leaves a block comment's inner lines unmasked — the new generators mask the whole text.
- `--apply-body` refuses a dirty tree: one commit per bank (the script does it); the calibration must be at HEAD.
- Two git writers (a bank script and a tool commit) race on the index — commit tools only while no bank runs.
- `delever_pack --only` matches fn / TU / alias, not `alias__fn`.
- Banked bodies keep the tree's stale `LOAD-BEARING CONSTRUCTS` header comments (232 files mention the phrase) — T9.
### 6. OPEN BY NAME
- `func_80181D1C` (ov_SC04_004 ×4): d17 read it — two defects the `for`/`switch` move does not reach (an early `return 0` with
the reorg symptom and no loop; a return value kept in `v0` across a test while every spelling puts it in `v1`) — a separate
draw or the structs phase.
- The structs phase's list: `func_80157D20`, `func_8013CF68`, `func_80178970` (+ the four same-shape families), `func_8017FC5C`
+ `func_80180200`, `func_80185578`, `func_80168828`, `func_8013F350`'s head, the minimum-lever classes of S103; d10's union
proof (`func_8017EF88`) is the first evidence FOR Drew's struct hypothesis; d6 and d18 name struct types the phase can adopt.
- d14's side probe: `func_8012E364` (134 bodies at two marked pins) reaches 3 by local reuse (`ov_SC02_027__func_801860B8/scratch/e364/c0009.c`).
### 7. WHERE EVERYTHING IS
S103's §7 holds, plus `.run/P36/regen/s104_*` (all, r27, new5, part1/part2 TSVs, `s104_marked/` R7 candidates with markers) ·
`.run/P36/s104/` (R22 logs r22_a/b/c, bank lists banks_1–5, known-true harnesses kt.py/kt34.py, r27_probe.py) · each landed
pack's `mechanism.md` (d1–d19) · SETUP under the delever_regen entry.
## (superseded) SESSION CHECKPOINT — S103 (2026-09-10, refreshed at the session's end): T0–T6 ☑, **T7 RUNNING**. 24,119 → **5,097 sites** this session (−19,022); 56 agent draws; generators **R22–R26**; `delever_regen` + `delever --port-scan`; **the MINIMUM-LEVER pivot** (four 130-copy classes now carry 1-2 marked levers instead of 4-34); R22 `check-all: 218 passed, 0 failed of 218` at every bank | `lever_census --check` OK, exit 0 (5,097 marked, 0 UNMARKED, 0 orphans) · the session's last commit follows
### LATE S103 — READ THIS FIRST (it supersedes §0-§2 below where they differ)
- **Drew ended agent drawing at 89% context: "no more agents this session. let the current ones finish."** At that