feat(phase-29): func_80177940 (101 ins, reach-138) BANKED via the permuter loop — R22 140/140

- The loop: permuter (§31 schedule, 900s -j12) 5 -> 1, closing the 4-ins INSN_LUID scheduler tie the
  drafting agent had swept by hand and recorded as un-steerable; read the last instruction (andi vs
  addu); fixed it from the byte-verified sibling func_801778A8's pinned plain-copy idiom; permuter
  again from the corrected seed (cse profile, 1800s) -> MATCH.
- The diagnosis was byte-driven, not guessed: dropping the redundant & 0xf alone COLLAPSED the copy
  (100 vs 101 ins, 52 mismatched), proving the target needs a distinct PINNED register.
- GATE: harvest_verify --chunk 1 -> verified 1 / failed 0, d19c9580 BYTE-IDENTICAL; stub gone from
  source (checked by grep, not the report). R22 clean-fleet: check-all 140 passed, 0 failed of 140.
- NEGATIVE recorded: the pin does NOT transfer to func_8014D820 (pinning its temp t to $v1 -> 285
  mismatched, 303 vs 304 ins). Its run improved 33 -> 27 and plateaued; seed kept for ILS.

phase-ends/CURRENT_PHASE.md

@@ -2544,3 +2544,26 @@ conditional) · main-EXE/B9 + GLM/B6 + resident's 14 walls (P30) · behemoths B7
   on the 32-thread box silently killed each other the moment the first timed out, with no error anywhere.
   Scoped to the run's own scratch dir (which is in argv). This is what makes grinding several giants at
   once safe, and it is why the giant queue had only ever been run one-at-a-time.
+
+- **✅ 2026-07-24 (SESSION-17) — `func_80177940` (101 ins, reach-138) BANKED byte-identical in
+  ov_SC01_077. R22 clean-fleet 140/140. The permuter→diagnose→idiom→permuter loop closed a giant the
+  drafting agent had characterized as un-steerable.**
+  **The loop, in order:** (1) permuter, §31 `schedule` profile, 900 s @ -j12 → **5 → 1**, closing the
+  4-instruction INSN_LUID scheduler tie by itself. (2) Read the last instruction: `andi $a2,$v0,0xf` vs
+  target `addu $a2,$v0,$zero`. (3) Fixed it from a **byte-verified sibling** — `func_801778A8`'s
+  `nib = uVar1;` plain copy between two hard-pinned vars — NOT by guessing: dropping the redundant mask
+  alone collapsed the copy (100 vs 101 ins, 52 mismatched), which is what proved the target needs a
+  distinct pinned register rather than an unmasked value. (4) `register u32 n __asm__("$6")` + `n = nn;`
+  → 101/101, 6 left, retyped by `residual_class` as `ADDRESSING` → [permuter]/cse. (5) permuter again
+  from that structurally-correct seed, cse profile, 1800 s → **MATCH**. Its edit was two uses of one
+  temp (`new_var = a_` as a cse-opaque copy; `new_var = n * 8` splitting the expression) — the kind of
+  thing a hand sweep does not find and a search does.
+  **GATE (the sole arbiter, G3/P9):** `harvest_verify --chunk 1` → `verified 1 / failed 0`, final SHA
+  **`d19c9580…` BYTE-IDENTICAL**; stub confirmed GONE from source by `grep INCLUDE_ASM`, never the
+  report (§55b trap 4). **R22 `make clean && extract-all && check-all` → 140 passed, 0 failed of 140.**
+  **⚠️ NEGATIVE, recorded so it is not re-bought:** the same pin idiom does NOT transfer to
+  `func_8014D820`. Its residual is the mirror image (target holds the `lhu` results in `$v1` and keeps
+  `$a0` live to fill the load-delay slot), but pinning its reusable temp `t` to `$3` made it far worse
+  — **303 vs 304 ins, 285 mismatched** (`$v1` is needed elsewhere). §44's "each giant is its own class"
+  holds: the *loop* transfers, the *specific pin* does not. Its permuter run improved **33 → 27** in
+  1800 s @ -j8 and plateaued; the 27-seed is kept at `.run/perm_s17c/best27.c` for an ILS warm restart.

src/ov_SC01_077/ov_SC01_077_jr_801734BC.c

@@ -3122,7 +3122,89 @@ INCLUDE_ASM("asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_801734BC", func_801777B
 
 INCLUDE_ASM("asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_801734BC", func_801778A8);
 
-INCLUDE_ASM("asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_801734BC", func_80177940);
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+extern s32 func_80029504(void);
+void func_80177940(u32 *p, u32 a_, u32 b_, u32 c_)
+{
+  int new_var;
+register u32 a __asm__("$18");
+register u32 b __asm__("$16");
+register u32 c __asm__("$17");
+register u32 v __asm__("$2");
+  u32 *q;
+  u32 *r;
+  u32 flag;
+register u32 n __asm__("$6");
+  u32 nn;
+  u32 t;
+  u32 cl;
+  u32 cs;
+  u32 col;
+  s16 i;
+  new_var = a_;
+  b = b_;
+  c = c_;
+  a = new_var;
+  v = (u32) func_80029504();
+  v = v - 10;
+  v = v < 0x4b0;
+  v = -v;
+  v = v & 0xb4;
+  c++;
+  c--;
+  cs = c << 16;
+  p[0] = (((u32) (p - 5)) & 0xffffff) | 0x3000000;
+  p[2] = cs | ((b + 0xf) & 0xffff);
+  p[1] = 0x74808080;
+  p[3] = (((v << 6) | 0x4016) << 16) | 0x3850;
+  p += 5;
+  q = p;
+__asm__("" : "=r"(v) : "0"(v));
+  cl = ((v << 6) | 0x4016) << 16;
+  flag = 0x1000000;
+  for (i = 0; i < 4; i++)
+  {
+    nn = (a << 16) >> 28;
+    n = nn;
+    if (((nn != 0) || (i == 3)) || (i == 1))
+    {
+      flag = 0;
+    }
+    q[0] = (((u32) (q - 5)) & 0xffffff) | 0x3000000;
+    q[2] = (cs | (b & 0xffff)) | flag;
+    col = 0x74808080;
+    new_var = n * 8;
+    q[1] = col;
+    t = (new_var + 8) | 0x4000;
+    q[3] = cl | t;
+    q += 5;
+    b += 8;
+    a <<= 4;
+    col = 0;
+  }
+
+  p = q;
+  r = p;
+__asm__("" : "=r"(r) : "0"(r));
+  *((u16 *) (r - 8)) += 6;
+  *((u16 *) (r - 3)) += 6;
+}
+
 
 DEFINE_func_80177AD4()  /* dedup: shared engine-core @0x80177AD4 (src/shared) */