mirror of
https://github.com/ran-j/PS2Recomp.git
synced 2026-09-26 08:51:05 -04:00
feat: more instruction
This commit is contained in:
Ran-j
@@ -281,7 +281,7 @@ namespace ps2recomp
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MMI3_PCPYH = 0x1B,
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MMI3_PEXCW = 0x1E,
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MMI3_PMTHI = 0x08, // Move To HI register
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MMI3_PMTLO = 0x09 // Move To LO register
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MMI3_PMTLO = 0x09 // Move To LO register
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};
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// COP0 (rs field)
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@@ -342,8 +342,8 @@ namespace ps2recomp
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COP1_W = 0x14, // Word (integer) Operation
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COP1_BC_BCF = 0x00,
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COP1_BC_BCT = 0x01,
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COP1_L = 0x15, // Long (64-bit integer) Operation
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COP1_D = 0x11, // Double Precision Operation (unused on PS2 FPU?)
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COP1_L = 0x15, // Long (64-bit integer) Operation
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COP1_D = 0x11, // Double Precision Operation (unused on PS2 FPU?)
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};
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enum Cop1Functions
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@@ -386,7 +386,6 @@ namespace ps2recomp
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COP1_FUNC_C_LE = 0x3E, // Signaling Less Than or Equal
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COP1_FUNC_C_NGT = 0x3F, // Not Greater Than (Unordered or Less Than or Equal)
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};
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// COP2 (VU0 macro) function codes
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enum Cop2Functions
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@@ -435,7 +434,8 @@ namespace ps2recomp
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VU0_VISWR = 0x16,
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VU0_VCALLMS = 0x20,
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VU0_VCALLMSR = 0x21,
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VU0_VRGET = 0x3F // Get VU0 R register
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VU0_VRGET = 0x3F, // Get VU0 R register
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VU0_VSUB_XYZ = 0x38 // Subtract with component selection
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};
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enum VU0SpecialFormats
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@@ -459,13 +459,39 @@ namespace ps2recomp
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enum VU0OPSFunctions
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{
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VU0OPS_QMFC2_NI = 0x00, // Non-incrementing QMFC2
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VU0OPS_QMFC2_I = 0x01, // Incrementing QMFC2
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VU0OPS_QMTC2_NI = 0x02, // Non-incrementing QMTC2
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VU0OPS_QMTC2_I = 0x03, // Incrementing QMTC2
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VU0OPS_VMFIR = 0x04, // Move From Integer Register
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VU0OPS_VXITOP = 0x08, // Execute Interrupt on VU0
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VU0OPS_VWAITQ = 0x3C // Wait for Q register operations to complete
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VU0OPS_QMFC2_NI = 0x00, // Non-incrementing QMFC2
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VU0OPS_QMFC2_I = 0x01, // Incrementing QMFC2
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VU0OPS_QMTC2_NI = 0x02, // Non-incrementing QMTC2
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VU0OPS_QMTC2_I = 0x03, // Incrementing QMTC2
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VU0OPS_VMFIR = 0x04, // Move From Integer Register
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VU0OPS_VXITOP = 0x08, // Execute Interrupt on VU0
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VU0OPS_VWAITQ = 0x3B, // Wait for Q register operations to complete
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VU0OPS_VMFHL = 0x1C, // Move from High / Low(similar to PMFHL)
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VU0OPS_VMTIR = 0x3C // Move to VU0 I Register with function code
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};
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enum VU0OPSFunctionsExtra
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{
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VU0_VCALLMS_DIRECT = 0x00,
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VU0_VCALLMS_REG = 0x01
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};
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enum VU0SpecialMasks
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{
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VU0_FIELD_MASK = 0xF, // Mask for vector field selection
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VU0_FIELD_SHIFT = 21, // Shift amount for field selection
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VU0_STORE_BIT = 0x80, // Bit indicating store operation
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VU0_SUBOP_MASK = 0x1F, // Mask for sub-operation code
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VU0_SUBOP_SHIFT = 6, // Shift amount for sub-operation
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VU0_SQC0 = 0x8 // SQC0 instruction code
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};
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enum VU0FormatsExtra
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{
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VU0_FMT_MACRO_MOVE = 0x1, // Move between VU registers format
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VU0_FMT_VIF_STATUS = 0x5, // VIF status operations
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VU0_FMT_VCALLMS = 0x14, // VU0 microprogram call format
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VU0_FMT_LQSQ_COP0 = 0x1B // Load/store quad VU0 format
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};
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// PMFHL functions (sa field)
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@@ -586,18 +586,18 @@ namespace ps2recomp
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inst.rt, inst.rs, (int16_t)inst.immediate);
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// Special case for R5900
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case OPCODE_COP0:
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return translateCOP0Instruction(inst);
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case OPCODE_COP1:
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return translateFPUInstruction(inst);
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case OPCODE_CACHE:
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return "// CACHE instruction (ignored)";
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case OPCODE_PREF:
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return "// PREF instruction (ignored)";
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case OPCODE_COP1:
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return translateFPUInstruction(inst);
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case OPCODE_COP0:
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return translateCOP0Instruction(inst);
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// REGIMM special format (opcode=0x01)
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case OPCODE_REGIMM:
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switch (inst.rt)
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@@ -616,8 +616,7 @@ namespace ps2recomp
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}
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case REGIMM_MTSAB:
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return fmt::format("ctx->sa = (ctx->r[{}] + 0x{:X}) & 0x0F;",
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inst.rs, inst.immediate);
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return fmt::format("ctx->sa = (ADD32(ctx->r[{}], (int32_t)(int16_t)0x{:X})) & 0x0F;", inst.rs, inst.immediate);
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case REGIMM_MTSAH:
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return fmt::format("ctx->sa = ((ctx->r[{}] + 0x{:X}) & 0x07) << 1;",
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@@ -1037,7 +1036,7 @@ namespace ps2recomp
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return fmt::format("ctx->cop0_errorepc = ctx->r[{}];", rt);
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default:
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return fmt::format("// MTC0 to register {} ignored", rd);
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return fmt::format("// Unimplemented MTC0 to COP0 {}", rd);
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}
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case COP0_CO: // COP0 co-processor operations
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@@ -1047,24 +1046,16 @@ namespace ps2recomp
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switch (function)
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{
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case COP0_CO_TLBR:
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return fmt::format("// TLBR instruction - TLB Read\n"
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" // Reads TLB entry specified by Index register\n"
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" // Not fully implemented in recompiled code");
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return fmt::format("runtime->handleTLBR(rdram, ctx);");
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case COP0_CO_TLBWI:
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return fmt::format("// TLBWI instruction - TLB Write Indexed\n"
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" // Writes TLB entry specified by Index register\n"
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" // Not fully implemented in recompiled code");
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return fmt::format("runtime->handleTLBWI(rdram, ctx);");
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case COP0_CO_TLBWR:
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return fmt::format("// TLBWR instruction - TLB Write Random\n"
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" // Writes TLB entry specified by Random register\n"
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" // Not fully implemented in recompiled code");
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return fmt::format("runtime->handleTLBWR(rdram, ctx);");
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case COP0_CO_TLBP:
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return fmt::format("// TLBP instruction - TLB Probe\n"
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" // Searches TLB for matching entry to EntryHi, sets Index\n"
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" // Not fully implemented in recompiled code");
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return fmt::format("runtime->handleTLBP(rdram, ctx);");
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case COP0_CO_ERET:
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return fmt::format("// ERET instruction - Return from Exception\n"
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@@ -1543,6 +1534,138 @@ namespace ps2recomp
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case COP2_BC2:
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return fmt::format("// VU branch instruction not implemented");
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case VU0_FMT_LQSQ_COP0:
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if (inst.function & VU0_SQC0) // Store operation
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{
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return fmt::format("WRITE128(ADD32(ctx->r[{}], 0x{:X}), (__m128i)ctx->vu0_vf[{}]);",
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inst.rs, (int16_t)inst.immediate, inst.rt);
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}
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else // Load operation
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{
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return fmt::format("ctx->vu0_vf[{}] = (__m128)READ128(ADD32(ctx->r[{}], 0x{:X}));",
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inst.rt, inst.rs, (int16_t)inst.immediate);
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}
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case VU0_FMT_VIF_STATUS:
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{
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int field = (inst.function >> VU0_FIELD_SHIFT) & VU0_FIELD_MASK; // Field selector
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int dest = inst.rd; // Destination register
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if (inst.function & VU0_STORE_BIT) // Store to status
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{
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return fmt::format("ctx->vu0_status &= ~(0xFF << {}); ctx->vu0_status |= (_mm_extract_epi32(ctx->vu0_vf[{}], 0) & 0xFF) << {};",
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field * 8, dest, field * 8);
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}
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else // Load from status
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{
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return fmt::format("ctx->vu0_vf[{}] = (__m128)_mm_set1_epi32((ctx->vu0_status >> {}) & 0xFF);",
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dest, field * 8);
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}
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}
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case VU0_FMT_MACRO_MOVE:
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{
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uint32_t subop = (inst.function >> VU0_SUBOP_SHIFT) & VU0_SUBOP_MASK;
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switch (subop)
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{
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case VU0OPS_QMFC2_NI: // VMOVE - Move between VF registers
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return fmt::format("ctx->vu0_vf[{}] = ctx->vu0_vf[{}];",
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inst.rd, inst.rs);
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case VU0OPS_QMFC2_I: // VRNEXT - Get next random value
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return fmt::format("{{ uint32_t random_val = (ctx->vu0_status * 0x41C64E6D + 12345) & 0xFFFFFFFF;\n"
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" ctx->vu0_status = random_val;\n"
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" ctx->vu0_vf[{}] = (__m128)_mm_set1_epi32(random_val); }}",
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inst.rd);
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case VU0OPS_QMTC2_NI: // VRGET - Get random state
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return fmt::format("ctx->vu0_vf[{}] = (__m128)_mm_set1_epi32(ctx->vu0_status);",
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inst.rd);
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default:
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return fmt::format("// Unhandled VU0 format 0x1 subop: 0x{:X}", subop);
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}
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}
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case VU0_FMT_VCALLMS:
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{
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uint32_t subop = inst.function & 0x3F;
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switch (subop)
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{
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case VU0_VCALLMS_DIRECT: // VCALLMS - Call VU0 microprogram
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return fmt::format("{{ uint32_t mpg_addr = 0x{:X};\n"
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" ctx->vu0_cmsar0 = mpg_addr;\n"
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" ctx->vu0_status |= 0x1; // Set execution bit }}",
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inst.immediate * 8);
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case VU0_VCALLMS_REG: // VCALLMSR - Call VU0 microprogram (register)
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return fmt::format("{{ uint32_t mpg_addr = ctx->r[{}].m128i_u32[0] & 0xFFF;\n"
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" ctx->vu0_cmsar0 = mpg_addr;\n"
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" ctx->vu0_status |= 0x1; // Set execution bit }}",
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inst.rs);
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default:
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return fmt::format("// Unhandled VU0 format 0x14 subop: 0x{:X}", subop);
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}
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}
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case VU0_VSUB_XYZ:
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{
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int destMask = (inst.function >> 21) & 0xF;
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return fmt::format("{{ __m128 result = PS2_VSUB(ctx->vu0_vf[{}], ctx->vu0_vf[{}]);\n"
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" __m128 destMask = _mm_set_ps(\n"
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" {}f, {}f, {}f, {}f);\n"
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" // Blend the result with the destination register based on mask\n"
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" ctx->vu0_vf[{}] = _mm_blendv_ps(ctx->vu0_vf[{}], result, destMask); }}",
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inst.rs, inst.rt,
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(destMask & 0x8) ? 0xFFFFFFFF : 0,
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(destMask & 0x4) ? 0xFFFFFFFF : 0,
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(destMask & 0x2) ? 0xFFFFFFFF : 0,
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(destMask & 0x1) ? 0xFFFFFFFF : 0,
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inst.rd, inst.rd);
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}
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case VU0OPS_VMFHL: // 0x1C - Move from High/Low (similar to PMFHL)
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{
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int subop = (inst.function >> 16) & 0x1F;
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switch (subop)
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{
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case 0: // LW variant - Extracts low word from accumulator
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return fmt::format("{{ \n"
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" float w = _mm_cvtss_f32(_mm_castsi128_ps(_mm_cvtsi32_si128(ctx->lo)));\n"
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" float z = 0.0f;\n"
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" float y = 0.0f;\n"
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" float x = 0.0f;\n"
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" ctx->vu0_vf[{}] = _mm_set_ps(w, z, y, x); }}",
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inst.rd);
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case 1: // UW variant - Extracts upper word from accumulator
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return fmt::format("{{ \n"
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" float w = _mm_cvtss_f32(_mm_castsi128_ps(_mm_cvtsi32_si128(ctx->hi)));\n"
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" float z = 0.0f;\n"
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" float y = 0.0f;\n"
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" float x = 0.0f;\n"
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" ctx->vu0_vf[{}] = _mm_set_ps(w, z, y, x); }}",
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inst.rd);
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case 2: // SLW variant - Saturated conversion of accumulator
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return fmt::format("{{ \n"
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" int64_t acc = ((int64_t)ctx->hi << 32) | ctx->lo;\n"
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" float result = (float)acc;\n"
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" // Clamp to prevent overflow\n"
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" if (result > FLT_MAX) result = FLT_MAX;\n"
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" if (result < -FLT_MAX) result = -FLT_MAX;\n"
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" ctx->vu0_vf[{}] = _mm_set_ps(result, 0.0f, 0.0f, 0.0f); }}",
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inst.rd);
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default:
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return fmt::format("// Unhandled VU0OPS_VMFHL suboperation: 0x{:X}", subop);
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}
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}
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case COP2_BC2F:
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switch (inst.rt)
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{
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@@ -1577,9 +1700,6 @@ namespace ps2recomp
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case COP2_MTVUCF:
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return fmt::format("ctx->vu0_cf[{}] = ctx->r[{}];", inst.rd, inst.rt);
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case COP2_VMTIR:
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return fmt::format("ctx->vu0_i = (float)ctx->r[{}].m128_i32[0];", inst.rt);
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case COP2_VCLIP: // VU0 Clipping operation (0x1E)
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return fmt::format("{{ float x = ctx->vu0_vf[{}].m128_f32[0]; "
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"float y = ctx->vu0_vf[{}].m128_f32[1]; "
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@@ -1753,6 +1873,9 @@ namespace ps2recomp
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return fmt::format("// VWAITQ - Wait for Q register operations to complete\n"
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" // need proper implementation for this\n");
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case VU0OPS_VMTIR:
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return fmt::format("ctx->vu0_i = (float)ctx->r[{}].m128_i32[0];", inst.rt);
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default:
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return fmt::format("// Unhandled VU0OPS function: 0x{:X}", inst.function);
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}
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