mirror of
https://github.com/open-goal/jak-project
synced 2026-06-08 04:17:28 -04:00
goalc/arm: another couple dozen instructions
This commit is contained in:
Tyler Wilding
+21
-21
@@ -718,87 +718,87 @@ Instruction sar_gpr64_u8(const ObjectGenerator& gen, Register reg, uint8_t sa) {
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}
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Instruction jmp_32(const ObjectGenerator& gen) {
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IGEN_DISPATCH(jmp_32);
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IGEN_DISPATCH(jmp_imm);
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}
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Instruction je_32(const ObjectGenerator& gen) {
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IGEN_DISPATCH(je_32);
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IGEN_DISPATCH(je_imm);
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}
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Instruction jne_32(const ObjectGenerator& gen) {
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IGEN_DISPATCH(jne_32);
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IGEN_DISPATCH(jne_imm);
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}
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Instruction jle_32(const ObjectGenerator& gen) {
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IGEN_DISPATCH(jle_32);
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IGEN_DISPATCH(jle_imm);
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}
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Instruction jge_32(const ObjectGenerator& gen) {
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IGEN_DISPATCH(jge_32);
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IGEN_DISPATCH(jge_imm);
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}
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Instruction jl_32(const ObjectGenerator& gen) {
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IGEN_DISPATCH(jl_32);
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IGEN_DISPATCH(jl_imm);
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}
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Instruction jg_32(const ObjectGenerator& gen) {
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IGEN_DISPATCH(jg_32);
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IGEN_DISPATCH(jg_imm);
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}
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Instruction jbe_32(const ObjectGenerator& gen) {
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IGEN_DISPATCH(jbe_32);
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IGEN_DISPATCH(jbe_imm);
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}
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Instruction jae_32(const ObjectGenerator& gen) {
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IGEN_DISPATCH(jae_32);
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IGEN_DISPATCH(jae_imm);
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}
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Instruction jb_32(const ObjectGenerator& gen) {
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IGEN_DISPATCH(jb_32);
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IGEN_DISPATCH(jb_imm);
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}
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Instruction ja_32(const ObjectGenerator& gen) {
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IGEN_DISPATCH(ja_32);
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IGEN_DISPATCH(ja_imm);
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}
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Instruction cmp_flt_flt(const ObjectGenerator& gen, Register a, Register b) {
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IGEN_DISPATCH(cmp_flt_flt, a, b);
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IGEN_DISPATCH(cmp_f32_f32, a, b);
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}
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Instruction sqrts_xmm(const ObjectGenerator& gen, Register dst, Register src) {
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IGEN_DISPATCH(sqrts_xmm, dst, src);
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IGEN_DISPATCH(sqrt_f32, dst, src);
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}
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Instruction mulss_xmm_xmm(const ObjectGenerator& gen, Register dst, Register src) {
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IGEN_DISPATCH(mulss_xmm_xmm, dst, src);
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IGEN_DISPATCH(mul_f32_f32, dst, src);
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}
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Instruction divss_xmm_xmm(const ObjectGenerator& gen, Register dst, Register src) {
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IGEN_DISPATCH(divss_xmm_xmm, dst, src);
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IGEN_DISPATCH(div_f32_f32, dst, src);
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}
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Instruction subss_xmm_xmm(const ObjectGenerator& gen, Register dst, Register src) {
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IGEN_DISPATCH(subss_xmm_xmm, dst, src);
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IGEN_DISPATCH(sub_f32_f32, dst, src);
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}
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Instruction addss_xmm_xmm(const ObjectGenerator& gen, Register dst, Register src) {
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IGEN_DISPATCH(addss_xmm_xmm, dst, src);
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IGEN_DISPATCH(add_f32_f32, dst, src);
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}
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Instruction minss_xmm_xmm(const ObjectGenerator& gen, Register dst, Register src) {
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IGEN_DISPATCH(minss_xmm_xmm, dst, src);
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IGEN_DISPATCH(min_f32_f32, dst, src);
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}
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Instruction maxss_xmm_xmm(const ObjectGenerator& gen, Register dst, Register src) {
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IGEN_DISPATCH(maxss_xmm_xmm, dst, src);
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IGEN_DISPATCH(max_f32_f32, dst, src);
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}
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Instruction int32_to_float(const ObjectGenerator& gen, Register dst, Register src) {
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IGEN_DISPATCH(int32_to_float, dst, src);
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IGEN_DISPATCH(int32_to_f32, dst, src);
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}
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Instruction float_to_int32(const ObjectGenerator& gen, Register dst, Register src) {
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IGEN_DISPATCH(float_to_int32, dst, src);
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IGEN_DISPATCH(f32_to_int32, dst, src);
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}
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Instruction nop(const ObjectGenerator& gen) {
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+138
-63
@@ -849,114 +849,189 @@ InstructionARM64 sar_gpr64_u8(Register reg, uint8_t sa) {
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//;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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// CONTROL FLOW
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//;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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//
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// All of these instructions jump to a target that is zero
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// and then its up to the IR to patch the actual target
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//
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// Critically, on arm these relative targets must be within
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// 128MB, which is much less than x86 (~2GB)
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//
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// However, these functions are only really used for jumps within
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// a given function...of which the largest we've seen isn't even in the MB
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// of sizes
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//
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// So for now, keep it simple and don't implement something more
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// complicated like veneers, this should be fine.
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InstructionARM64 jmp_32() {
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ASSERT_MSG(false, "not yet implemented");
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return InstructionARM64(0b0);
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InstructionARM64 jmp_imm() {
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// https://www.scs.stanford.edu/~zyedidia/arm64/b_uncond.html
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// B <label>
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return InstructionARM64(Base(0b000101, 6), Imm26(0));
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}
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InstructionARM64 je_32() {
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ASSERT_MSG(false, "not yet implemented");
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return InstructionARM64(0b0);
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// Now these instructions in ARM are even more limiting, conditional
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// branches must be within 1MB relative to the instruction
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//
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// However once again, that is still WAY below our biggest functions of a few kb
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//
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// But still...be aware! There should be some assertions in place in the patching so that
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// said issues don't just fly under the radar
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//
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// Also, these instructions may have to be patched slightly differently since
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// ARM uses a single branch instruction for all
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//
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// It's worth noting that these x86 instructions also have limitations, they cannot
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// jump to far labels (labels in other code segments). But that's more difficult to
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// give a numeric value to like with ARM.
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InstructionARM64 je_imm() {
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// https://www.scs.stanford.edu/~zyedidia/arm64/b_cond.html
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// B.<cond> <label>
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// 0000 EQ
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return InstructionARM64(Base(0b01010100, 8), Imm19(0), Cond(0b0000));
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}
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InstructionARM64 jne_32() {
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ASSERT_MSG(false, "not yet implemented");
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return InstructionARM64(0b0);
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InstructionARM64 jne_imm() {
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// https://www.scs.stanford.edu/~zyedidia/arm64/b_cond.html
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// B.<cond> <label>
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// 0001 NE
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return InstructionARM64(Base(0b01010100, 8), Imm19(0), Cond(0b0001));
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}
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InstructionARM64 jle_32() {
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ASSERT_MSG(false, "not yet implemented");
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return InstructionARM64(0b0);
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InstructionARM64 jle_imm() {
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// https://www.scs.stanford.edu/~zyedidia/arm64/b_cond.html
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// B.<cond> <label>
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// 1101 LE
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return InstructionARM64(Base(0b01010100, 8), Imm19(0), Cond(0b1101));
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}
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InstructionARM64 jge_32() {
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ASSERT_MSG(false, "not yet implemented");
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return InstructionARM64(0b0);
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InstructionARM64 jge_imm() {
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// https://www.scs.stanford.edu/~zyedidia/arm64/b_cond.html
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// B.<cond> <label>
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// 1010 GE
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return InstructionARM64(Base(0b01010100, 8), Imm19(0), Cond(0b1010));
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}
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InstructionARM64 jl_32() {
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ASSERT_MSG(false, "not yet implemented");
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return InstructionARM64(0b0);
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InstructionARM64 jl_imm() {
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// https://www.scs.stanford.edu/~zyedidia/arm64/b_cond.html
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// B.<cond> <label>
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// 1011 LT
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return InstructionARM64(Base(0b01010100, 8), Imm19(0), Cond(0b1011));
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}
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InstructionARM64 jg_32() {
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ASSERT_MSG(false, "not yet implemented");
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return InstructionARM64(0b0);
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InstructionARM64 jg_imm() {
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// https://www.scs.stanford.edu/~zyedidia/arm64/b_cond.html
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// B.<cond> <label>
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// 1100 GT
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return InstructionARM64(Base(0b01010100, 8), Imm19(0), Cond(0b1100));
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}
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InstructionARM64 jbe_32() {
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ASSERT_MSG(false, "not yet implemented");
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return InstructionARM64(0b0);
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InstructionARM64 jbe_imm() {
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// https://www.scs.stanford.edu/~zyedidia/arm64/b_cond.html
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// B.<cond> <label>
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// 1001 LS
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return InstructionARM64(Base(0b01010100, 8), Imm19(0), Cond(0b1001));
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}
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InstructionARM64 jae_32() {
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ASSERT_MSG(false, "not yet implemented");
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return InstructionARM64(0b0);
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InstructionARM64 jae_imm() {
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// https://www.scs.stanford.edu/~zyedidia/arm64/b_cond.html
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// B.<cond> <label>
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// 0010 CS
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return InstructionARM64(Base(0b01010100, 8), Imm19(0), Cond(0b0010));
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}
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InstructionARM64 jb_32() {
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ASSERT_MSG(false, "not yet implemented");
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return InstructionARM64(0b0);
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InstructionARM64 jb_imm() {
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// https://www.scs.stanford.edu/~zyedidia/arm64/b_cond.html
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// B.<cond> <label>
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// 0011 CC
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return InstructionARM64(Base(0b01010100, 8), Imm19(0), Cond(0b0011));
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}
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InstructionARM64 ja_32() {
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ASSERT_MSG(false, "not yet implemented");
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return InstructionARM64(0b0);
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InstructionARM64 ja_imm() {
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// https://www.scs.stanford.edu/~zyedidia/arm64/b_cond.html
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// B.<cond> <label>
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// 1000 HI
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return InstructionARM64(Base(0b01010100, 8), Imm19(0), Cond(0b1000));
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}
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//;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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// FLOAT MATH
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//;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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InstructionARM64 cmp_flt_flt(Register a, Register b) {
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ASSERT_MSG(false, "not yet implemented");
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return InstructionARM64(0b0);
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InstructionARM64 cmp_f32_f32(Register a, Register b) {
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// https://www.scs.stanford.edu/~zyedidia/arm64/fcmp_float.html
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// Single-precision (ftype == 00 && opc == 00)
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// FCMP <Sn>, <Sm>
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return InstructionARM64(Base(0b00011110001000000010000000000000, 32), Rn(a.id()), Rm(b.id()));
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}
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InstructionARM64 sqrts_xmm(Register dst, Register src) {
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ASSERT_MSG(false, "not yet implemented");
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return InstructionARM64(0b0);
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InstructionARM64 sqrt_f32(Register dst, Register src) {
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// https://www.scs.stanford.edu/~zyedidia/arm64/fsqrt_float.html
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// Single-precision (ftype == 00)
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// FSQRT <Sd>, <Sn>
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return InstructionARM64(Base(0b0001111000100001110000, 22), Rn(src.id()), Rm(dst.id()));
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}
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InstructionARM64 mulss_xmm_xmm(Register dst, Register src) {
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ASSERT_MSG(false, "not yet implemented");
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return InstructionARM64(0b0);
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InstructionARM64 mul_f32_f32(Register dst, Register src) {
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// https://www.scs.stanford.edu/~zyedidia/arm64/fmul_float.html
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// Single-precision (ftype == 00)
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// FMUL <Sd>, <Sn>, <Sm>
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return InstructionARM64(Base(0b0001111000100000000010, 22), Rd(dst.id()), Rn(dst.id()),
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Rm(src.id()));
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}
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InstructionARM64 divss_xmm_xmm(Register dst, Register src) {
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ASSERT_MSG(false, "not yet implemented");
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return InstructionARM64(0b0);
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InstructionARM64 div_f32_f32(Register dst, Register src) {
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// https://www.scs.stanford.edu/~zyedidia/arm64/fdiv_float.html
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// Single-precision (ftype == 00)
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// FDIV <Sd>, <Sn>, <Sm>
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return InstructionARM64(Base(0b0001111000100000000110, 22), Rd(dst.id()), Rn(dst.id()),
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Rm(src.id()));
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}
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InstructionARM64 subss_xmm_xmm(Register dst, Register src) {
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ASSERT_MSG(false, "not yet implemented");
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return InstructionARM64(0b0);
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InstructionARM64 sub_f32_f32(Register dst, Register src) {
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// https://www.scs.stanford.edu/~zyedidia/arm64/fsub_float.html
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// Single-precision (ftype == 00)
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// FSUB <Sd>, <Sn>, <Sm>
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return InstructionARM64(Base(0b0001111000100000001110, 22), Rd(dst.id()), Rn(dst.id()),
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Rm(src.id()));
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}
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InstructionARM64 addss_xmm_xmm(Register dst, Register src) {
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ASSERT_MSG(false, "not yet implemented");
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return InstructionARM64(0b0);
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InstructionARM64 add_f32_f32(Register dst, Register src) {
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// https://www.scs.stanford.edu/~zyedidia/arm64/fadd_float.html
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// Single-precision (ftype == 00)
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// FADD <Sd>, <Sn>, <Sm>
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return InstructionARM64(Base(0b0001111000100000001010, 22), Rd(dst.id()), Rn(dst.id()),
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Rm(src.id()));
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}
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InstructionARM64 minss_xmm_xmm(Register dst, Register src) {
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ASSERT_MSG(false, "not yet implemented");
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return InstructionARM64(0b0);
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InstructionARM64 min_f32_f32(Register dst, Register src) {
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// https://www.scs.stanford.edu/~zyedidia/arm64/fmin_float.html
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// Single-precision (ftype == 00)
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// FMIN <Sd>, <Sn>, <Sm>
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return InstructionARM64(Base(0b0001111000100000010110, 22), Rd(dst.id()), Rn(dst.id()),
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Rm(src.id()));
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}
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InstructionARM64 maxss_xmm_xmm(Register dst, Register src) {
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ASSERT_MSG(false, "not yet implemented");
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return InstructionARM64(0b0);
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InstructionARM64 max_f32_f32(Register dst, Register src) {
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// https://www.scs.stanford.edu/~zyedidia/arm64/fmax_float.html
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// Single-precision (ftype == 00)
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// FMAX <Sd>, <Sn>, <Sm>
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return InstructionARM64(Base(0b0001111000100000010010, 22), Rd(dst.id()), Rn(dst.id()),
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Rm(src.id()));
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}
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InstructionARM64 int32_to_float(Register dst, Register src) {
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ASSERT_MSG(false, "not yet implemented");
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return InstructionARM64(0b0);
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InstructionARM64 int32_to_f32(Register dst, Register src) {
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// https://www.scs.stanford.edu/~zyedidia/arm64/scvtf_float_int.html
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// 32-bit to single-precision (sf == 0 && ftype == 00)
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// SCVTF <Sd>, <Wn>
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return InstructionARM64(Base(0b0001111000100010000000, 22), Rd(dst.id()), Rn(dst.id()));
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}
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InstructionARM64 float_to_int32(Register dst, Register src) {
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ASSERT_MSG(false, "not yet implemented");
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return InstructionARM64(0b0);
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InstructionARM64 f32_to_int32(Register dst, Register src) {
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// https://www.scs.stanford.edu/~zyedidia/arm64/fcvtzs_float_int.html
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// 32-bit to single-precision (sf == 0 && ftype == 00)
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// FCVTZS <Wd>, <Sn>
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return InstructionARM64(Base(0b0001111000111000000000, 22), Rd(dst.id()), Rn(dst.id()));
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}
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InstructionARM64 nop() {
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+21
-21
@@ -515,57 +515,57 @@ InstructionARM64 sar_gpr64_u8(Register reg, uint8_t sa);
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/*!
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* Jump, 32-bit constant offset. The offset is by default 0 and must be patched later.
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*/
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InstructionARM64 jmp_32();
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InstructionARM64 jmp_imm();
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/*!
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* Jump if equal.
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*/
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InstructionARM64 je_32();
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InstructionARM64 je_imm();
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/*!
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* Jump not equal.
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*/
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InstructionARM64 jne_32();
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InstructionARM64 jne_imm();
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/*!
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* Jump less than or equal.
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*/
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InstructionARM64 jle_32();
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InstructionARM64 jle_imm();
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/*!
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* Jump greater than or equal.
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*/
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InstructionARM64 jge_32();
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InstructionARM64 jge_imm();
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/*!
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* Jump less than
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*/
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InstructionARM64 jl_32();
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InstructionARM64 jl_imm();
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/*!
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* Jump greater than
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*/
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InstructionARM64 jg_32();
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InstructionARM64 jg_imm();
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/*!
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* Jump below or equal
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*/
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InstructionARM64 jbe_32();
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InstructionARM64 jbe_imm();
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/*!
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* Jump above or equal
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*/
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InstructionARM64 jae_32();
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InstructionARM64 jae_imm();
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/*!
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* Jump below
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*/
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InstructionARM64 jb_32();
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InstructionARM64 jb_imm();
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/*!
|
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* Jump above
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*/
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InstructionARM64 ja_32();
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InstructionARM64 ja_imm();
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//;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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// FLOAT MATH
|
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@@ -574,49 +574,49 @@ InstructionARM64 ja_32();
|
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/*!
|
||||
* Compare two floats and set flag register for jump (ucomiss)
|
||||
*/
|
||||
InstructionARM64 cmp_flt_flt(Register a, Register b);
|
||||
InstructionARM64 cmp_f32_f32(Register a, Register b);
|
||||
|
||||
InstructionARM64 sqrts_xmm(Register dst, Register src);
|
||||
InstructionARM64 sqrt_f32(Register dst, Register src);
|
||||
|
||||
/*!
|
||||
* Multiply two floats in xmm's
|
||||
*/
|
||||
InstructionARM64 mulss_xmm_xmm(Register dst, Register src);
|
||||
InstructionARM64 mul_f32_f32(Register dst, Register src);
|
||||
|
||||
/*!
|
||||
* Divide two floats in xmm's
|
||||
*/
|
||||
InstructionARM64 divss_xmm_xmm(Register dst, Register src);
|
||||
InstructionARM64 div_f32_f32(Register dst, Register src);
|
||||
|
||||
/*!
|
||||
* Subtract two floats in xmm's
|
||||
*/
|
||||
InstructionARM64 subss_xmm_xmm(Register dst, Register src);
|
||||
InstructionARM64 sub_f32_f32(Register dst, Register src);
|
||||
|
||||
/*!
|
||||
* Add two floats in xmm's
|
||||
*/
|
||||
InstructionARM64 addss_xmm_xmm(Register dst, Register src);
|
||||
InstructionARM64 add_f32_f32(Register dst, Register src);
|
||||
|
||||
/*!
|
||||
* Floating point minimum.
|
||||
*/
|
||||
InstructionARM64 minss_xmm_xmm(Register dst, Register src);
|
||||
InstructionARM64 min_f32_f32(Register dst, Register src);
|
||||
|
||||
/*!
|
||||
* Floating point maximum.
|
||||
*/
|
||||
InstructionARM64 maxss_xmm_xmm(Register dst, Register src);
|
||||
InstructionARM64 max_f32_f32(Register dst, Register src);
|
||||
|
||||
/*!
|
||||
* Convert GPR int32 to XMM float (single precision)
|
||||
*/
|
||||
InstructionARM64 int32_to_float(Register dst, Register src);
|
||||
InstructionARM64 int32_to_f32(Register dst, Register src);
|
||||
|
||||
/*!
|
||||
* Convert XMM float to GPR int32(single precision) (truncate)
|
||||
*/
|
||||
InstructionARM64 float_to_int32(Register dst, Register src);
|
||||
InstructionARM64 f32_to_int32(Register dst, Register src);
|
||||
|
||||
InstructionARM64 nop();
|
||||
|
||||
|
||||
@@ -75,6 +75,16 @@ constexpr Field Imm12(u32 x) {
|
||||
return Field{(static_cast<uint32_t>(x) & 0b111111111111) << 10};
|
||||
}
|
||||
|
||||
constexpr Field Imm26(u32 x) {
|
||||
ASSERT(x >= 0 && x <= ((2 ^ 26) - 1));
|
||||
return Field{(static_cast<uint32_t>(x) & 0b11111111111111111111111111) << 0};
|
||||
}
|
||||
|
||||
constexpr Field Imm19(u32 x) {
|
||||
ASSERT(x >= 0 && x <= ((2 ^ 19) - 1));
|
||||
return Field{(static_cast<uint32_t>(x) & 0b1111111111111111111) << 5};
|
||||
}
|
||||
|
||||
constexpr Field Imms(u32 x) {
|
||||
ASSERT(x >= 0 && x <= ((2 ^ 6) - 1));
|
||||
return Field{(static_cast<uint32_t>(x) & 0b111111) << 10};
|
||||
@@ -84,6 +94,11 @@ constexpr Field Immr(u32 x) {
|
||||
ASSERT(x >= 0 && x <= ((2 ^ 6) - 1));
|
||||
return Field{(static_cast<uint32_t>(x) & 0b111111) << 16};
|
||||
}
|
||||
|
||||
constexpr Field Cond(u32 x) {
|
||||
ASSERT(x >= 0 && x <= ((2 ^ 4) - 1));
|
||||
return Field{(static_cast<uint32_t>(x) & 0b1111) << 0};
|
||||
}
|
||||
} // namespace ARM64
|
||||
|
||||
struct InstructionARM64 : InstructionImpl<InstructionARM64> {
|
||||
|
||||
Reference in New Issue
Block a user