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arm64: dts: qcom: sdm845: Add i2c-qcom-cci node

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The sdm845 SOC ships with a CCI controller, which
has two CCI/I2C buses.

Signed-off-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20200324155843.10719-4-robert.foss@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This commit is contained in:
Robert Foss
2020-03-24 16:58:39 +01:00
committed by Bjorn Andersson
parent 39e0ce6cd1
commit 07484de372
2 changed files with 96 additions and 0 deletions
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4
arch/arm64/boot/dts/qcom/sdm845-db845c.dts
View File

@@ -866,3 +866,7 @@
bias-pull-up;
};
};
&cci {
status = "ok";
};

92
arch/arm64/boot/dts/qcom/sdm845.dtsi
View File

@@ -5,6 +5,7 @@
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
*/
#include <dt-bindings/clock/qcom,camcc-sdm845.h>
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
#include <dt-bindings/clock/qcom,gpucc-sdm845.h>
@@ -1813,6 +1814,42 @@
gpio-ranges = <&tlmm 0 0 150>;
wakeup-parent = <&pdc_intc>;
cci0_default: cci0-default {
/* SDA, SCL */
pins = "gpio17", "gpio18";
function = "cci_i2c";
bias-pull-up;
drive-strength = <2>; /* 2 mA */
};
cci0_sleep: cci0-sleep {
/* SDA, SCL */
pins = "gpio17", "gpio18";
function = "cci_i2c";
drive-strength = <2>; /* 2 mA */
bias-pull-down;
};
cci1_default: cci1-default {
/* SDA, SCL */
pins = "gpio19", "gpio20";
function = "cci_i2c";
bias-pull-up;
drive-strength = <2>; /* 2 mA */
};
cci1_sleep: cci1-sleep {
/* SDA, SCL */
pins = "gpio19", "gpio20";
function = "cci_i2c";
drive-strength = <2>; /* 2 mA */
bias-pull-down;
};
qspi_clk: qspi-clk {
pinmux {
pins = "gpio95";
@@ -3194,6 +3231,61 @@
#reset-cells = <1>;
};
cci: cci@ac4a000 {
compatible = "qcom,sdm845-cci";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x0ac4a000 0 0x4000>;
interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
power-domains = <&clock_camcc TITAN_TOP_GDSC>;
clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
<&clock_camcc CAM_CC_SOC_AHB_CLK>,
<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
<&clock_camcc CAM_CC_CPAS_AHB_CLK>,
<&clock_camcc CAM_CC_CCI_CLK>,
<&clock_camcc CAM_CC_CCI_CLK_SRC>;
clock-names = "camnoc_axi",
"soc_ahb",
"slow_ahb_src",
"cpas_ahb",
"cci",
"cci_src";
assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
<&clock_camcc CAM_CC_CCI_CLK>;
assigned-clock-rates = <80000000>, <37500000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cci0_default &cci1_default>;
pinctrl-1 = <&cci0_sleep &cci1_sleep>;
status = "disabled";
cci_i2c0: i2c-bus@0 {
reg = <0>;
clock-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
};
cci_i2c1: i2c-bus@1 {
reg = <1>;
clock-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
};
};
clock_camcc: clock-controller@ad00000 {
compatible = "qcom,sdm845-camcc";
reg = <0 0x0ad00000 0 0x10000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
mdss: mdss@ae00000 {
compatible = "qcom,sdm845-mdss";
reg = <0 0x0ae00000 0 0x1000>;