ARM: dts: at91: sama7g5ek: Add QSPI0 node
QSPI0 comunicates with a MX66LM1G45G SPI NOR flash. Enable the controller and describe the flash. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20211209123643.341892-2-tudor.ambarus@microchip.com
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committed by
Nicolas Ferre
parent
0081a525ce
commit
078c2a0e8e
@@ -13,6 +13,7 @@
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#include "sama7g5.dtsi"
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#include <dt-bindings/mfd/atmel-flexcom.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/pinctrl/at91.h>
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/ {
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model = "Microchip SAMA7G5-EK";
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@@ -134,6 +135,59 @@
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cpu-supply = <&vddcpu>;
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};
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&qspi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_qspi>;
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status = "okay";
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flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <133000000>;
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spi-tx-bus-width = <8>;
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spi-rx-bus-width = <8>;
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m25p,fast-read;
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at91bootstrap@0 {
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label = "ospi: at91bootstrap";
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reg = <0x0 0x40000>;
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};
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bootloader@40000 {
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label = "ospi: bootloader";
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reg = <0x40000 0xc0000>;
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};
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bootloaderenvred@100000 {
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label = "ospi: bootloader env redundant";
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reg = <0x100000 0x40000>;
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};
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bootloaderenv@140000 {
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label = "ospi: bootloader env";
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reg = <0x140000 0x40000>;
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};
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dtb@180000 {
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label = "ospi: device tree";
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reg = <0x180000 0x80000>;
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};
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kernel@200000 {
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label = "ospi: kernel";
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reg = <0x200000 0x600000>;
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};
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rootfs@800000 {
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label = "ospi: rootfs";
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reg = <0x800000 0x7800000>;
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};
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};
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};
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&dma0 {
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status = "okay";
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};
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@@ -555,6 +609,25 @@
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bias-disable;
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};
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pinctrl_qspi: qspi {
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pinmux = <PIN_PB12__QSPI0_IO0>,
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<PIN_PB11__QSPI0_IO1>,
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<PIN_PB10__QSPI0_IO2>,
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<PIN_PB9__QSPI0_IO3>,
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<PIN_PB16__QSPI0_IO4>,
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<PIN_PB17__QSPI0_IO5>,
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<PIN_PB18__QSPI0_IO6>,
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<PIN_PB19__QSPI0_IO7>,
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<PIN_PB13__QSPI0_CS>,
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<PIN_PB14__QSPI0_SCK>,
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<PIN_PB15__QSPI0_SCKN>,
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<PIN_PB20__QSPI0_DQS>,
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<PIN_PB21__QSPI0_INT>;
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bias-disable;
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slew-rate = <0>;
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atmel,drive-strength = <ATMEL_PIO_DRVSTR_HI>;
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};
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pinctrl_sdmmc0_default: sdmmc0_default {
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cmd_data {
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pinmux = <PIN_PA1__SDMMC0_CMD>,
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