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arm64: dts: qcom: sc8180x: correct dispcc clocks

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Correct the clocks being used by the display clock controller on the
SC8180X platform (to match the schema):
- Drop the sleep clock
- Add DSI clocks
- Reorder eDP / DP clocks

This changes the order of clocks, however it should be noted that the
clock list was neither correct nor followed the schema beforehand.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240512-typec-fix-sm8250-v4-2-ad153c747a97@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Dmitry Baryshkov
2024-05-12 01:04:08 +03:00
committed by Bjorn Andersson
parent 98a0c4f227
commit 17944fd55b
1 changed files with 14 additions and 8 deletions
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22
arch/arm64/boot/dts/qcom/sc8180x.dtsi
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@@ -3303,21 +3303,27 @@
compatible = "qcom,sc8180x-dispcc";
reg = <0 0x0af00000 0 0x20000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&sleep_clk>,
<&mdss_dsi0_phy 0>,
<&mdss_dsi0_phy 1>,
<&mdss_dsi1_phy 0>,
<&mdss_dsi1_phy 1>,
<&usb_prim_dpphy 0>,
<&usb_prim_dpphy 1>,
<&usb_sec_dpphy 0>,
<&usb_sec_dpphy 1>,
<&edp_phy 0>,
<&edp_phy 1>;
<&edp_phy 1>,
<&usb_sec_dpphy 0>,
<&usb_sec_dpphy 1>;
clock-names = "bi_tcxo",
"sleep_clk",
"dsi0_phy_pll_out_byteclk",
"dsi0_phy_pll_out_dsiclk",
"dsi1_phy_pll_out_byteclk",
"dsi1_phy_pll_out_dsiclk",
"dp_phy_pll_link_clk",
"dp_phy_pll_vco_div_clk",
"dptx1_phy_pll_link_clk",
"dptx1_phy_pll_vco_div_clk",
"edp_phy_pll_link_clk",
"edp_phy_pll_vco_div_clk";
"edp_phy_pll_vco_div_clk",
"dptx1_phy_pll_link_clk",
"dptx1_phy_pll_vco_div_clk";
power-domains = <&rpmhpd SC8180X_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
#clock-cells = <1>;